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M74HCT74
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
■ HIGH SPEED :
f
= 48MHz (TYP.) at VCC = 4.5V
MAX
■ LOW POWER DISSIPATION:
=2µA(MAX.) at TA=25°C
I
CC
■ COMPAT I B LE WITH TT L OUTPUTS :
V
= 2V (MIN.) VIL = 0.8V (MAX)
IH
■ BALANCED PROPAGATION DELAYS:
t
≅ t
PLH
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
■ PIN AND FUNCTION COMPATIBLE WITH
PHL
| = IOL = 4mA (MIN)
74 SERIES 74
DESCRIPTION
The M74HCT74 is an high spee d CMO S DUAL D
TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C
2
MOS technology.
A signal on the D INPUT (nD) is transferred on the
Q OUTPUT during t he positive going t ransition of
the clock pulse. CLEAR (CLR
) and PRESET (PR)
are independent of the clock and accomplished by
a low on the appropriate input.
TSSOPDIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP M74HCT74B1R
SOP M74HCT74M1R M74HCT74RM13TR
TSSOP M74HCT74TTR
The M74HCT74 is designed to directly interface
2
HSC
MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10August 2001
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M74HCT74
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1,13 1CLR
2, 12 1D, 2D Data Inputs
3, 11 1CK, 2CK
4, 10 1PR
5, 9 1Q, 2Q True Flip-Flop Outputs
6, 8 1Q
7 GND Ground (0V)
14 Vcc Positive Supply Voltage
TRUTH TABLE
, 2CLR
, 2PR
, 2Q
Asynchronous Reset Direct Input
Clock Input
(LOW-to-HIGH,
Edge-Triggered)
Asynchronous Set - Direct
Input
Complement Flip-Flop
Outputs
INPUTS OUTPUTS
CLR
L H X X L H CLEAR
H L X X H L PRESET
L L X X H H ----
H H L L H ---H H H H L ---HHX
X : Don’t Care
PR DCKQ Q
Q
n
Q
n
LOGIC DIAGRAM
FUNCTION
NO CHANGE
This log i c diagram has not be used to esti m ate propagation delays
2/10
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M74HCT74
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
V
T
t
r
Supply Voltage
CC
DC Input Voltage -0.5 to VCC + 0.5
I
DC Output Voltage -0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Power Dissipation
D
Storage Temperature
stg
Lead Temperature (10 sec)
L
°C; derate to 300mW by 10mW/°C from 65°C to 85°C
Supply Voltage
CC
Input Voltage 0 to V
I
Output Voltage 0 to V
O
Operating Temperature
op
, t
Input Rise and Fall Time (VCC = 4.5 to 5.5V)
f
-0.5 to +7 V
± 20 mA
± 20 mA
± 25 mA
± 50 mA
500(*) mW
-65 to +150 °C
300 °C
4.5 to 5.5 V
CC
CC
-55 to 125 °C
0 to 500 ns
V
V
V
V
DC SPECIFICATIONS
Symbol Parameter
V
V
V
V
I
∆ I
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
I
Input Leakage
I
Current
Quiescent Supply
CC
Current
Additional Worst
CC
Case Supply
Current
Test Condition Value
T
= 25°C
V
CC
(V)
A
Min. Typ. Max. Min. Max. Min. Max.
4.5
to
2.0 2.0 2.0 V
5.5
4.5
to
0.8 0.8 0.8 V
5.5
4.5
4.5
5.5
5.5
IO=-20 µA
I
=-4.0 mA
O
IO=20 µA
I
=4.0 mA
O
= VCC or GND
V
I
V
= VCC or GND
I
5.5 Per Input pin
= 0.5V or
V
I
V
= 2.4V
I
4.4 4.5 4.4 4.4
4.18 4.31 4.13 4.10
0.0 0.1 0.1 0.1
0.17 0.26 0.33 0.40
± 0.1 ± 1 ± 1 µA
2.0 2.9 3.0 mA
Other Inputs at
V
or GND
CC
I
= 0
O
-40 to 85°C -55 to 125°C
Unit
V
V
22040µA
3/10