SGS Thomson Microelectronics M74HC595 Datasheet
M54HC595
M74HC595
8 BIT SHIFT REGISTERWITH OUTPUT LATCHES (3 STATE)
.HIGH SPEED
f
= 55 MHz (TYP.) AT VCC=5V
MAX
.LOWPOWER DISSIPATION
ICC=4µA(MAX.) AT TA=25°C
.HIGH NOISEIMMUNITY
V
NIH=VNIL
.OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS FOR QA TO QH
10 LSTTL LOADS FOR QH’
=28%VCC(MIN.)
B1R
(PlasticPackage)
F1R
(CeramicPackage)
.SYMMETRICAL OUTPUT IMPEDANCE
|IOH|=IOL=6 mA(MIN.) FOR QA TOQH
|IOH|=IOL=4 mA(MIN.) FOR QH’
.BALANCEDPROPAGATION DELAYS
t
PLH=tPHL
.WIDE OPERATING VOLTAGERANGE
VCC(OPR)= 2V TO 6 V
.PIN AND FUNCTION COMPATIBLE
WITH LSTTL54/74LS595
M1R
(MicroPackage)
ORDER CODES :
M54HC 595F1R M74H C595M1R
M74HC 595B1R M74HC5 95C1R
C1R
(Chip Carrier)
DESCRIPTION
The M54/74HC595 is a high speed CMOS 8-BIT
SHIFT REGISTERS/OUTPUT LATCHES (3STATE) fabricated in silicon C2MOS technology. It
has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
This device contains an 8-bit serial-in, parallel-out
shift registerthat feeds an 8-bit D-type storageregister.The storage register has 8 3-STATE outputs.
Separate clocks are provided for both the shift registerand the storage register.
The shiftregister hasa direct-overriding clear,serial
input, and serial output (standard) pins for cascading. Both the shift register and storageregister use
positive-edge triggered clocks. If both clocks are
connected together, the shift register state will always be one clock pulse ahead of the storageregister.
All inputs are equipped with protection circuits
against static discharge and transient excess voltage.
PIN CONNECTIONS(top view)
NC =
No Internal
Connection
April1993
1/13
M54/M74HC595
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
INPUTS
SI SCK SCLR RCK G
X X X X H QA THRU QH OUTPUTS DISABLE
X X X X L QA THRU QH OUTPUTS ENABLE
X X L X X SHIFT REGISTER IS CLEARED
LHXX
HHXX
X H X X STATE OF S.R IS NOT CHANGED
X X X X S.R. DATA IS STORED INTO STORAGE REGISTER
X X X X STORAGE REGISTER STATE IS NOT CHANGED
X:DON’TCARE
FIRST STAGE OF S.R. BECOMES ”L” OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
FIRST STAGE OF S.R. BECOMES ”H” OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
OUTPUT
LOGIC DIAGRAM
2/13
LOGIC DIAGRAM
M54/M74HC595
TIMING CHART
3/13
M54/M74HC595
PIN DESCRIPTION
IEC LOGIC SYMBOL
PIN No SYMBOL NAME AND FUNCTION
1, 2, 3, 4, 5,
QA to QH Data Outputs
6, 7, 15
9 QH’ Serial Data Outputs
10 SCLR Shift Register Clear
Input
11 SCK Shift Register Clock
Input
13 G Output Enable Input
14 SI Serial Data Input
12 RCK Storage Register Clock
Input
8 GND Ground (0V)
16 V
CC
Positive Supply Voltage
ABSOLU TE M AXIMU M R AT INGS
Symbol Parameter Value Unit
V
CC
V
V
O
I
IK
I
OK
I
O
I
O
I
or I
CC
P
D
T
stg
T
AbsoluteMaximumRatingsarethosevaluesbeyond whichdamage tothedevicemayoccur.Functionaloperation under theseconditionisnotimplied.
(*)500 mW:≅ 65oC derate to 300 mWby 10mW/oC: 65oCto85oC
Supply Voltage -0.5 to +7 V
DC Input Voltage -0.5 to VCC+ 0.5 V
I
DC Output Voltage -0.5 to VCC+ 0.5 V
DC Input Diode Current ± 20 mA
DC Output Diode Current ± 20 mA
DC Output Current Per Output Pin QA-QH ± 35 mA
DC Output Current Per Output Pin QH’ ± 25 mA
DC VCCor Ground Current ± 70 mA
GND
Power Dissipation 500 (*) mW
Storage Temperature -65 to +150
Lead Temperature (10 sec) 300
L
o
C
o
C
RECO MM ENDED OPERAT I N G CO NDI TIONS
Symbol Parameter Value Unit
Supply Voltage 2 to 6 V
CC
Input Voltage 0 to V
I
Output Voltage 0 to V
O
Operating Temperature: M54HC Series
op
M74HC Series
CC
CC
-55 to +125
-40 to +85
Input Rise and Fall Time VCC= 2 V 0 to 1000 ns
V
= 4.5 V 0 to 500
CC
V
= 6 V 0 to 400
CC
4/13
V
T
t
V
V
r,tf
V
V
o
C
o
C
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