SGS Thomson Microelectronics M74HC40103, M74HC40102 Datasheet

M54/74HC40102

M54/74HC40103

8 STAGE PRE SETTABLE SYNCHR ONOUS DOWN COUNTE RS

.HIGH SPEED

f

= 40 MHz (TYP.) at VCC=5V

MAX

.LOWPOWER DISSIPATION

ICC=4µA(MAX.) at TA=25°C

.HIGH NOISE IMMUNITY

V

NIH=VNIL

.OUTPUT DRIVE CAPABILITY

10 LSTTLLOADS

=28%VCC(MIN.)

B1R

(PlasticPackage)

F1R

(CeramicPackage)

.SYMMETRICAL OUTPUT IMPEDANCE

|IOH|=IOL=4 mA (MIN.)

.BALANCEDPROPAGATION DELAYS

t

PLH=tPHL

.WIDE OPERATINGVOLTAGERANGE

VCC(OPR)= 2 V to 6 V

.PIN AND FUNCTION COMPATIBLE WITH

40102B/40103B

M1R

(MicroPackage)

ORDER CODES :

M54HCXXXXXF1R M74HCXXXXXM1 R
M74HCXXXXXB1R M74HCXXXXX C1R

C1R

(Chip Carrier)

DESCRIPTION

The M54/74HC40102/40103 are highspeedCMOS
8-STAGE PRESETTABLE SYNCHRONOUS
DOWN COUNTERS fabricated with silicon gate
C2MOS technology. They achieve the high speed
operation similar to equivalent LSTTL while main­tainingthe CMOS low powerdissipation.

The HC40102,and HC40103 consistof an 8-stage
synchronous down counter with a single output
which is activewhen the internalcountis zero. The
HC40102is configured as two cascaded 4-bit BCD
counters, and the HC40103 contains a single 8-bit
binarycounter. Eachtype hascontrol inputs for en­ablingordisabling theclock,forclearing thecounter
toitsmaximum count,andforpresettingthecounter
eithersynchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT out­put are active-low logic. In normal operation, the
counter isdecremented byonecount on eachposi­tive transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/CE)
input is high. The CARRY-OUT/ZERO-DETECT
(CO/ZD) output goes low when the count reaches
zero if the CI/CE input is low, and remains low for
one full clock period. When the SYNCHRONOUS
PRESET-ENABLE (SPE) input is low,data at the J
inputis clockedintothe counteron the nextpositive
clocktransition regardless of the state of the CI/CE
input.

PIN CONNECTIONS (top view)

NC =
No Internal
Connection

March1993

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M54/M74HC40102/40103

DESCRIPTION (Continued)

When the ASYNCHRONOUS PRESET-ENABLE
(APE)input islow,data attheJ inputsisasynchron­ouslyforced into the counter regardless ofthe state
of theSPE, CI/CE, or CLOCK inputs.J Inputs J0-J7
representtwo4-bit BCDwordsfortheHC40102and
a single 8-bit binary word for the HC40103. When
the CLEAR (CLR input is low, the counter is asyn­chronously cleared to its maximum count (9910for
the HC40102 and 25510for the HC40103 regard-

relationship between control inputis indicated in the
truthtable. Ifall control inputsarehighat thetime of
zero count, the counters will jump to the maximum
count, giving a counting sequence of 100 pr 256
clockpulseslong. The HC40102and HC40103 may
be cascaded usingthe CI/CEinput and the CO/ZD
output, in either a synchronous or ripple mode. All
inputs are equipped with protection circuits against
static discharge and transient excessvoltage.

less of thestateof any other input. The precedence

TRUTH TABLE

CONTROL INPUTS

CLEAR APE SPE CI/CE

H H H H COUNT INHIBIT EVEN IF CLOCK IS GIVEN, NO COUNT IS

H H H L REGULAR COUNT DOWN COUNT AT RISING EDGE OF CLOCK
H H L X SYNCHRONOUS PRESET DATA OF PI TERMINAL IS PRESET AT

H L X X ASYNCRONOUS PRESET DATA PF PI TERMINAL IS

L X X X CLEAR COUNTER IS SET TO MAXIMUM COUNT

X: DON’TCARE - MAXIMUM COUNT:”99” FOR HC40102 AND ”255”: FOR HC40103

MODE FUNCTIONAL DESCRIPTION

MADE

RISING EDGE OF CLOCK

ASYNCHRONOUSLY PRESET TO CLOCK

LOGIC DIAGRAM (HC40102)

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LOGIC DIAGRAM (HC40103)

M54/M74HC40102/40103

TIMING CHART

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M54/M74HC40102/40103

PIN No SYMBOL NAME AND FUNCTION

1 CLOCK CLock Input (LOW to

HIGH edge triggered)

2 CLEAR Asynchronous Master

Reset Input (Active LOW)

3 CI/CE Terminal Enable Input

4, 5, 6, 7, 10,

11, 12, 13

9 APE Asynchronous Preset

14 CO/ZD Terminal Count Output

15 SPE Synchronous Preset

8 GND Ground (0V)

16 V

IEC LOGIC SYMBOLS

J0 to J9 Jam Inputs

Enable Input (Active LOW)

(Active LOW)

Enable Input (Active LOW)

CC

Positive Supply Voltage

HC4 0102 HC401 03

INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTION

ABSOLU TE M AXI MUM R AT I NG S

Symbol Parameter Value Unit

V

CC

V

V

O

I

IK

I

OK

I

O

I

or I

CC

P

D

T

stg

T

AbsoluteMaximumRatingsarethosevalues beyondwhichdamage tothedevicemayoccur.Functionaloperationunder thesecondition isnotimplied.
(*)500 mW:≅ 65oC derate to 300 mWby 10mW/oC: 65oCto85oC

4/14

Supply Voltage -0.5 to +7 V
DC Input Voltage -0.5 to VCC+ 0.5 V

I

DC Output Voltage -0.5 to VCC+ 0.5 V
DC Input Diode Current ± 20 mA
DC Output Diode Current ± 20 mA
DC Output Source Sink Current Per Output Pin ± 25 mA
DC VCCor Ground Current ± 50 mA

GND

Power Dissipation 500 (*) mW
Storage Temperature -65 to +150
Lead Temperature (10 sec) 300

L

o

C

o

C

M54/M74HC40102/40103

RECO MM ENDED OPERAT IN G CO NDITIO NS

Symbol Parameter Value Unit

V

V

V

T

t

r,tf

DC SPECIFICATIONS

Symbol Parameter

V

IH

V

V

OH

V

OL

I

I

CC

Supply Voltage 2 to 6 V

CC

Input Voltage 0 to V

I

Output Voltage 0 to V

O

Operating Temperature: M54HC Series

op

M74HC Series

CC
CC

-55 to +125

-40 to +85

Input Rise and Fall Time VCC= 2 V 0 to 1000 ns

V

= 4.5 V 0 to 500

CC

V

= 6 V 0 to 400

CC

Test Conditions Value

V

(V)

CC

=25oC

T

A

54HC and 74HC

-40 to 85oC
74HC

-55 to 125oC

Min. Typ. Max. Min. Max. Min. Max.

High Level Input
Voltage

2.0 1.5 1.5 1.5

4.5 3.15 3.15 3.15

6.0 4.2 4.2 4.2

Low Level Input

IL

Voltage

2.0 0.5 0.5 0.5

4.5 1.35 1.35 1.35

6.0 1.8 1.8 1.8

High Level
Output Voltage

Low Level Output
Voltage

Input Leakage

I

Current
Quiescent Supply

2.0
V

=

I

4.5 4.4 4.5 4.4 4.4

6.0 5.9 6.0 5.9 5.9

4.5 I

6.0 I

2.0

4.5 0.0 0.1 0.1 0.1

6.0 0.0 0.1 0.1 0.1

4.5 I

6.0 I

6.0

IO=-20 µA

V

IH

or

V

IL

=-4.0 mA 4.18 4.31 4.13 4.10

O

=-5.2 mA 5.68 5.8 5.63 5.60

O

V

=

I

IO=20µA

V

IH

or

V

IL

= 4.0 mA 0.17 0.26 0.33 0.40

O

= 5.2 mA 0.18 0.26 0.33 0.40

O

VI=VCCor GND ±0.1 ±1 ±1 µA

1.9 2.0 1.9 1.9

0.0 0.1 0.1 0.1

6.0 VI=VCCor GND 4 40 80 µA

Current

54HC

V
V

o

C

o

C

Unit

V

V

V

V

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