.HIGH SPEED
f
= 84 MHz (TYP.) AT VCC=5V
MAX
.LOWPOWER DISSIPATION
ICC=4µA(MAX.) AT TA=25°C
.HIGH NOISE IMMUNITY
V
NIH=VNIL
=28%VCC(MIN.)
.OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.SYMMETRICALOUTPUT IMPEDANCE
|IOH|=IOL=4 mA (MIN.)
.BALANCEDPROPAGATION DELAYS
t
PLH=tPHL
.WIDE OPERATING VOLTAGERANGE
VCC(OPR)= 2 V TO 6 V
.PIN AND FUNCTION COMPATIBLE WITH
54/74LS390
M54HC390
M74HC390
DUAL DECADE COUNTER
B1R
(PlasticPackage)
M1R
(MicroPackage)
ORDER CODES :
M54HC 390F1R M74H C390M1R
M74HC 390B1R M74HC3 90C1R
F1R
(CeramicPackage)
C1R
(Chip Carrier)
DESCRIPTION
The M54/74HC390 is a high speed CMOS DUAL
DECADE COUNTER fabricated in silicon gate
C2MOStechnology.It hasthesamehighspeedperformance of LSTTL combined with true CMOS low
powerconsumption.
Thisdualdecade counter containstwo independent
ripple carry counters. Each counter is composed of
a divide-by-two and divide-by-five counter. The
divide-by-two and divide-by-five counters can be
cascaded to form dual decade, dual biquinary, or
various combinations up to a single divide-by-100
counter.
Each4-bit counter is incremented onthe hightolow
transition (negative edge) of the clock input, and
eachhas an independent clear input. When clearis
set low all four bits of each counter are set to low.
This enables count truncation and allows the implementation of divide-by-N counterconfigurations.
All inputs are equipped with protection circuits
against static discharge and transient excess voltage.
NC =
No InternalCon-
PIN CONNECTIONS (top view)
February 1993
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M54/M74HC390
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
COUNT
QD QC QB QA QA QD QC QB
0 LLLLLLLL
1 LLLHLLLH
2LLHLLLHL
3LLHHLLHH
4 LHLLLHLL
5LHLHHLLL
6LHHLHLLH
7 LHHHHLHL
8 HLLLHLHH
9 HLLHHHLL
BCD COUNT * BI-QUINARY **
OUTPUTS
INPUTS OUTPUTS
CLOCK A CLOCK B CLEAR QA QB QC QD
X X H LLLL
X L BINARY COUNT UP
X L QUINARY COUNT UP
Note: * Output QA is connected toinput CLOCK Bfor BCD count.
** OutputQD isconnected to inputCLOCKA forbi-quinary count.
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BLOCK DIAGRAM
LOGIC DIAGRAM
M54/M74HC390
3/13
M54/M74HC390
TIMING CHART
(1) BCDCOUNT SEQUENCE *
(2) BI-QUINARYCOUNT SEQUENCE**
*OUTPUTQA IS CONNECTEDTO INPUTCLOCK B
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