SGS Thomson Microelectronics M7020 Datasheet

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PRELIMINARY DATA

December 2001

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M7020R

32K x 68-bit Entry NETWORK SEARCH ENGINE

FEATURES SUMMARY

■ 32K DATA ENTRIES IN 68-BIT MODE

■ TABLE MAY BE PARTITIONED INTO UP TO

FOUR (4) QUADRANTS
(Data entry width in each oc tant is conf igurab le

as 34, 68, 136, or 272 bits.)

■ UP TO 83 MILLION SUSTAINED SEARCHES

PER SECOND IN 68-BIT and 136-BIT
CONFIGURATIONS

■ UP TO 41.5 MILLION SEARCHES PER

SECOND IN 34-BIT and 272-BIT
CONFIGURATIONS

■ SEARCHES ANY SUB-FIELD IN A SINGLE

CYCLE

■ OFFERS BIT-BY-BIT and GLOBAL MASKING

■ SYNCHRONOUS, PIPELINED OPERATION

■ UP TO 31 SEARCH ENGINES CASCADABLE

WITHOUT PERFORMANCE DEGRADATION

■ WHEN CASCADED, THE DATABASE

ENTRIES CAN SCALE FROM 248K TO 1984K
DEPENDING ON THE WIDTH OF THE ENTRY

■ GLUELESS INTERFACE TO INDUSTRY-

STANDARD SRAMS

■ SIMPLE HARDWARE INSTRUCTION

INTERFACE

■ IEEE 1149.1 TEST ACCESS PORT

■ OPER A T I NG SUPPLY VOLTAGES INCLUD E:

V

DD

(Operating Supply Voltage) = 1.8V

V

DDQ

(Operating Supply Voltage for I/O) = 2.5

or 3.3V

■ 272 PBGA, 27mm x 27mm

Figure 1. 272-ball PBGA Package

272-ball PBGA
27mm x 27mm

M7020R

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TABLE OF CONTENTS

DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Product Range (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Switch/Router Implementation Using the M7020R (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Signal Names (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Connections (Figure 3.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

M7020R Block Diagram (Figure 4.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Absolute Maximum Ratings (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DC and AC Measurement Conditions (Table 4.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

M7020R 2.5, or 3.3V AC Testing Load (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

M7020R 2.5, or 3.3V Input Waveform (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

M7020R 2.5, or 3.3V I/O Output Load Equivalent (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Capacitance (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

AC Timing Waveforms with CLK2X (Figure 8.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

AC Timing Parameters with CLK2X (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CMD Bus and DQ Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Database Entry (Data Array and Mask Array). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Arbitration Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Pipeline and SRAM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Full Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CONNECTION DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Clocks and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CMD and DQ Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SRAM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Cascade Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Clocks (CLK2X and PHS_L) (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1

Register Overview (Table 8.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Comparand Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Comparand Register Selection During SEA RCH and LEARN Instructions (Figure 10.). . . . . . . . . 22

Addressing the Global Masks Register Array (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SEARCH-Successful Registers (SSR[0:7]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SEARCH-Successful Register (SSR) Description (Table 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

The Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4

Command Register Field Descriptions (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

The Information Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Information Register Field Descriptions (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

The Read Burst Address Register (RBURREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

The Write Burst Address Register (WBURREG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

The NFA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Read Burst Register Description (Table 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Write Burst Register Description (Table 13.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

NFA Register (Table 14.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

SEARCH ENGINE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Data and Mask Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7

M7020R Database Width Configuration (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Bit Position Match (Table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Multi-width Configuration Example (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

M7020R Data and Mask Array Addressing (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

COMMAND CODES AND PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Commands and Command Pa rameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Command Codes (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Command Parameters (Table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

READ COMMAND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Single Location READ Cycle Timing (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Burst READ of the Data and Mask Arrays (BLEN = 4) (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . 31

READ Command Parameters (Table 18.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Data and Mask Array, SRAM Read Address Format (Table 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . 32

READ Address Format for Internal Registers (Table 20.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

READ Address Format for Data and Mask Arrays (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

WRITE COMMAND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Single Location WRITE Cycle Timing (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Burst WRITE of the Data and Mask Arrays (BLEN = 4) (Figure 18.). . . . . . . . . . . . . . . . . . . . . . . . 35

(Single) WRITE Address Format for Data and Mask Arrays or SRAM (Table 22.) . . . . . . . . . . . . . 35

WRITE Address Format for Internal Registers (Table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

WRITE Address Format for Data and Mask Array (Burst Write) (Table 24.). . . . . . . . . . . . . . . . . . 36

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SEARCH COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

68-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Hardware Diagram for a Table with One Device (Figure 19.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Timing Diagram for a 68-bit Configuration SEARCH for One Device (Figure 20.) . . . . . . . . . . . . . 38

x68 Table with One Device (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, 1 Device (Table 25.). . . . . . 39

Shift of SSF and SSV from SADR (Table 26.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

68-bit SEARCH on Tables Configured as x68 Using up to Eight M7020R Devices . . . . . . . . . 40

Hit/Miss Assumption (Table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1

Hardware Diagram for a Table with Eight Devices (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

x68 Table with Eight Devices (Figure 23.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Timing Diagrams for x68 Using up to Eight M7020R Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

68-bit SEARCH For Device 0 (Figure 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

68-bit SEARCH For Device 1 (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

68-bit SEARCH For Device 7 (Last Device) (Figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 8 Devices (Table 28.) 46

Shift of SSF and SSV from SADR (Table 29.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

68-bit SEARCH on Tables Configured as x68 Using Up To 31 M7020R Devices. . . . . . . . . . . 46

Hit/Miss Assumption (Table 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7

Hardware Diagram for a Table with 31 Devices (Figure 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Hardware Diagram for a Block of Up To Eight Devices (Figure 28.). . . . . . . . . . . . . . . . . . . . . . . . 49

x68 Table with 31 Devices (Figure 29.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Timing Diagrams for x68 Using Up To 31 M7020R Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Each Device in Block Number 0 (Miss on Each Device) (Figure 30.). . . . . . . . . . . . . . . . . . . . 51

Each Device Above the Winning Device in Block Number 1 (Figure 31.). . . . . . . . . . . . . . . . .52

Globally Winning Device in Block Number 1 (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Devices Below the Winning Device in Block Number 1 (Figure 33.). . . . . . . . . . . . . . . . . . . . . 54

Devices Above the Winning Device in Block Number 2 (Figure 34.) . . . . . . . . . . . . . . . . . . . . 55

Globally Winning Device in Block Number 2 (Figure 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Devices Below the Winning Device in Block Number 2 (Figure 36.). . . . . . . . . . . . . . . . . . . . . 57

Devices Above the Winning Device in Block Number 3 (Figure 37.) . . . . . . . . . . . . . . . . . . . . 58

Globally Winning Device in Block Number 3 (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device). . . . . . . 60

Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) (Figure 40.). . . . . . . . . . . 61

Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 31 Devices . . . . . . . . 62

Shift of SSF and SSV from SADR (Table 32.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

136-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Hardware Diagram for a Table with 1 Device (Figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Timing Diagram for a 136-bit SEARCH for One Device (Figure 42.). . . . . . . . . . . . . . . . . . . . . . . . 64

x136 Table with One Device (Figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, 1 Device (Table 33.). . . . . 65

Shift of SSF and SSV from SADR (Table 34.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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136-bit Search on Tables Configured as x136 Using Up to Eight M7020R Devices . . . . . . . . 66

Hit/Miss Assumption (Table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7

Hardware Diagram for a Table with Eight Devices (Figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

x136 Table with Eight Devices (Figure 45.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Timing Diagrams for x136 Using Up to Eight M7020R Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

136-bit SEARCH for Device Number 0 (Figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

136-bit SEARCH for Device Number 1 (Figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

136-bit SEARCH for Device Number 7 (Last Device) (Figure 48.) . . . . . . . . . . . . . . . . . . . . . . 71

Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, Up to 8 Devices . . . . . . . . 72

Shift of SSF and SSV from SADR (Table 37.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

136-bit Search on Tables Configured as x136 Using Up to 31 M7020R Devices. . . . . . . . . . . 72

Hit/Miss Assumption (Table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3

Hardware Diagram for a Table with 31 Devices (Figure 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Har d w a re Dia g r a m for a Bl ock of Up to Eight Dev ices (Fig u r e 5 0 .) . . . . . . . . . . . . . . . . . . . . . . . . 75

x136 Table with 31 Devices (Figure 51.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Timing Diagrams for x136 Using Up to 31 M7020R Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Each Device in Block Number 0 (Miss on Each Device) (Figure 52.). . . . . . . . . . . . . . . . . . . . 77

Each Device Above the Winning Device in Block Number 1 (Figure 53.). . . . . . . . . . . . . . . . .78

Globally Winning Device in Block Number 1 (Figure 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Devices Below the Winning Device in Block Number 1 (Figure 55.). . . . . . . . . . . . . . . . . . . . . 80

Devices Above the Winning Device in Block Number 2 (Figure 56.) . . . . . . . . . . . . . . . . . . . . 81

Globally Winning Device in Block Number 2 (Figure 57.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Devices Below the Winning Device in Block Number 2 (Figure 58.). . . . . . . . . . . . . . . . . . . . . 83

Devices Above the Winning Device in Block Number 3 (Figure 59.) . . . . . . . . . . . . . . . . . . . . 84

Globally Winning Device in Block Number 3 (Figure 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device). . . . . . . 86

Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) (Figure 62.). . . . . . . . . . . 87

Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, Up to 31 Devices . . . . . . . 88

Shift of SSF and SSV from SADR (Table 40.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

272-bit SEARCH on Tables Configured as x272 Using a Single M7020R Device . . . . . . . . . . 88

Hardware Diagram for a Table with One Device (Figure 63.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Timing Diagram for a 272-bit SEARCH for One Device (Figure 64.). . . . . . . . . . . . . . . . . . . . . . . . 90

x272 Table with One Device (Figure 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, 1 Device. . . . . . . . . . 91

Shift of SSF and SSV from SADR (Table 42.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

272-bit SEARCH on Tables x272-configured Using Up to Eight M7020R Devices . . . . . . . . . 92

Hit/Miss Assumption (Table 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3

Hardware Diagram for a Table with Eight Devices (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

x272 Table with Eight Devices (Figure 67.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Timing Diagrams for x272-configured Using Up to Eight M7020R Devices . . . . . . . . . . . . . . . . . . 96

272-bit SEARCH for Device Number 0 (Figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

272-bit SEARCH for Device Number 1 (Figure 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

272-bit SEARCH for Device Number 7 (Last Device) (Figure 70.) . . . . . . . . . . . . . . . . . . . . . . 98

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, Up to 8 Devices . . . .99

Shift of SSF and SSV from SADR (Table 45.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

M7020R

6/150

272-bit Search on Tables Configured as x272 Using Up to 31 M7020R Devices. . . . . . . . . . . 99

Hit/Miss Assumption (Table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Hardware Diagram for a Table with 31 Devices (Figure 71.) . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Hardware Diagram for a Block of Up to Eight Devices (Figure 72.) . . . . . . . . . . . . . . . . . . . . . . . 102

x272 Table with 31 Devices (Figure 73.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Timing Diagrams for x272 Using Up to 31 M7020R Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Each Device in Block Number 0 (Miss on Each Device) (Figure 74.). . . . . . . . . . . . . . . . . . . 104

Each Device Above the Winning Device in Block Number 1 (Figure 75.). . . . . . . . . . . . . . . .105

Globally Winning Device in Block Number 1 (Figure 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Devices Below the Winning Device in Block Number 1 (Figure 77.). . . . . . . . . . . . . . . . . . . . 107

Devices Above the Winning Device in Block Number 2 (Figure 78.) . . . . . . . . . . . . . . . . . . . 108

Globally Winning Device in Block Number 2 (Figure 79.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Devices Below the Winning Device in Block Number 2 (Figure 80.). . . . . . . . . . . . . . . . . . . . 110

Devices Above the Winning Device in Block Number 3 (Figure 81.) . . . . . . . . . . . . . . . . . . . 111

Globally Winning Device in Block Number 3 (Figure 82.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device). . . . . . 113

Last Device in Block Number 3 (Device 30 in the Table) (Figure 84.) . . . . . . . . . . . . . . . . . . 114

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, Up to 31 Devices . . 115

Shift of SSF and SSV from SADR (Table 48.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

MIXED SEARCHES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Tables Configured with Different Widths Using an M7020R . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Timing Diagram for Mixed SEARCH for One Device (Figure 85.). . . . . . . . . . . . . . . . . . . . . . . . .116

Multi-Width Configurations Example (Figure 86.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

LRAM AND LDEV DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

LEARN COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Timing Diagram of LEARN: TLSZ = 00 (Figure 87.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Timing Diagram of LEARN: TLSZ = 01 (Except on the Last Device) (Figure 88.). . . . . . . . . . . . . 120

Timing Diagram of LEARN on Device 7: TLSZ = 01 (Figure 89.) . . . . . . . . . . . . . . . . . . . . . . . . .121

Latency of SRAM WRITE Cycle from Second Cycle of LEARN Instruction (Table 49.) . . . . . . . . 121

DEPTH-CASCADING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Depth-Cascading Up to Eight Devices (One Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Depth-Cascading Up to 31 Devices (4 Blocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Depth-Cascading to Generate a “FULL” Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Depth-Cascading to Form a Single Block (Figure 90.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Depth-Cascading Four Blocks (Figure 91.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

“FULL” Generation in a Cascaded Table (Figure 92.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SRAM ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

SRAM PIO Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

7/150

M7020R

SRAM READ with a Table of One Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Generating an SRAM Bus Address (Table 50.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

SRAM READ Access for One Device (Figure 93.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

SRAM READ with a Table of Up to Eight Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table with Eight Devices (Figure 94.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

SRAM READ Through Device 0 in a Block of Eight Devices (Figure 95.). . . . . . . . . . . . . . . . . . . 130

SRAM READ Timing for Device 7 in a Block of Eight Devices (Figure 96.) . . . . . . . . . . . . . . . . . 131

SRAM READ with a Table of Up to 31 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Table of 31 Devices Made of Four Blocks (Figure 97.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

SRAM READ Through Device 0 in a Bank of 31 Devices (Device 0 Timing) (Figure 98.) . . . . . . 134

SRAM READ Through Device 0 in a Bank of 31 Devices (Device 30 Timing) (Figure 99.) . . . . . 135

SRAM WRITE with a Table of One Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

SRAM WRITE Access for One Device (Figure 100.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

SRAM WRITE with a Table of Up to Eight Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table with Eight Devices (Figure 101.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

SRAM WRITE Through Device 0 in a Block of Eight Devices (Figure 102.). . . . . . . . . . . . . . . . . 140

SRAM WRITE Timing for Device 7 in a Block of Eight Devices (Figure 103.). . . . . . . . . . . . . . . . 141

SRAM WRITE with Table(s) of Up to 31 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Table of 31 Devices (Four Blocks) (Figure 104.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 0 Timing) (Figure 105.). . . . . 144

SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 30 Timing) (Figure 106.). . . . 145

JTAG (1149.1) TESTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Supported Operations (Table 51.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

TAP Device ID Register (Table 52.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

M7020R

8/150

DESCRIPTION
Overview

ST Microelectronics, Inc.’s M7020R Search En­gine incorporates patent-pending Associative Pro­cessing Technology™ (APT) and is designed to
be a high-performance, pipelined, synchronous,
32K-entry network database search engine. The
M7020R database entry size can be 68 bits, 136
bits, or 272 bits. In the 68-bit entry mode, the size
of the database is 32K entries. In the 136-bit
mode, the size of the database is 16K entries, and
in the 272-bit mode, the size of the database is 8K
entries. The M7020R is configurable to support
multiple databases with different entry sizes. The
34-bit entry table can be impleme nted using the
Global Mask Registers (GMRs) building-database
size of 64K entries with a single device.

Performance

The Search Engine can sustain 83 million transac­tions per second when the database is pro­grammed or configured as 68 or 136 bits. When
the database is programmed to have an entry size

of 34 or 272 bits, the Search Engine will perform at

41.5 million transactions per second. STM’s
M7020R can be used to accelerate network proto­cols such as Longest-prefix Match (CIDR), ARP,
MPLS, and other Layer 2, 3, and 4 protocols.

Applications

This high-speed, high-capacity Search Engine can
be deployed in a variety of networking and com­munications applications. The performance and
features of the M7020R make it attractive in appli­cations such as Enterprise LAN switches and rout­ers and broadband switching and/or routing
equipment supporting multiple data rates at OC –
48 and beyond. The Search Engine is designed to
be scalable in order to support network database
sizes to 1984K entries specifically for environ­ments that require large network policy databases.
Figure 4, page 11 shows the block diagram for the
M7020R device.

Tabl e 1. Product Rang e

Figure 2. Switch/Router Implemen tation Using the M7020R

Part Number

Operating

Supply Voltage

Operating I/O

V oltage

Speed Temperature Range

M7020R-083ZA1 1.8V 2.5 or 3.3V 83MHz Commercial
M7020R-066ZA1 1.8V 2.5 or 3.3V 66MHz Commercial
M7020R-050ZA1 1.8V 2.5 or 3.3V 50MHz Commercial

Program

Memory

Switch

Fabric

Switch

Processor

Network Line Interfaces

System Bus

Host

ASIC

SRAM

Bank

Search
Engine

AI04272

9/150

M7020R

Table 2. Signal Names

Note: 1. Signal types are: I = Input only; I/O = Input or Output; O = Output; and T = Tristate

2. “CLK” is an internal clock signal. Any reference to “ CLK Cycles” m eans one cycl e of CLK.

3. ACK and EOT Signal s require a weak, external pull-down resistor of 47 KΩ or 100 KΩ.

Symbol

Type

(1)

Description

Clocks and Reset

CLK2X I Master Clock
PHS_L I Phase
TEST I Test Input
RST_L I Re set

Command and DQ Bus

CMD[8:0] I Command Bus
CMDV I Command Valid
DQ[67:0] I/O Address/Data Bus

ACK

(4)

T READ Acknowledge

EOT

(4)

T End of Transfer

SSF T SEARCH Successful Flag

SSV T

SEARCH Successful Flag
Valid

SRAM Interface

SADR[21:0] T SRAM Address
CE_L T SRAM Chip Enable
WE_L T SRAM Write Enable
OE_L T SRAM Output Enable
ALE_L T Address Latch Enable

Cascade Interface

LHI[6:0] I Local Hit In
LHO[1:0] O Local Hit Out
BHI[2:0] I Block Hit In
BHO[2:0] O Block Hit Out
FULI[6:0] I Full In
FULO[1:0] O Full Out
FULL O Full Flag

Device Identification

ID[4:0] I Device Identification

Supplies

V

DD

n/a Chip Core Supply (1.8V)

V

DDQ

n/a

Chip I/O Supply (2.5 or

3.3V)

Test Access Port

TDI I

Test Access Port’s Test
Data In

TCK I

Test Access Port’s Test
Clock

TDO T

Test Access Port’s Test
Data Out

TMS I

Test Access Port’s Test
Mode Select

TRST_L I Test Access Port’s Reset

M7020R

10/150

Figure 3. Connections

SADR

8

SADR

13

SADR

11

SADR

14

SADR

17

SADR

20

SADR

10

SADR

19

SADR

18

SADR

21

SADR

15

SADR

5

SADR

6

SADR

7

SADR

9

SADR

12

SADR

16

SADR2SADR

1

SADR

3

SADR

0

SADR

4

GND

GND

GNDGNDGND

GND

GND

GNDGND

GND

GND

GNDGND

GNDGNDGND

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

FULL

EOTNC

NC

NC

NC

ACK

NC

NC

NC

NC

NC

NC

NC

NC

NC NC

NC

NC

NC NC

NC

NC

NC

NC

NC

NC

NC

LHI6

LHI5

LHI4

LHI1

LHO0

LHO1

BHI0BHO0

BHO1

BHO2

FULI0

FULI3

FULO0

FULO1 FULI2

FULI1FULI4FULI5

FULI6

BHI2

BHI1

LHI0

LHI2

LHI3

NC

NC

NC

NC

NC

NCNC

NC

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

CMD8

CMD7

CMD5

CMD4

CMD3

CMD1

CMD6

CMD2

CMD0

CMDV

DQ17

DQ15

DQ13DQ11

DQ9

DQ1

DQ5

DQ7

DQ21

DQ27

DQ31

DQ33

DQ29

DQ25

DQ23

DQ19

DQ35

DQ37

DQ43

DQ53

DQ57DQ61

DQ63

DQ67

DQ59

DQ55

DQ49

DQ64

DQ62

DQ60

DQ66

DQ58

DQ56

DQ50

DQ48

DQ46

DQ44

DQ42

DQ38

DQ30

DQ36

DQ32DQ34

DQ28

DQ20

DQ24

DQ22

DQ16

DQ18

DQ8 DQ0

DQ2 DQ4

DQ12

DQ10

DQ14

DQ6

DQ26

DQ40

DQ52

DQ54

DQ51

DQ45

DQ41

DQ39

DQ47

DQ65

DQ3

TDO

TMS

TCK

TDI

ID0

ID2

ID3

ID1

ID4

GND

GND

GND

GNDGND

GND

GND

GND

GND

GND GND

GNDCLK2X

WE_L

OE_L

AE_L

CE_L

PHS_L

SSF

SSV

RSTL

GND

T

RST_L

RIGHT

BOTTOM

LEFT

TOP

AI04270

11/150

M7020R

Figure 4. M7020R Block Diagram

AI04271

Comparand Registers[15:0]
Global Mask Registers [7:0]

Information and Command Register

Burst Read Register
Burst Write Register

Next Free Address Register

Search Successful Index Registers [7:0]

(All registers are 68-bit-wide)

TAP

Controller

Pipeline

and

SRAM

Control

Arbitration

Logic

Command

Decode

and PIO Access

Compare/PIO Data

PHS_L

CLK2X

RST_L

DQ [67:0]

CMD [8:0]

CMDV

ACK
EOT

Cmd

Compare/PIO Data

Address Decode

Priority Encode

Match Logic

Configurable as

64K x 34
32K x 68

16K x 136

8K x 272

Data Array

Configurable as

64K x 34
32K x 68

16K x 136

8K x 272

Mask Array

Full LogicFULL [6:0]

FULL

FULO [1:0]

ID [4:0]

LHI [6:0]
BHI [2:0]

SSF
SSV

LHO [1:0]

BHO [2:0]

TAP

SADR [21:0]

OE_L

WE_L

CE_L

ALE_L

M7020R

12/150

MAXIMUM RATIN G

Stressing the device ab ove the rating listed in t he

“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the dev ice at
these or any other conditions above those indicat­ed in the Operating sections of this specification is

not implied. Exposure to Absol ute Maxim um Ra t­ing conditions for extended periods may affect de­vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel­evant quality documents.

Table 3. Absolute Maximum Ratings

Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

Symbol Parameter Value Unit

T

STG

Storage Temperature (VDD Off)

–0 to 70 °C

T

SLD

(1)

Lead Solder Temperature for 10 seconds 235 °C

V

DD

VDD Operating Supply Voltage

1.9 V

V

DDQ

V

DDQ

Voltage for I/O (3.3V)

3.465 V

V

DDQ

V

DDQ

Voltage for I/O (2.5V)

2.6 V

I

O

Output Current 200 mA

P

D

Power Dissipation < 5 W

13/150

M7020R

DC AND AC PARAMETERS

This section summarizes the operat ing and mea­surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the M easure-

ment Conditions listed in the rel evant tables. De­signers should check that the operating conditions
in their projects match the measurement condi­tions when using the quoted parameters.

Table 4. DC and AC Measurement Conditions

Note: 1. Maximum al l owable applies to overshoot only (V

DDQ

is 3.3V supply).

2. Minimum allowable applies to undershoo t only.

Sym Parameter Min Max Units

V

DDVDD

Operating Supply Voltage

1.7 1.9 V

V

DDQVDDQ

Voltage for I/O (3.3V)

3.135 3.465 V

V

DDQVDDQ

Voltage for I/O (2.5V)

2.4 2.6 V

t

A

Ambient Operating Temperature 0 70 °C

Supply Voltage Tolerance –5 +5 %
Input Pulse Levels (V

DDQ

= 3.3V)

GND to 3.0 V

Input Pulse Levels (V

DDQ

= 2.5V)

GND to 2.5 V

Input Rise and Fall Times at 0.3V and 2.7V (V

DDQ

= 3.3V)

≤

2ns (see Figure 6, page 14) ns

Input Rise and Fall Times at 0.25V and 2.25V (V

DDQ

= 2.5V)

≤

2ns (see Figure 6, page 14) ns

Input Timing Reference Levels (V

DDQ

= 3.3V)

1.5 V

Input Timing Reference Levels (V

DDQ

= 2.5V)

1.25 V

Output Timing Reference Levels (V

DDQ

= 3.3V)

1.5 V

Output Timing Reference Levels (V

DDQ

= 2.5V)

1.25 V

Output Load (see Figure 5 and Figure 7, page 14) V

M7020R

14/150

Figure 5. M7020R 2.5, or 3.3V AC Testing Load

Figure 6. M7020R 2.5, or 3.3V Input Waveform

Figure 7. M7020R 2.5, or 3.3V I/O Output Load Equivalent

Note: 1. Output loading is specified with CL = 5pF as in Fig ure 7. Transit i on i s measured at ± 200 mV from s teady-stat e voltage.

2. The load used for V

OH

, VOL testing is shown in Figur e 7.

C

L

VL = 1.25V for V

DDQ

= 2.5V

VL = 1.50V for V

DDQ

= 3.3V

50ΩZ0 = 50Ω

D

OUT

AC Load

AI05653

+2.5V V

DDQ

= 2.5V /

+3.0V V

DDQ

= 3.3V

90%

10%

90%

10%

GND

AI04299

208Ω for V

DDQ

= 2.5V

158Ω for V

DDQ

= 3.3V

192Ω for V

DDQ

= 2.5V

175Ω for V

DDQ

= 3.3V

AI04266

5pF

Q

V

DDQ

For Hi-Z and VOL/V

OH

(1, 2)

15/150

M7020R

Table 5. Capacitance

Note: 1. Effective capacitance measured with power suppl y. Sampled only, not 100% tested.

2. At 25°C, f = 1MHz.

3. Outputs deselect ed.

Table 6. DC Characteristics

Note: 1. Valid for A m bi ent Operat in g T emperat ure: TA = 0 to 70°C; VDD = 1.5V.

Symbol Parameter

Test Condition

(1,2)

Min Max Unit

C

IN

Input Capacitance

V

IN

= 0V

6pF

C

IO

(3)

Output Capacitance

V

OUT

= 0V

6pF

Sym Parameter

Test Condition

(1)

Min Max Unit

I

LI

Input Leakage Current

V

DDQ

= V

DDQ

(max), VIN = 0 to V

DDQ

(max)

±10 µA

I

LO

Output Leakage Current

V

DDQ

= V

DDQ

(max), VIN = 0 to V

DDQ

(max)

±10 µA

V

IL

Input Low Voltage (V

DDQ

= 3.3V)

–0.3 0.8 V

V

IH

Input High Voltage (V

DDQ

= 3.3V)

2.0

V

DDQ

+ 0.3

V

V

IL

Input Low Voltage (V

DDQ

= 2.5V)

–0.3 0.7 V

V

IH

Input High Voltage (V

DDQ

= 2.5V)

1.7

V

DDQ

+ 0.3

V

V

OL

Output Low Voltage (V

DDQ

= 3.3V) V

DDQ

= V

DDQ

(min), IOL = 8mA

0.4 V

V

OH

Output High Voltage (V

DDQ

= 3.3V) V

DDQ

= V

DDQ

(min), IOH = 8mA

2.4 V

V

OL

Output Low Voltage (V

DDQ

= 2.5V) V

DDQ

= V

DDQ

(min), IOL = 8mA

0.4 V

V

OH

Output High Voltage (V

DDQ

= 2.5V) V

DDQ

= V

DDQ

(min), IOH = 8mA

2.0 V

I

DD1

1.8V Supply Current at VDD(max)

66MHz Search Rate 2300 mA
50MHz Search Rate 1800 mA

I

DD2

3.3V Supply Current at VDD(max)

66MHz Search Rate, I

OUT

= 0mA

200 mA

50MHz Search Rate, I

OUT

= 0mA

150 mA

I

DD2

2.5V Supply Current at VDD(max)

66MHz Search Rate, I

OUT

= 0mA

160 mA

50MHz Search Rate, I

OUT

= 0mA

120 mA

M7020R

16/150

Figure 8. AC Timing Waveforms with CLK2X

Cycle

1

Cycle

0

Cycle

2

Cycle

3

Cycle

4

Cycle

5

Cycle

7

Cycle

6

Cycle

8

Cycle

10

Cycle

12

Cycle

9

Cycle

11

CLK2X

Signal

Group 0

Signal

Group 2

Signal

Group 3

Signal

Group 4

Signal

Group 5

CLK

AI04265

Signal Group 0: PHS_L, RST_L
Signal Group 1: DQ, CMD, CMDV
Signal Group 2: LHI, BHI, FULI
Signal Group 3: LHO, BHO, FULO, FULL
Signal Group 4: SADR, CE_L, OE_L, WE_L, ALE_L, SSF, SSV
Signal Group 5: DQ, ACK, EOT

tICSCH

tCKHOV

tCKHSV

tCKHSHZ

tCKHSLZ

tCKHOV

tIHCH

tISCH

tCKHDZ

tCKHDV

Signal

Group 1

tICHCH

tIHCH

tISCH

tISCH

tIHCH

tIHCH

17/150

M7020R

Table 7. AC Timing Parameters with CLK2X

Note: 1. Valid for A m bi ent Operat in g T emperat ure: TA = 0 to 70°C; VDD = 1.8V.

2. Values are based on 50% signal lev el s.

3. Base d on an AC load of C L = 30pF (see Figure 5, Figure 6, and Figur e 7, page 14).

4. These parameters are sampl ed and not 100% tested, and are based on an AC lo ad of 5pF.

Row Symbol

M7020R-050 M7020R-066 M7020R-083

Unit

Description

(1)

Min Max Min Max Min Max

1

f

CLOCK

100 133 166 MHz CLK2X frequency

2

t

CLK

10 7.5 ns CLK2X period

3

t

CKHI

4.0 3.0 ns

CLK2X high pulse

(2)

4

t

CKLO

4.0 3.0 ns

CLK2X low pulse

(2

5

t

ISCH

2.5 2.5 2.5 ns

Input Setup Time to CLK2X rising edge.

(2)

6

t

IHCH

0.6 0.6 0.6 ns

Input Hold Time to CLK2X rising edge.

(2)

7

t

ICSCH

4.2 4.2 4.2 ns

Cascaded Input Setup Time to CLK2X rising
edge.

(2)

8

t

ICHCH

0.6 0.6 0.6 ns

Cascaded Input Hold Time to CLK2X rising
edge.

(2)

9

t

CKHOV

9.5 8.5 ns

Rising edge of CLK2X to LHO, FULO, BHO,
FULL valid.

(3)

10

t

CKHDV

10.0 9.0 ns

Rising edge of CLK2X to DQ valid.

(2)

11

t

CKHDZ

1.2 9.5 1.2 9.5 1.2 9.5 ns

Rising edge of CLK2X to DQ high-Z.

(4)

12

t

CKHSV

10.0 9.0 ns

Rising edge of CLK2X to SRAM Bus valid.

(2)

13

t

CKHSHZ

7.0 6.5 ns

Rising edge of CLK2X to SRAM Bus high­Z.

(2,4)

14

t

CKHSLZ

7.5 7.0 ns

Rising edge of CLK2X to SRAM Bus low­Z.

(2,4)

M7020R

18/150

OPERATION

The following subsections contain command
(CMD and DQ Bus (command and databus), data­base entry, arbitration logic, pipeline, and SRAM
control, and full logic descriptions.

CMD Bus and DQ Bus

CMD[8:0] carries the CMD and its associated pa­rameter. DQ[67:0] is used for data t ransfer to and
from the database en tries, wh ich com prise a dat a
and a mask fiel d that are organized a s data and
mask arrays. The DQ Bus carries the SEARCH
data (of the data and mask arrays and internal reg­isters) during the SEARCH command as well as
the address and data during READ and/or WRITE
operations. The DQ Bus can also carry the ad­dress information for the flow-through accesses to
the external SRAMs and/or SSRAMs.

Database Entry (Data Array and Mask Array)

Each database ent ry comprises a data and a mask

field. The resultant value of the entry is ’1,' ’0,’ or
’X (don’t care),’ depending on the value in the data
and mask bits. The on-chip priority encoder se­lects the first matching entry in the da tabase that
is nearest to location '0.'

Arbitrati on L ogi c

When multiple Search Engines are cascaded to
create large databases, the data being searched is
presented to all search engines simultaneously in
the cascaded system. If multiple matches occur
within the cascaded devices, arbitration log ic on
the search engin es w ill e nable the winning devic e
(with a matching entry that is closest to address “0”
of the cascaded database) to drive the SRAM bus.

Pipeline an d SR AM Control

Pipeline latency is added to give enough time to a
cascaded system’s arbitration logic to determ ine
the device that will drive the index of the matching
entry on the SRAM bus. Pipeline logic adds laten­cy to both the SRAM access c ycles and the SSF
and SSV signals to align them to the host ASIC re­ceiving the associated data.

Full Logic

Bit[0] in each of the 68-bit entries has a special
purpose for the LEARN command (0 = empty, 1 =
full). When all the data ent ries have bit[0] = 1, t he
database asserts the FULL Flag, indicating all the
search engines in the depth-cascade d array are
full.

19/150

M7020R

CONNECTION DESCRIPTIONS
Clocks and Reset
Master Clock (CLK2X). M7020R samples all the

data and control pins on the positive edge of
CLK2X. All signals are driven out of the device on
the rising edge of CLK2X (when PHS_L is low).

Phase (PHS_L). This signal runs at half the fre­quency of CLK2X and generates an internal CLK
from CLK2X see Figure 9, page 20.

Test Input (TEST - for Cypress Semiconductor
Use Only). This signal should be connected to

ground.
Reset (RST_L). Driving RS T_L low initial ize s the

device to a known state.

CMD and DQ Bus
CMD Bus (CMD[8:0]. [1:0] specifies the com-

mand; [8:2] contains the CMD parameters. The
descriptions of individual comm ands explains the
details of the parameters. The enc oding of com­mands based on the [1:0] field are:

– 00: PIO READ
– 01: PIO WRITE
– 10: SEARCH
–11: LEARN

CMD Valid (

CMDV). Qualifies the CMD bus:

– 0: No Command
– 1: Command

Address/Data Bus (

DQ[67:0]). This signal carries

the READ and WRITE address and data during
register, data, and mask array o perations. It car­ries the compare data during SEARCH opera­tions. It also carries the SRAM address during
SRAM PIO accesses.

READ Acknowledge (ACK). This signal indi­cates that valid data is available on the DQ Bus
during register, data, and mask array READ oper­ations, or the data is available on the SR AM data
bus during SRAM READ operations.

Note: ACK Signals require a weak external pull­down resistor such as 47 or 100 KΩ.

End of Transfe r (E OT) . This signal indicates the
end of burst transfer to the data or mask array dur­ing READ or WRITE burst operations.

Note: EOT Signals require a weak external pull­down resistor such as 47 KΩ or 100 KΩ.

SEARCH Successful Flag (SSF). When assert­ed, this signal indicates that the device is the glo­bal winner in a SEARCH operation.

SEARCH Successful Flag Valid (SSV). When
asserted, this signal qualifies the SSF signal.

SRAM Interface
SRAM Address (SADR[21:0]). This bus con-

tains address lines to access off-chip SRAMs that
contain associative data. See Tab le 50, page 127
for the details of the generated SRAM address. In
a database of multiple M7020Rs, each corre­sponding bit of SADR from all cascaded devices
must be connected.

SRAM Chip Enable (CE_L). This is chip ena ble
control for external SRAMs. In a database o f mul­tiple M7020Rs, CE_L of all cascaded devices
must be connected. This signal is then driven by
only one of the devices.

SRAM Write Enable (WE_L). This is write en­able control for external SRA M s. In a database of
multiple M7020Rs, WE_L of all cascaded devices
must be connected together. This signal is then
driven by only one of the devices.

SRAM Output Enable (OE_L). This is output en­able control for external SRAMs. Only the last de­vice drives this signal (with the LRAM bit set).

Address Latch Enable (ALE_L). When this sig­nal is low, the addresses are valid on the SR AM
Address Bus. In a database of multiple M7020Rs,
the ALE_L of all cascaded devices mu st be con­nected. This signal is then driven by only one of
the devices.

Cascade Interface
Local Hit In (LHI[6:0]). These pins depth-cas-

cade the device to form a larger table siz e. One
signal of this bus is c onnected to the LHO[1] or
LHO[0] of each of the upstream devices in a block.
All unused LHI pins are conn ected to a logic '0.'
(For more information, see DEPTH-CASCADING,
page 122.)

Local Hit Out (LHO[1:0]). LHO[1] and LHO[0]
are the same logical signal. LHO[1] or LHO[0] is
connected to one input of the LHI bus of up to four
downstream devices in a bl ock of up to ei ght de­vices. (For more information, see DEPTH-CAS­CADING, page 122.)

Block Hit In (BHI[2:0]). Inputs from t he previous
BHO[2:0] are tied to the BHI[2:0] of the current de­vice. In a four-block system, the last block can
contain only seven devices bec ause the ID code
11111 is used for broadcast access.

Block Hit Out (BHO[2:0]). These outputs from
the last device in a block are connected to the
BHI[2:0] inputs of the devices in the downstream
blocks.

Full In (FULI[6:0]). Each signal in this bus is con­nected to FULO[0] or FULO[1] of an upstream de­vice to generate the FULL signal for the depth­cascaded block.

M7020R

20/150

Full Out (FULO[1:0]). FULO[1] and FULO[0] are
the same logical signal. One of these two signals
must be connected to the FULI of up to four down­stream devices in a depth-casc aded table. Bit [0]
in the data array indicates if the entry is full (1) or
empty (0).This signal is asserted if all of the bits in
the data array are ’1s.’ Refer to Depth-Cascading

to Generate a “FULL” Signal, page 122.
Full Flag (FULL). When asserted, t his signal in-

dicates that the table consisting of many depth­cascaded devices is full .

Device Identification
Device Identification (ID[4:0]). The binary-en-

coded device ID for a depth-cascaded system
starts at 00000 and goes up to 11110. 11111 is re­served for a special broadcast address that se­lects all cascaded search engines in the system.

On a broadcast READ-only, the device with the
LDEV bit set to '1' responds.

Supplies
Chip Core Supply (V

DD

). This is equal to 1.8V.

Chip I/O Supply (V

DDQ

). This is equal to either

2.5 or 3.3V.

Test Access Port
Test Data In (TDI). This is the Test Access Port’s

Test Data In.
Test Clock (TCK). This is the Test Access Port’s

Test Clock.
Test Data Out (TDO). This is the Test Access

Port’s Test Data Out.
Test Mode Select (TMS). This is the Test Ac-

cess Port’ s T e st Mod e Select.
Test Reset (TRST_L). This is the Test Access

Port’s Test Reset.

CLOCKS

The M7020R receives the CLK2X and PHS_L sig­nals. It uses the PHS_L signal to divide CLK2X
and generate an internal clock (CLK), as shown in

Figure 9. The M7020R uses CLK2X and CLK for
internal operations.

Figure 9. Clocks (CLK2X and PHS_L)

Note: Any refe rence to “CLK Cycles” means 1 cycle of the signal, “CLK.”

1. “CLK” is an internal signal.

CLK2X

PHS_L

CLK

(1)

AI04750

21/150

M7020R

REGISTERS

All registers in the M 7020R are 6 8 bits wide. T he
M7020R contains 8 pairs of comparand storage
registers, 16 pairs of global mask registers
(GMRs), eight search successful index registers
and one each of CM D, information, burst READ,

burst WRITE, and next-free address registers. Ta­ble 8 provides an overview of all the M7020R reg­isters. The registers are ordered in ascending
address order. Each register group is then de­scribed in the following subsections.

Table 8. Register Overview

Address Abbreviation Type Name

0–31 C OMP0–31 R

16 Comparand Registers. Stores comparands from the DQ Bus for

learning later.
32–47 MASKS RW 8 Global Mask Registers Array.
48–55 SSR0–7 R 8 SEARCH Successful Index Registers.

56 COMMAND RW Command Register.
57 INFO R Information Register.
58 RBURREG RW Burst Read Register.
59 WBURREG RW Burst Write Register.
60 NFA R Next Free Address Register.

61–63 – – Reserved

M7020R

22/150

Comparand Registers

The device contains 3 2 68-bit comparand regis­ters (16 pairs) dynamically selected in every
SEARCH operation to store the comparand pre­sented on the DQ Bus. The LEARN command will
later use these registers when executed. The

M7020R stores the SEARCH command’s Cycle A
comparand in the even-numbered register and the
Cycle B comparand in the odd-numbered register,
as shown in Figure 10.

Mask Registers

The device contains 16 68-bit global mask regis­ters (8 pairs) dynamically selected in every
SEARCH operation to select the search subfield.
The addressing of these registers is explained in
Figure 11. The three-bit GMR Index supplied on
the CMD bus can apply 8 pairs of global masks
during the SEARCH and WRITE operations, as
shown in Figure 11.

Note: In 68-bit SEA RCH and WRITE opera tions,
the host ASIC must p rogram both the even and
odd mask registers with the same values.

Each mask bit in the GMRs is used during
SEARCH and WRITE operations. In SEARCH op­erations, setting the mask bit to '1' enables com­pares; setting the mask bit to '0' disables
compares (forced match) at the corresponding bit
position. In WRITE operations to the data or mask
array, setting the mask b it to '1' en ables WRITEs;
setting the mask bit to '0' disables W RITEs at the
corresponding bit position.

Figure 10. Comparand Register Selection

During SEARCH and LEARN
Instructions

Figure 11. Addressing the Global Masks

Register Array

135 0

6868

1

0

32
54

7

6

30 31

0

15

1

Address

Index

AI04275

135 0

6868

1

0

32
54

7

6

9

8

11

10

13

12

15

14

0
1

6
7

2

5

4

3

Address

Index

AI04276

SEARCH and WRITE Command

Global Mask Selection

23/150

M7020R

SEARCH-Successful Registers (SSR[0:7])

The device contains eight sea rch successful reg­isters (SSRs) to hold the index of the location
where a successful search occurred. The format of
each register is described in Table 9. The
SEARCH command specifies which SSR stores
the index of a specific SE ARCH comma nd in Cy­cle B of the SEARCH Instruction. Subsequently,
the host ASIC can u se this register to acc ess that

data array, mask array, or external SRAM using
the index as part of the indirect access address
(see Table 19, page 32 and Table 22, page 35)

.

The device with a valid bit set performs a READ or
WRITE operation. All other devices suppress the
operation.

Table 9. SEARCH-Successful Register (SSR) Description

Field Range Initial Value Description

INDEX [14:0] X

Index. This is the address of the 68-bit entry where a successful

search occurs. The device updates this field only when a search is

successful. If a hit occurs in a 136-bit entry-size quadrant, the LSB is

’0.’ If a hit occurs in a 272-bit entry size quadrant, the two LSBs are

’00.’ This index updates if the device is either a local or global winner

in a SEARCH operation.

– [30:15] 0 Reserved.

VALID [31] 0

Valid. During SEARCH operation in a depth-cascaded configuration,

the device that is a global winner in a match sets this bit to '1.' This bit

updates only when the device is a global winner in a SEARCH

operation.

– [67:32] 0 Reserved.

M7020R

24/150

The Command Register

Table 10. Command Register Field Descriptions

Field Range Initial Value Description

SRST [0] 0

Software Reset. If ’1,’ this bit resets the device, with the same effect

as the hardware reset. Internally, it generates a reset pulse lasting for

eight CLK cycles. This bit automatically resets to a ’0’ the reset cycle

has completed.

DEVE [1] 0

Device Enable. If ’0,’ it keeps the SRAM Bus (SADR, WE_L, CE_L,

OE_L, and ALE_L), SSF, and SSV signals in 3-state condition and

forces the cascade interface output signals LHO[1:0] and BHO[2:0] to

’0.’ It also keeps the DQ Bus in input mode. The purpose of this bit is

to make sure that there are no bus contentions when the devices

power up in the system.

TLSZ [3:2] 01

Table Size. The host ASIC must program this field to configure the

chips into a table of a certain size. This field affects the pipeline

latency of the SEARCH and LEARN operations as well as the READ

and WRITE accesses to the SRAM (SADR[21:0], CE_L, OE_L,

WE_L, ALE_L, SSV, SSF, and ACK). Once programmed, the search

latency stays constant.

TLSZ [3:2] 01

Latency in #

of CLK Cycles
00: 1 device 4
01: 2-8 devices 5
10: 9-31 devices 6
11: Reserved

HLAT [6:4] 000

Latency of Hit Signals. This field adds latency to the SSF and SSV
signals during SEARCH, and ACK signal during SRAM READ access
by the following number of CLK cycles.

000: 0 100: 4
001: 1 101: 5
010: 2 110: 6
011: 3 111: 7

LDEV [7] 0

Last Device in the Cascade. When set, this device is the last device
on the SRAM bus in the depth-cascaded table and is the default driver
for the SSF and SSV signals.
In the event of a SEARCH failure, the device with this bit set drives the
hit signals as follows:
SSF = 0, SSV = 1

During non-SEARCH cycles, the device with this bit set drives the
signals as follows:
SSF = 0, SSV = 0

LRAM [8] 0

Last device on this SRAM Bus. When set, this device is the last
device on this SRAM bus in the depth-cascaded table and is the
default driver for the SADR, CE_L, WE_L, and ALE_L signals. In
cycles where no M7020R device in a depth-cascaded table drives
these signals, this device drives the signals as follows:
SADR = 3FFFFF,
CE_L = 1
WE_L = 1
ALE_L = 1
OE_L is always driven by the device for which this bit is set.

25/150

M7020R

The Information Register

Table 11. Information Register Field Descriptions

Note: 1. This field may change in future ve rsions.

CFG [16 :9]

0000
0000

Database Configuration. The device is internally divided into four
quadrants of 8K x 68, each of which can be configured as 8K x 68, 4K
x 136, or 2K x 272 as follows:
00: 8K x 68
01: 4K x 136
10: 2K x 272

11: Reserved
Bits [10:9] apply to configuring the 1st quadrant in the address space.

Bits [12:11] apply to configuring the 2nd quadrant in the address
space.
Bits [14:13] apply to configuring the 3rd quadrant in the address
space.
Bits [16:15] apply to configuring the 4th quadrant in the address
space.

[67:17] 0 Reserved.

Field Range Initial Value Description

Field Range Initial Value Description

Revision [3:0]

0001

(1)

Revision Number. This is the current device revision
number. Numbers start from one and increment by one
for each revision of the device.

Implementation [6:4] 001 This is the M7020R implementation number.

Reserved [7] 0 Reserved.
Device ID [11:8] 0001 or 0010 This is the Device Identification Number.
Device ID [12] Reserved
Device ID [15:13] 00000100 This is the Device Identification Number.

MFID [31:16] 1101_1100_0111_1111

Manufacturer ID. This field is the same as the
manufacturer ID and continuation bits in the TAP
controller.

[67:32] Reserved.

M7020R

26/150

The Read Burst Address Register (RBURREG)

These READ burst address register fields must be
programmed before burst READ (see Table 12).

The Write Burst Address Register (WBURREG)

These WRITE burst a ddress register fields must
be programmed before burst W RITE (see Table

13).

The NFA Register

Bit [0] of each 68-bit data entry is a special bit des­ignated for use in the operation of the LEARN
command. In 68-bit quadrant s, the bi t[0] indi cates
whether a location is full (bit set to ’1’ ) or empty (bit

set to ’0’). Every WRITE/LEARN command loads
the address of first 68-bit location that cont ains a

'0' in the entry’s bit[0]. This i s stored in the NFA
register (see Table 14). If all the bits in a device are
set to '1,' the M7020R asserts FULO[1:0] to '1.'

In 136-bit-configured quadrants, the LSB of this
register is always set to '0.' The host ASIC must
set bit '0' and Bit 68in a 136-bit word to either '0' or
'1' to indicate full/empty status.

Note: Both bits (0 and 68) must be set to '0' or '1'
(e.g., '10' or '01' settings are invalid).

Table 12. Read Burst Register Description

Table 13. Write Burst Register Description

Table 14. NFA Register

Field Range Initial Value Description

ADR [14:0] 0

Address. This is the starting address of the data array or mask array
during a burst READ operation. It automatically increments by 1 for
each successive read of the data array or mask array. Once the
operation is complete, the contents of this field must be reinitialized for
the next operation.

[18:15] Reserved.

BLEN [27:19] 0

Length of Burst Access. The device is capable of writing from 4 up
to 511 locations in a single burst. The BLEN decrements
automatically. Once the operation is complete, the contents of this
field must be reinitialized for the next operation.

[67:28] Reserved.

Field Range Initial Value Description

ADR [14:0] 0

Address. This is the starting address of the data array or mask array
during a burst WRITE operation. It automatically increments by 1 for
each successive write of the data array or mask array. Once the
operation is complete, the contents of this field must be reinitialized for
the next operation.

[18:15] Reserved.

BLEN [27:19] 0

Length of Burst Access. The device is capable of writing from 4 up
to 511 locations in a single burst. The BLEN decrements
automatically. Once the operation is complete, the contents of this field
must be reinitialized for the next operation.

[67:28] Reserved.

Address 67 - 15 14 - 0

60 Reserved Index

27/150

M7020R

SEARCH ENGINE ARCHITECTURE

The M7020R consists of 32K x 68-bit storage cells
referred to as data bi t s. T here i s a mask cell corre­sponding to each data cell. Figure 12 shows the
three organizations of the device based on the val­ue of the CFG bits in the command register.

During a SEARCH operation, the search data bit
(S), data array bit (D), mask array bit (M) and the
global mask bit (G) are used in the following man­ner to generate a mat ch at that bit position (see
Table 15, page 28).

The entry with all matched bit positions results in a
successful search during a SEARCH operation.

In order for a successful search within a device to
make the device the local winner in the SEARCH
operation, all 68-bit positions must generate a
match for a 68-bit entry in 68-bit-configured quad­rants, or all 136-bit positions must generate a
match for two consecutive even and odd 68-bit en­tries in quadrants configured as 136 bits, or all

272-bit positions must generate a match for 4 con­secutive entries aligned to 4 entry-page bound­aries of 68-bit entries in quadrants configured as
272 bits.

An arbitration mechanism using a cascade bus de­termines the global winning device among the lo­cal winning devices in a SEARCH cycle. The
global winning device drives the SRAM Bus, SSV,
and the SSF signals. In case of a SEARCH failure,
the devices with the LDEV and LRAM bits set
drive(s) the SRAM Bus, SSF, and SSV signals.

The M7020R device can be configured to contain
tables of different widths, even within the same
chip. Figure 13, page 28 shows a sample configu­ration of different widths.

Data and Mask Addressing

Figure 14, page 28 shows the M7020R data array
and mask array addressing procedure.

Figure 12. M7020R Database Width Configuration

Data

Data

Data

Masks

Masks

Masks

32 K

CFG = 00000000

CFG = 01010101

CFG = 10101010

68

136

272

16 K

8 K

AI04279

M7020R

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Table 15. Bit Position Match Figure 13. Multi-width Configuration Example

Figure 14. M7020R Data and Mask Array Addressing

G M D S Match

0XXX1
10XX1
11001
11100
11010
11111

8 K

8 K

4 K
2 K

68

68

136

272

CFG = 10010000

AI04280

CFG = 00000000

CF G = 1010 1010

67 0

0
1
2
3

32767

271 0

3210
7654

32764 32765 32766 32767

68

CFG = 010 1010 1

135 0

10
32
54
76

32766 32767

(68-bit Configuration)

( 27 2- bi t c onf ig ur atio n)

(136-bit Configuration)

32 K

8K

16K

68 6868 68 6868

AI04281

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M7020R

COMMAND CODES AND PARAMETERS

A master device, such as an ASIC controller, is­sues commands t o the M7020R using the Com­mand Valid CMDV signal and the CMD Bus. The
following subsections describe the functions of the
commands.

Command Codes

The M7020R implements four basic commands
shown in Table 16. The Command Code must be
presented to CMD[1:0] while keeping the com­mand valid (CMDV) signal high for two CLK2X cy-

cles. These two CLK2X cycles are designated as

“Cycle A” and “Cycle B.” The controller ASIC must
align the instructions wi th the PHS_L signal. The
CMD[8:2] field passes the parameters of the com­mand in Cycles A and B.

Commands and Command Parameters

Table 17, page 29 li sts the CMD bus fields that
contain the M7020R command parameters as well
as their respective cycles.

Table 16. Command Codes

Table 17. Command Parame ters

Note: 1. The 272-bit -configured devices or 272-bit-configured quadrants within devices do not support the LEAR N Instruction.

CMD Code Command Description

00 READ

Reads one of the following: data array, mask array, device registers, or external
SRAM.

01 WRITE

Writes one of the following: data array, mask array, device registers, or external
SRAM.

10 SEARCH

Searches the data array for a desired pattern using the specified register from the
global mask register array and local mask associated with each data cell.

11 LEARN

The device has internal storage for up to 16 comparands that it can learn. The
device controller can insert these entries at the next free address (as specified by
the NFA register) using the LEARN Instruction.

Cmd Cyc 8 7 6 5 4 3 2 1 0

READ

A SADR[21] SADR[20] X 0 0 0

0 = Single

1 = Burst

00

B0 0 0 000

0 = Single

1 = Burst

00

WRITE

A SADR[21] SADR[20] X

Global Mask

Register Index [2:0]

0 = Single

1 = Burst

01

B0 0 0

Global Mask

Register Index [2:0]

0 = Single

1 = Burst

01

SEARCH

A SADR[21] SADR[20] SADR[19]

Global Mask

Register Index [2:0]

68-bit or 136-bit: 0

272-bit:

1 in 1st Cycle

0 in 2nd Cycle

10

B Successful Search Register Index[2:0] Comparand Register Index 1 0

LEARN

(1)

A SADR[21] SADR[20] X Comparand Register Index 1 1

B0 0

Mode

0: 68-bit

1: 136-bit

Comparand Register Index 1 1

M7020R

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READ COMMAND

The READ can be a single read of a data arra y, a
mask array, an SRAM, or a register location
(CMD[2] = 0). It can be a burst READ (CMD[2] = 1)
or mask array locations using an internal auto-in­crementing address register (RBURADR). Table
18, page 32 describes each t ype of READ com­mand.

A single-location READ operation lasts six cycles,
as shown in Figure 15, page 31. T he bu rst RE A D
adds two cycles for each successive READ. The
SADR[21:20] bits supplied in the READ Instruction
Cycle A drive SADR[21:20] signals during the
READ of an SRAM location.

The single READ operation takes six CLK cycles,
in the following sequence:

– Cycle 1: The ho st ASIC applies the READ In-

struction on the CMD[1:0] (CMD[2] = 0), using
CMDV = 1, and the DQ Bus supplies the ad­dress, as shown in Table 19, page 32 and Table
20, page 33. The host ASIC selects the M7020R
for which ID[4:0] matches the DQ[25:21] lines. If
the DQ[25:21] = 1 1111, the host ASIC selects
the M7020R with the LDEV Bit set. The host
ASIC also supplies SADR[21:20] on CMD[ 8:7]
in Cycle A of the RE A D I nstruction if t he REA D
is directed to the external SRAM.

– Cycle 2: The ho st ASIC floats DQ[67:0] to 3-

state condition.

– Cycle 3: The host ASIC keeps DQ[67:0] in 3-

state condition.

– Cycle 4: The selected device starts to driv e the

DQ[67:0] Bus and drives the ACK signal from Z
to low.

– Cycle 5: The selected d evice drives the read

data from the addressed location on the
DQ[67:0] Bus and drives the ACK signal high.

– Cycle 6: The selected device floats DQ[67:0] to

3-state condition and drives the ACK signal low.

At the termination of Cycle 6, the selected dev ice
releases the ACK line to 3-state condition. The
READ Instruction is complete, and a new opera­tion can begin.

Note: The laten cy of the SR AM RE AD will be d if­ferent than the one described ab ove (see SRAM
PIO Access, page 126). Table 19, page 32 lists

and describes the format of the READ address for
a data array, mask array, or SRAM.

In a burst READ operation, the READ lasts 4 + 2n
CLK-cycles (where “n” stands for the number of
accesses in the burst specified by the BLEN field
of the RBURREG). Table 20, page 33 describes
the READ address format for the internal registers.
Figure 16, page 31 illustrates the timing diagram
for the burst READ of the data or mask array. This
operation assumes that the host ASIC has pro­grammed the RBURREG with the starting address
(ADR) and the length of transfer (BLEN) before ini­tiating the burst READ command.

– Cycle 1: The ho st ASIC applies the READ In-

struction on the CMD[1:0] (CMD[2] = 1), using
CMDV=1 and the address supplied on the DQ
Bus, as shown in Ta ble 21, page 33. The h ost
ASIC selects the M7020R for which ID[4:0]
matches the DQ[25:21] lines. If the DQ[25:21] =
11111, the host ASIC selects the M70 20R with
the LDEV Bit set.

– Cycle 2: The host ASIC floats DQ[67:0] to the 3-

state condition.

– Cycle 3: The host ASIC keeps DQ[67:0] in t he

3-state condition.

– Cycle 4: The selected device starts to driv e the

DQ[67:0] Bus and drives ACK and E OT from Z
to low.

– Cycle 5: The selected dev ice drives the REA D

data from the addressed location on the
DQ[67:0] Bus and drives the ACK signal high.

Note: Cycles four and five repeat for each addi­tional access until all the accesses specified in
the burst length (BLEN) field of RBURREG are
complete. On the last transfer, the M7020R
drives the EOT signal high.

– Cycle (4 + 2n): The selected device drives t he

DQ[67:0] to 3-state condition and drives the
ACK and the EOT signals low.

At the termination of Cycle 4 + 2n, the selected de­vice floats the ACK line to 3 -state condition. The
burst READ Instruction is complete, and a new op­eration can begin (see Table 21, page 33 for burst
READ address formats).