SGS Thomson Microelectronics M7010R Datasheet

1/67July 2002

M7010R

16K x 68-bit Entry NETWORK SEARCH ENGINE

FEATURES SUMMARY

■ 16K ENTRIES IN 68-BIT MODE

■ TABLE MAY BE PARTITIONED INTO UP TO

FOUR (4) QUADRANTS (Data entry width in each quadrant is config-

urable as 34, 68, 136, or 272 bits.)

■ UP TO 83 MILLION SUSTAINED SEARCHES

PER SEC OND IN 68-BIT and 136-BIT CONFIGURATIONS

■ UP TO 41.5 MILLION SEARCHES PER

SECOND IN 34-BIT and 272-BIT CONFIGURATIONS

■ SEARCHES ANY SUB-FIELD IN A SINGLE

CYCLE

■ OFFERS BIT-BY-BIT and GLOBAL MASKING

■ SYNCHRONOUS, PIPELINED OPERATION

■ UP TO 31 SEARCH ENGINES CASCADABLE

WITHOUT PERFORMANCE DEGRADATION

■ WHEN CASCADED, THE DATABASE

ENTRIES C A N SCALE FROM 124K to 992K DEPENDING ON THE SIZE OF THE ENTRY

■ GLUELESS INTERFACE TO INDUSTRY-

STANDARD SRAMS

■ SIMPLE HARDWARE INSTRUCTION

INTERFACE

■ IEEE 1149.1 TEST ACCESS PORT

■ OPERATING SUPPLY VOLTAGES INCLUDE:

(Operating Supply Voltage) = 1.8V

DDQ

(Operating Supply Voltage for I/O) = 2.5

or 3.3V

■ 272 BALL, 27mm x 27mm, CAVITY-UP BGA

Figure 1. 272-ball PBGA Package

272 PBGA

27mm x 27mm

1.27mm ball pitch

M7010R

2/67

TABLE OF CONTENTS

DESCRIPTION ....................................................................6

Overview......................................................................6

Performance...................................................................6

Applications....................................................................6

Product Range (Table 1.) . ........................................................6

Switch/Router Implementation Using the M7010R (Figure 2.) .............................6

SignalNames(Table2.)..........................................................7

Connections (Figure 3.). . . ........................................................8

M7010RBlockDiagram(Figure4.)..................................................9

MAXIMUMRATING................................................................10

AbsoluteMaximumRatings(Table3.) ..............................................10

DC AND AC PARAMETERS. . .......................................................11

DC and AC Measurement Condi tions (Table 4.). . . ....................................11

M7010R2.5VACTestingLoad(Figure5.)...........................................12

M7010R2.5VInputWaveform(Figure6.)............................................12

M7010R2.5VOutputLoadEquiv.(Figure7.).........................................12

M7010R3.3VACTestingLoad(Figure8.)...........................................12

M7010R3.3VInputWaveform(Figure9.)............................................12

M7010R3.3VOutputLoadEquiv.(Figure10.)........................................12

Capacitance (Table 5.) . . . .......................................................13

DCCharacteristics(Table6.).....................................................13

ACTimingWaveformswithCLK2X(Figure11.).......................................14

ACTimingParameterswithCLK2X(Table7.)........................................15

OPERATION.....................................................................16

CommandBusandDQBus ......................................................16

DatabaseEntry(DataArrayandMaskArray).........................................16

Arbitration Logic. . . .............................................................16

PipelineandSRAMControl.......................................................16

FullLogic.....................................................................16

Connections Descriptions . .......................................................16

3/67

M7010R

CLOCKS........................................................................18

Registers.....................................................................18

Clocks(Figure12.).............................................................18

RegisterOverview(Table8.)......................................................18

ComparandRegisters...........................................................18

ComparandRegisterSelectionDuringSEARCHandLEARN(Figure13.)...................19

MaskRegisters................................................................18

AddressingtheGlobalMaskRegister(GMR)Array(Figure14.)..........................19

SEARCH-Successful Registers. . . .................................................19

SEARCH-Successful Register (S S R) Description (Table 9.). .............................19

TheCommandRegister .........................................................20

CommandRegisterFieldDescriptions(Table10.).....................................20

SEARCH PROCEDURE FOR 32-BIT WIDE PREFIXES ...................................22

GlobalMaskRegisterPatterns(Figure15.)..........................................22

StoringlefthalfofaDataorMaskArray(Figure16.)...................................22

TheInformationRegister.........................................................23

InformationRegisterFieldDescriptions(Table11.) ....................................23

The RE AD Burst Address Register (RBURREG) . . ....................................23

READBurstRegisterDescription(Table12.).........................................23

The WRITE Burst Address Register (WB URRE G) . ....................................23

WRITEBurstRegisterDescription(Table13.)........................................23

TheNFARegister..............................................................24

NFARegister(Table14.).........................................................24

SEARCH ENGINE ARCHITECTURE . .................................................24

DataandMaskAddressing.......................................................24

M7010RDatabaseConfiguration(Figure17.).........................................25

BitPositionMatch(Table15.).....................................................25

Multi-widthConfigurationExample(Figure18.) .......................................25

M7010RDataandMaskArrayAddressing(Figure19.).................................26

COMMAND CODES AND PARAMETERS..............................................27

CommandCodes...............................................................27

CommandsandCommandParameters.............................................27

CommandCodes(Table16.) .....................................................27

CommandParameters(Table17.) .................................................27

READCOMMAND.................................................................28

SingleLocationREADCycleTiming(Figure20.)......................................29

BurstREADoftheDataandMaskArrays(BLEN=4)(Figure21.)........................29

READCommandParameters(Table18.)............................................30

DataandMaskArray,SRAMREADAddressFormat(Table19.) .........................30

READAddressFormatforInternalRegisters(Table20.)................................30

READAddressFormatforDataandMaskArrays(Table21.)............................31

M7010R

4/67

WRITECOMMAND................................................................31

SingleLocationWRITECycleTiming(Figure22.).....................................32

BurstWRITEoftheDataandMaskArrays(BLEN=4)(Figure23.)........................32

(Single)WRITEAddressFormatforDataandMaskArraysorSRAM(Table22.).............33

WRITEAddressFormatforInternalRegisters(Table23.)...............................33

WRITEAddressFormatforDataandMaskArray(BurstWRITE)(Table24.)................33

SEARCH COMMAND . .............................................................34

68-bitConfiguration ...........................................................34

HardwareDiagramforaTablewithaSingleDevice(68-bitOperation)(Figure24.)...........34

68-BitConfigurationSEARCHTimingDiagram(OneDevice)(Figure25.)...................35

Right-Shift o f 68-bit Signals for TLSZ Valu es (Table 25.) . . . .............................36

ShiftofSSFandSSVfromSADR(fordifferentHLATValues)(Table26.)...................36

Latency of SEARCH from I nstruction to SRAM Access Cycle (68-bit Mode) (Table 27.) ........36

68-bitLogicalSEARCH..........................................................37

x68TablewithOneDevice(Figure26.).............................................37

136-bitConfiguration ..........................................................38

Hardware Diagram for a Table with One Device (136-bit Operation) (Figure 27.) . . . ..........38

136-BitConfigurationSEARCHTimingDiagram(OneDevice)(Figure28.)..................39

Right-Shift o f 136-bit Signals for TLSZ Val ues (Table 28.) . . .............................40

ShiftofSSFandSSVfromSADR(fordifferentHLATvalues)(Table29.)...................40

LatencyofSEARCHfromInstructiontoSRAMAccessCycle(136-bitMode)(Table30.).......40

136-bitLogicalSEARCH.........................................................41

x136TablewithOneDevice(Figure29.)............................................41

272-bitConfiguration ..........................................................42

Hardware Diagram for a Table with One Device (272-bit Operation) (Figure 30.) . . . ..........42

272-BitConfigurationSEARCHTimingDiagram(OneDevice)(Figure31.)..................43

Right-Shift o f 272-bit Signals for TLSZ Val ues (Table 31.) . . .............................44

ShiftofSSFandSSVfromSADR(fordifferentHLATValues)(Table32.)...................44

LatencyofSEARCHfromInstructiontoSRAMAccessCycle(272-bitMode)(Table33.).......44

272-bitLogicalSEARCH.........................................................45

x272TablewithOneDevice(Figure32.)............................................45

Mixed-sized Searches on Tables Configured with Different Width Using an M7010R Device46

MultiwidthConfigurationExample(Figure33.)........................................46

TimingDiagramforMixedSEARCH(OneDevice)(Figure34.)...........................47

LRAM an d LDEV Description . . . .................................................48

LEARNCOMMAND ...............................................................48

LEARNCommandTimingDiagram(TLSZ=00)(Figure35.).............................49

LEARNTimingDiagram(TLSZ=1,exceptonLastDevice)(Figure36.)....................50

LEARNTimingDiagramonDeviceNumber7(TLSZ=01)(Figure37.).....................51

SRAMWRITECycleLatencyfromSecondCycleofLEARNInstruction(Table34.)...........51

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M7010R

DEPTH-CASCADING . .............................................................52

Depth-CascadingUptoEightDevices(OneBlock) ....................................52

Depth-Cascading Up to 31 Devices (4 Blocks) ........................................52

Depth-CascadingtoGeneratea“FULL”StateforaBlock ...............................52

Depth-CascadingtoFormaSingleBlock(8Devices)(Figure38.).........................53

Four Blocks (31 Devices Cascaded) SEARCH, 68-bit Configured with LDEV = 1 (Figure 39.) ...54

“FULL” State Generation in a Cascaded Table (Figure 40.) . .............................55

ARBITRATION ...................................................................56

TimingDiagramforArbitrationWithinaBlock(Figure41.)...............................56

TimingforArbitrationforTwoorMoreBlocksfortheLastDevice(Figure42.)................57

SRAM ADDRESSING . .............................................................58

SRAMPIOAccess .............................................................58

SRAM RE AD Access for One M7010R Device (Figure 43.) . .............................59

SRAMWRITEAccessforOneM7010RDevice(Figure44.).............................61

SRAMBusAddressGeneration(Table35.)..........................................61

Right-Shift o f SRAM Signals for TLSZ V alues (Table 36.) . . .............................62

Right-Shift o f SRAM Signals for HLAT Values (Table 37.) . . .............................62

JTAG(1149.1)TESTING ...........................................................62

TestAccessPortControllerInstructions(Table38.)....................................62

TAPDeviceIDRegister(Table39.) ................................................62

POWERDISTRIBUTIONGUIDELINE .................................................63

NetworkSearchEnginePowerDistribution(Figure45.).................................63

PARTNUMBERING ...............................................................64

PACKAGE MECHANICAL INFORMATION . . . ..........................................65

REVISIONHISTORY...............................................................66

M7010R

6/67

DESCRIPTION Overview

The M7010R is a feature-rich, TCAM-based hardware search engine optimized for networking and communications applications. It incorporates leading-edge Associative Processing Technology (APT, tradema rk of Cypress Semiconductor, Inc.) and Advanced Power Management. The data table may be partitioned into u p to four (4) quadrants, allowing the user t o configure each quadrant with different table entry widths (x34, x68, x136, or x272-bit). It is also programmable to accelerate performance.

Performance

The M7010R outperforms competitive solutions using software sequential search algorithms in conjunction with SRAMs or A SICs, or hardware implementation with ASICs and C A Ms. The latter solution, while faster than a software-based solu-

tion, still suffers from performance degradation when depth-cascaded and is unable to scale to next-generation requirements. The M7010Rbased solutions overcome all of these drawbacks.

Applications

The performance and features of the M7010R makes it ideal in applications such as enterprise LAN switches, broadband switching and routing equipment, supporting multiple data rat es from OC–48 and beyond.

Figure 2 illustrates how a search engine subsystem can be optimized using a host bridge ASIC, the M7010R, and synchronous o r non-synchronous SRAMs. It also illustrates how this system fits into a switch-router implementation.

Table 1. Product Range

Figure 2. Switch/Router Im pl ementation Using the M7010R

Part Number Operating Supply Voltage Operating I/O Voltage Speed

M7010R-083ZA1 1.8V 2.5 or 3.3V 83MHz M7010R-066ZA1 1.8V 2.5 or 3.3V 66MHz

Program

Memory

Switch

Fabric

Switch

Processor

Network Line Interfaces

System Bus

Host

ASIC

SRAM

Bank

Search Engine

AI04272

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M7010R

Table 2. Signal Names

Note: Signal types are: I = Input only; I/O = Input or Output; O = Output; and T = Tristate

1. ACK and EOT Signals require a pull-down resistor of 47 ohms.

Symbol Type Connection Name

Clocks and Reset

CLK2X I Master Clock PHS_L I Phase RST_L I Reset

Command and DQ Bus

CMD[8:0] I Command Bus CMDV I Command Valid DQ[67:0] I/O Address/Data Bus

ACK

(1)

T READ Acknowledge

EOT

(1)

T End of Transfer SSF T SEARCH Successful Flag SSV T SEARCH Successful Flag Valid

SADR[21:0] T SRAM Address CE_L T SRAM Chip Enable WE_L T SRAM WRITE Enable OE_L T SRAM Output Enable ALE_L T Address Latch Enable

Cascade Interface

LHI[6:0] I Local Hit In LHO[1:0] O Local Hit Out BHI[2:0] I Block Hit In BHO[2:0] O Block Hit Out FULI[6:0] I Full In FULO[1:0] O Full Out FULL O Full Flag

Device Identification

ID[4:0] I Device Identification

Test Access Port

TDI I Test Access Port’s Test Data In TCK I Test Access Port’s Test Clock

TDO T

Test Access Port’s Test Data Out

TMS I

Test Access Port’s Test Mode Select

TRST_L I Test Access Port’s Reset

M7010R

8/67

Figure 3. Connections

Note: This diagram is TOP VIEW perspective(view through package).

SADR

SADR2SADR

SADR

GND

GNDGNDGND

GND

GNDGND

GND

GNDGND

GNDGNDGND

FULL

EOTNC

ACK

NC NC

LHI6

LHI5

LHI4

LHI1

LHO0

LHO1

BHI0BHO0

BHO1

BHO2

FULI0

FULI3

FULO0

FULO1 FULI2

FULI1FULI4FULI5

FULI6

BHI2

BHI1

LHI0

LHI2

LHI3

NCNC

DDQ

CMD8

CMD7

CMD5

CMD2

CMD3

CMD1

CMD6

CMD4

CMD0

CMDV

DQ17

DQ15

DQ13DQ11

DQ9

DQ1

DQ5

DQ7

DQ21

DQ27

DQ31

DQ33

DQ29

DQ25

DQ23

DQ19

DQ35

DQ37

DQ43

DQ53

DQ57DQ61

DQ63

DQ67

DQ59

DQ55

DQ49

DQ64

DQ62

DQ60

DQ66

DQ58

DQ56

DQ50

DQ48

DQ46

DQ44

DQ42

DQ38

DQ30

DQ36

DQ32DQ34

DQ28

DQ20

DQ24

DQ22

DQ16

DQ18

DQ8 DQ0

DQ2 DQ4

DQ12

DQ10

DQ14

DQ6

DQ26

DQ40

DQ52

DQ54

DQ51

DQ45

DQ41

DQ39

DQ47

DQ65

DQ3

TDO

TMS

TCK

TDI

ID0

ID2

ID3

ID1

ID4

GND

GNDGND

GND

GND GND

GNDCLK2X

WE_L

OE_L

AE_L

CE_L

PHS_L

SSF

SSV

RSTL

GND

RST_L

RIGHT

BOTTOM

LEFT

TOP

AI04270

9/67

M7010R

Figure 4. M7010R Block Diagram

AI04273

Comparand Registers[15:0] Global Mask Registers [7:0]

Information and Command Register

Burst Read Register Burst Write Register

Next Free Address Register

Search Successful Index Registers [7:0]

(All registers are 68-bit-wide)

TAP

Controller

Pipeline

and

SRAM

Control

Arbitration

Logic

Command

Decode

and PIO Access

Compare/PIO Data

PHS_L CLK2X RST_L

DQ [67:0]

CMD [8:0]

CMDV

ACK EOT

Cmd

Compare/PIO Data

Address Decode

Priority Encode

Match Logic

Configurable as

32K x 34 16K x 68 8K x 136 4K x 272

Data Array

Configurable as

32K x 34 16K x 68 8K x 136 4K x 272

Mask Array

Full LogicFULL [6:0]

FULL

FULO [1:0]

ID [4:0]

LHI [6:0]

BHI [2:0]

SSF SSV

LHO [1:0] BHO [2:0]

TAP

SADR [21:0]

OE_L

WE_L

CE_L

ALE_L

M7010R

10/67

MAXIMUM RATING

Stressingthedeviceabovetheratinglistedinthe “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Ope ra ting sections of this specificat ion is

not implied. Exposure to A bs olute Maximum Rating conditions for extended periods may af fect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

Table 3. Absolute Maximum Ratings

Note: 1. Solderingtemperaturenot to exceed260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

Symbol Parameter Value Unit

STG

Storage Temperature (VDDOff)

–0to70 °C

SLD

(1)

Lead Solder Temperature for 10 seconds 235 °C

DDQ

Input or Output Voltages 3.3 V

Supply Voltage –0.4 to 2.7 V

Output Current 100 mA

Power Dissipation < 3 W

11/67

M7010R

DC AND AC PARAMETERS

This section summarizes the operating and measurement c onditions, as well as the DC and A C characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under t he Measure-

ment Conditions listed in the relevant tables. Designers should check that the operat ing conditions in their projects match the measurement conditions when using the quoted parameters.

Table 4. DC and AC Measurement Conditions

Note: 1. Maximum allowable applies to overshoot only (V

DDQ

is 3.3V supply).

2. Minimumallowableappliesto undershoot only.

Sym Parameter M7010R 2.5V M7010R 3.3V Units

DDVDD

Operating Supply Voltage

1.7 to 1.9 1.7 to 1.9 V

DDQVDDQ

Voltage for I/O

2.4 to 2.6 3.1 to 3.5 V

Ambient Operating Temperature 0 to 70 0 to 70 °C

Load Capacitance 6 6 pF

Input High Voltage

(1)

1.7 to

DDQ

+0.3

2.0 to

DDQ

+ 0.3

Input Low Voltage

(2)

–0.3 to 0.7 –0.3 to 0.8 V

Supply Voltage Tolerance ±5 ±5 %

R,tF

Input Rise and Fall Times (at 0.3V and 2.7V)

≤ 2 (see Figure 6, page 12) ≤ 2 (see Figure 9, page 12) ns

Input Timing Reference Levels 1.25 1.5 V Output Timing Reference Levels 1.25 1.5 V Input Pulse Voltages GND to 2.5 GND to 3.3 V Input and Output Timing Ref. Voltages (see Figure 7, page 12) (see Figure 10, page 12) V

M7010R

12/67

Figure 5. M7010R 2.5V AC Testing Load

Figure 6. M7010R 2.5V Input Waveform

Figure 7. M7010R 2.5V Output L oad Equiv.

Figure 8. M7010R 3.3V AC Testing Load

Figure 9. M7010R 3.3V Input Waveform

Figure 10. M7010R 3.3V Output Load Equiv.

VL= 1.25V

50ΩZ0 = 50Ω

OUT

AI04268

+2.5V

90%

10%

90%

10%

GND

AI04299

208Ω

192Ω

AI04266

5pF

+2.5V

VL= 1.5V

50ΩZ0 = 50Ω

OUT

AI04269

+3.3V

90%

10%

90%

10%

GND

AI04298

158Ω

175Ω

AI04267

5pF

+3.3V

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M7010R

Table 5. Capacitance

Note: Effective capacitance measured with power supply. Sampled only, not 100% tested.

1. Outputs deselected.

Table 6. DC Characteristi cs

Note: 1. Valid for Ambient OperatingTemperature:TA=0to70°C; VDD=1.8V.

Symbol Parameter Test Condition Min Max Unit

Input Capacitance

=0V

6pF

(1)

Input / Output Capacitance

OUT

=0V

6pF

Symb Parameter

Test Condition

(1)

Min Max Unit

Input Leakage Current

DDQ=VDDQ

(max)

0V ≤ V

≤ V

DDQMAX

–10 +10 µA

Output Leakage Current

DDQ=VDDQ

(max)

0V ≤ V

OUT

≤ V

DDQMAX

–10 +10 µA

DD1

1.8V Supply Current @ V

DDMAX

M7010R

OUT

= 0mA,

83MHz Search

1250 mA

M7010R

OUT

= 0mA,

66MHz Search

1000 mA

DD2

2.5V Supply Current @ V

DDMAX

M7010R

OUT

= 0mA,

83MHz Search

180 mA

M7010R

OUT

= 0mA,

66MHz Search

150 mA

DD3

3.3V Supply Current @ V

DDMAX

M7010R

OUT

= 0mA,

83MHz Search

300 mA

M7010R

OUT

= 0mA,

66MHz Search

240 mA

Input Low Voltage –0.3 0.8 V

Input High Voltage 2.0

DDQ

+0.3

Output Low Voltage

DDQ=VDDQ

(min)

=8mA

0.4 V

Output High Voltage

DDQ=VDDQ

(min)

= 8mA

2.4 V

M7010R

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Figure 11. AC Timing Waveforms with CLK2X

Cycle

CLK2X

Signal

Group 0

Signal

Group 2

Signal

Group 3

Signal

Group 4

Signal

Group 5

PHS_L

AI04265

Signal

Group 1

Signal Group 1: PHS_L, RST_L Signal Group 1: DQ, CMD, CMDV Signal Group 2: LHI, BHI, FULI Signal Group 3: LHO, BHO, FULO, FULL Signal Group 4: SADR, CE_L, OE_L, WE_L, ALE_L, SSF, SSV Signal Group 5: DQ, ACK, EOT

tICSCH

tICHCH

tCKHOV

tCKHSV

tCKHSHZ

tCKHSLZ

tCKHOV

tIHCH

tISCH

tIHCH

tCKHDZ

tCKHDV

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M7010R

Table 7. AC Timing Parameters with CLK2X

Note: 1. Valid for Ambient OperatingTemperature:TA=0to70°C; VDD=1.8V.

2. Values are based on 50% signal levels.

3. BasedonanACloadofCL=50pF(seeFigure5,page12andFigure8,page12).

4. Unless otherwise noted, all values are based on AC load of CL = 50pF (see Figure 5, page 12 and Figure 8, page 12).

5. These parameters are sampled and not 100% tested.

Row Symbol

M7010R-066 M7010R-083

Unit

Description

(1)

Min Max Min Max

CLK

133 166 MHz CLK2X frequency

CLK

7.5 6.0 ns CLK2X period

CKHI

3.0 2.4 ns

CLK2X high pulse

(2)

CKLO

3.0 2.4 ns

CLK2X low pulse

(2)

ISCH

2.5 1.8 ns

Input Setup Timeto CLK2X rising edge

(2)

IHCH

0.6 0.6 ns

Input Hold Time to CLK2X rising edge

(2)

ICSCH

4.2 3.5 ns

Cascaded Input Setup Time to CLK2X rising edge

(2)

ICHCH

0.6 0.6 ns

Cascaded Input Hold Time to CLK2X rising edge

(2)

CKHOV

8.5 7.0 ns

Rising edge of CLK2X to LHO, FULO, BHO, FULL valid

(3)

CKHDV

9.0 7.5 ns

Rising edge of CLK2X to DQ valid

(4)

CKHDZ

8.5 7.0 ns

Rising edge of CLK2X to DQ high-Z

(5)

CKHSV

9.0 7.5 ns

Rising edge of CLK2X to SRAM Bus valid

(4)

CKHSHZ

6.5 6.0 ns

Rising edge of CLK2X to SRAM Bus high-Z

(4,5)

CKHSLZ

7.0 6.5 ns

Rising edge of CLK2X to SRAM Bus low-Z

(4,5)

M7010R

16/67

OPERATION Command Bus and DQ Bus

CMD[8:0] carries the com mand and its associated parameter. DQ[67:0] is used for data transfer to, and from the data base entries. The database entries are comprised of a data field and a mask field which are organized as a data array and a mask array. The DQ Bus carries t he SEARCH data during the SEARCH command as we ll as the address and data during Pipelined I/O (P IO) READ/WRITE operations, of the data array, mask array, and internal registers. The DQ Busalsocan carry the address information for the PIO accesses to the SRAM.

Database Entry (Data Array a nd Mask Array)

Each database entry comprises a data field and a mask field.The resultant value of t he entry is a logical AND of the corresponding data and mask bits and can take logi c al values of '1,' '0' and 'X' (don’t care), depending on t he v alue in the mask bi t. The on-chip priority encoder selects the first matching entry in the database which is nearest to location

Arbitration Logic

When multiple (Silicon) Search Engines are cas caded to create large databas es , the data being searched is presented to all Se arch proc es s ors simultaneously in thecascaded system.W hen more than one device has duplicate entries, the arbitration logic on the Search Engine with the matching entry whichis closest toaddress0 of the cascaded database, will be selected to drive the SRAM Bus.

Pipeline and SRAM Control

Pipeline latency is added to give enough time t o the arbi tration logic in a cascaded system to determine the index with the highest priority. T he pipeline logic adds latency to the SRAM access cycles and the SSF and SSV signals to align t hem to the host ASIC receiving the associated data. Refer to Table 27, page 36 for details.

Full Logic

Bit[0] in each of the 68-bit entries has a special purpose for the LEARN command (0 = empty, 1 = full). When all thedata ent ries have Bit[0] set to '1,' the database asserts the FULL flag, indicating that all the Search Engines in the depth-cascaded array are full.

Connections Descri ption s Master Clock (CLK2X). T he M7010R samples

all of the control and data signals on the pos itive edge of CLK2X when PHS_L is low.

Phase (PHS_L). This signal runs at half the frequency of CLK2X and generates an internal clock from CLK2X (see Figure 12, page 18).

Reset (RST_L). Driving RST low initializes the device to a known state.

Command Bus (CMD[8:0]. [1:0] specifies the command; [8:2] contains the comm and parameters. The descriptions of individual commands explains the details of t he parameters. The encod ing of comman ds based on the [1:0] field are:

– 00: PIO READ – 01 : PIO WRITE – 10: SEARCH – 11: LEARN

Command Valid (

CMDV). Qualifies the CMD bus

as follows:

– 0: No Command – 1: Command

Address/Data Bus (

DQ[67:0]). Carries the READ

and WRITE address as well as the data during register, data, and mask array operations. It carries the compare data during SEARCH operations. It also carries the SRAM address during SRAM PIO accesses.

READ Acknowledge (ACK). Indicates that valid data is available on the DQ Bus during register, data, and mask array READ operations, or the data is available on the SRAM data bus during SRAM READ operations.

Note: ACK Signals require a pull-down resistor of 47Ω.

End of Transfer (EOT). Indicates the end of burst t rans fer during READ or WRITE burst operations.

Note: EOT Signals re quire a pull-down resistor of 47 ohms.

SEARCH Successful Flag (SSF). When asserted, t his signal indicates t hat the device is the global winner in a SEARCH operation.

SEARCH Successful Flag Valid (SSV). When asserted, this signal qualifies the SSF signal.

SRAM Address (SADR[21:0]). This bus con- tains address lines to access off-chip SRAMs that contain associative data. See Table 35, page 61 for the details of the generated SRA M address.

SRAM Chip Enable (CE_L). This is Chip Enable control for external SRAMs. When more than one device is cascaded, CE_L of all devices must be connected.

SRAM WRITE Enable (WE_L). This is WRITE Enable control for external SRAMs. When more than one device is cascaded, WE_L of all devices must be connected.

SRAM Output Enable (OE_L). This is Output Enable control for external SR AM s . Only the last device drives this signal (with the LRAM Bit set).

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M7010R

Address Latch Enable (ALE_L). When this sig-

nal is low, t he addresses on the SRA M address bus havebeenvalidated.When more than one device is cascaded, the A LE_Lof all devices must be connected.

Local Hit In (LHI[6:0]). These pins depth-cascade the device to form a larger table size. One signal of th is bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block. Connect all unused LHI pins to a logic '0. ' (For more information, see DEPTH-CASCADING, page 52.)

Local Hit Out (LHO[1:0]). LHO[1] and LHO[0] are the same logical signal. LHO[1] or LHO[0] is connected to one input of the LHI bus of up to four downstream devices (in a block t hat cont ains up to eight devices; for more information , s ee DEPTHCASCADING, page 52.)

Block Hit In (BHI[2:0]). Input s from the previous BHO[2:0] are tied to the BHI[2:0] of the current device (see DEPTH-CASCADING, page 52). In a four-block system, t he last block can cont ain only seven devices because the ID c ode 11111 is used for broadcast access.

Block Hit Out (BHO[2:0]). Outputs from the current de vic e are connected to the BHI[2:0] of the next device (see DEPTH-CASCADING, page 52).

Full In (FUL I[6:0]). Each signal in this bus is connected to FULO[0] or FULO[1] of an upstream device to generate the FULL flag for the depth-

cascaded block. For more information, see DEPTH-CASCADING, page 52 to Generate Full for a Block Section.

Full Out (FULO[1:0]). FULO[1] and FULO[0] are the same logical signal. One of these two signals must be connected to the FULI of up to four downstream devices in a depth-cascaded table. Bit [0] in the dat a array indicates if the entry is full (1) or empty (0).This sign al is asserted if all of the bits in the data array are '1s.' Refer to Depth-Cascading to Generate a “FULL” State for a B lock , page 52.

Full Flag (FULL). When assert ed, this signal indicates that the table consisting of m any depthcascaded devices is full.

Device Identification (ID[4:0]). The binary-en- coded device ID for a depth-cascaded system starts at 00000 and goes up to 11110. 11111 is reserved for a special broadcast ad dres s that selects all cascad ed (silicon) Search Engines in t he system. On a broadca st read-only, the device with the LDEV Bit set to '1' responds.

Test Data In (TDI). This is the Test Access Port’s Test Data In.

Test Clock (TCK). This is the Test Access Port’s Test Clock.

Test Data Out (TDO). This is the Test Access Port’s Test Data Out.

Test Mode Select (TMS). This is the Test Access Port’s Test Mode Select.

Test Reset (TRST_L). This is the Test Access

M7010R

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CLOCKS

The M7010R receives a Clock (CLK 2X ) signal and Phase ( PHS_L) signal. The Phase (PHS_L) divides the CLK2X signal to generate the Internal Clock (CLK), as shown in Figure 12. The CLK2X and CLK signals are us ed for internal operations.

Registers

All the M7010R registers are 68 bits wide. The M7010R contains 32 comparand storage registers, 16 global mask registers, 8 SEARCH-successful index registers, c ommand, information, burst RE AD, burst WRITE, and next free address registers. Table 8 provides a register overview of all the registers. The registers a re ordered in ascending add re ss order.

Comparand Registers

The device contains t hirty-two 68-bit comparand registers dynamically selected in every SEARCH operation to store the comparand presented on the DQ Bus. The LEARN command will also use these registers when it is executed. The M7010R stores the SEARCH command’s “Cycle A” comparand in the ev en-number register and the “Cycle B” comparand in the odd-numbered register, as shown in Figure 13, page 19.

Mask Registers

The device contains sixteen (8 pairs) 68-bit glo bal mask registers dynamically s elect ed in every SEARCH operation to select the SEARCH subfield (see Figure 14, page 19). The three-bit GMR Index supplied on the CMD bus applies eight pairs of global masks during the SEARCH and WRITE operations, also shown in Figure 14.

Note: In 68-bit SEARCH and WRITE operations, the host ASIC must program the even and odd mask register with the same values, and the M7010R uses even-numbered mask registers as global masks.

Each mask b it in the global mask registers is used during SEARCH and WR ITE operations. In SEARCH operations, settingthe Mask Bit to '1' enables compares; setting the Mas k Bit to '0' disables compares (forced match) at the current bit position. In WRITE operations to the data or mask array, setting the Mask Bit to '1' enables WRITEs; setting the Mask Bit to '0' disables WRITEs at the corresponding bit position.

Figure 12. Clocks

Note: Any reference to “CLK Cycles” means 2 cycles of the signal, “CLK2X.”

1. “CLK” is an internal signal. The period for this clock is specified in Table 7, page 15.

Table 8. Register Overv iew

Address Abbreviation Type Name

0–31 COMP0–31 R

32 Comparand Registers. Stores comparands from the DQ Bus for

learning later. 32–47 MASKS RW 16 Global Mask Registers Array. 48–55 SSR0–7 R 8 SEARCH Successful Index Registers.

56 COMMAND RW Command Register. 57 INFO R Information Register. 58 RBURREG RW Burst READ Register. 59 WBURREG RW Burst WRITE Register. 60 NFA R Next Free Address Register.

61–63 ––Reserved

CLK2X

PHS_L

CLK

(1)

AI04274

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M7010R

Figure 13. Comparand Register Selection

During SEARCH and LEARN

Figure 14. Add ressing the Global Mask

SEARCH-Successful Registers

The device contains eight SEARCH-successful registers (SSRs) to hold the index of the location where a successful search occurred. Theformat of each register is described in Table 9. The SEARCH command specifies w hich SSR stores the index of a specific SEARCH command in “Cycle B” of the SEARCH Instruction.

After the index location is specified, the host ASIC can use this register to access t hat data array, mask array, or external SRAM u sing the index as part of the address (see SRAM ADDRESSING, page 58). The device with a vali d bit set performs a READ or WRITE operation. All other devices suppress the operation.

Table 9. SEARCH-Successful R egister (SSR) Description

135 0

6868

32 54

30 31

Address

Index

AI04275

135 0

6868

32 54

0 1

6 7

Address

Index

AI04276

SEARCH and WRITE Command

Global Mask Selection

Field Range Initial Value Description

INDEX [13:0] X

Index. This is the address of the 68-bit entry where a successful search occurs. The device updates this field if it has a successful search. In 136-bit, the LSB is '0;' in a 272-bit configuration, the two LSBs are '00.' The index updates if the device is either a local or global winner in a SEARCH operation.

– [30:14] 0 Reserved.

VALID [31] 0

Valid. The device sets this bit to '1' if it is a global winner (first device downstream with a hit) in a SEARCH operation, in a depth-cascaded configuration.

– [67:32] 0 Reserved.

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The Command Register Table 10. Command Register Field Description s

Field Range Initial Value Description

SRST [0] 0

Software Reset. If '1,' this bit resets the device, with the same effect as the hardware reset. Internally, it generates a reset pulse lasting for eight CLK cycles. This bit automatically resets to a '0' during the reset cycle.

DEVE [1] 0

Device Enable. If '0,' it keeps the SRAM bus (SADR, WE_L, CE_L, OE_L, and ALE_L), SSF, and SSV signals in a tri-state condition and forces the cascade interface output signals LHO[1:0] and BHO[2:0] to '0.' It also keeps the DQ Bus in Input mode. The purpose of this bit is to make sure that there is no bus contention when the devices power-up in the system.

TLSZ [3:2] 01

Table Size. The host ASIC must program this field to configure the chips into a table of a certain size. This field affects the pipeline latency of the SEARCH and LEARN operations as well as the READ and WRITE accesses to the SRAM (SADR[21:0], CE_L, OE_L, WE_L, ALE_L, SSV, SSF, and ACK). Once programmed, the SEARCH latency stays constant.

Latency #

CLK Cycles 00: 1 device 4 01: 2-8 devices 5 10: 9-31

devices

11: Reserved

HLAT [6:4] 000

Latency of Hit Signals. This field adds latency to the SSF, SSV, and ACK signals by the following number of CLK cycles during SEARCH and ACK during an SRAM READ access.

000: 0 100: 4 001: 1 101: 5 010: 2 110: 6 011: 3 111: 7

LDEV [7] 0

Last device in the cascade. When set, this device is the last device in the depth-cascaded table and is the default driver for the SSF and SSV signals. In the event of a SEARCH failure, the device with this bit set drives the hit signals as follows: SSF = 0, SSV = 1

During non-search cycles, the device with this bit set drives the signals as follows: SSF = 0, SSV = 0

LRAM [8] 0

Last device on this SRAM Bus. When set, this device is the last device on the SRAM bus in the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and ALE_L signals. In cycles where no M7010R device (in a depth-cascaded table) drives these signals, the signals are driven as follows: SADR = 22’h3FFFFF, CE_L = 1, WE_L = 1, and ALE_L = 1. OE_L is always driven by the device for which this bit is set.

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CFG [16:9]

0000 0000

Database Configuration. The device is internally divided into four quadrants of 8K x 68, each of which can be configured as 4K x 68, 2K x 136, or 1K x 272 as follows: 00: 4K x 68 01: 2K x 136 10: 1K x 272

11: Reserved Bits [10:9] apply to configuring the 1st quadrant in the address space.

Bits [12:11] apply to configuring the 2nd quadrant in the address space. Bits [14:13] apply to configuring the 3rd quadrant in the address space. Bits [16:15] apply to configuring the 4th quadrant in the address space.

[67:17] 0 Reserved.

Field Range Initial Value Description

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