SGS Thomson Microelectronics M59DR016C Datasheet

■ SUPPLY VOLTAGE

–V

= V

= 1.65V to 2.2V for Program,

DDQ

Erase and Read

–V

= 12V for fast Program (optional)

■ ASYNCHRONOUS PAGE MODE READ

– Page Width: 4 words – Page Access: 35ns – Random Access: 100ns

■ PROGRAMMING TIME

– 10µs by Word typical – Double Word Programming Option

■ MEMORY BLOCKS

– Dual Bank Memory Array: 4 Mbit - 12 Mbit – Parameter Blocks (Top or Bottom location)

■ DUAL BANK OPERATIONS

– Read within one Bank while Program or

Erase within the other

– No delay between Read and Write operations

■ BLOCK PROTECTION/UNPROTECTION

– All Blocks protected at Power Up – Any combination of Blocks can be protected

■ COMMON FLASH INTERFACE (CFI)

■ 64 bit SECURITY CODE

■ ERASE SUSPEND and RESUME MODES

■ 100,000 PROGRAM/ER ASE CYCL ES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Top Device Code, M59DR016C: 2293h – Bottom Device Code, M59DR016D: 2294h

M59DR016C M59DR016D

16 Mbit (1Mb x16, Dual Bank, Page)

1.8V Supply Flash Memory

PRODUCT PREVIEW

BGA

TFBGA48 (ZB)

8 x 6 balls array

Figure 1. Logic Diagram

DDQVPP

A0-A19

M59DR016C M59DR016D

DQ0-DQ15

AI04106

March 2001

This is preliminary information on a new product now in development. Details are subject to change without notice.

1/37

M59DR016C, M59DR016D

Figure 2. TFBGA Connections (Top view through package)

87654321

A13

A14

DDQ

DQ7V

A8A11

DQ13

Table 1. Signal Names

A0-A19 Address Inputs DQ0-DQ15 Data Input/Outputs, Command Inputs E G W RP WP V

DDQ

NC Not Connected Internally

Chip Enable Output Enable Write Enable Reset/Power Down Write Protect Supply Voltage Supply Voltage for Input/Output

Buffers Optional Supply Voltage for

Fast Program & Erase Ground

RP A18

DQ11

DQ12

DQ4

WP A19

DQ2

A7V

A5A17WA10

DQ0DQ9DQ3DQ6DQ15V

DQ1DQ10V

A1A3A6NCNCA9A12A15

A0EDQ8DQ5DQ14A16

AI04113

DESCRIPTION

The M59DR016 is a 16 Mbit non-volatile Flash memory that m ay be erased electrically a t block level and programmed in-system on a Word-byWord basis using a 1.65V to 2.2V V the circuitry. For Program and Erase operations the necessary high voltages are g enerated internally. The device supports asynchronous page mode from all the blocks of the memory array.

The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power Up. Blocks can be unprotected to make changes in the application and then reprotected.

Instructions for Read/Reset, Auto Select, Write Configuration Register, Programming, Block Erase, Bank Erase, Erase Suspend, Erase Resume, Block Protect, Block Unprotect, Block Locking, CFI Query, are written to the memory through a Command Interface using standard microprocessor write timings.

The device is offered in TFBGA48 (0.75 mm pitch) packages and it is supplied with all the bits erased

(set to ‘1’).

supply for

2/37

M59DR016C, M59DR016D

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

BIAS

STG

(3)

, V

DDQ

Note: 1. Except for the rating "Operat i ng Temperat ure Range", stresse s above th ose listed i n t he Table "Absolute M aximum Rat i ngs" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c onditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .

2. Depends on range.

3. Min i m um Voltage ma y undershoo t t o –2V during tr ansition and for less tha n 20ns.

Ambient Operating Temperature

Temperature Under Bias –40 to 125 °C Storage Temperature –55 to 155 °C

Input or Output Voltage Supply Voltage –0.5 to 2.7 V

Program Voltage –0.5 to 13 V

Organization

The M59DR016 is organized as 1Mb x16 bits. A0A19 are the address lines, DQ0-DQ15 are the Data Input/Output. Memory control is provided by Chip Enable E W

inputs.

Reset RP

, Output Enable G and Write Enable

is used to reset all the memory circuitry and to set the chip in power down mode if this function is enabled by a proper setting of the Configuration Register. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, DQ6 and DQ2 provide Toggle signals and DQ5 provides error bit to indicate the state of the P/E.C operations.

Memory Blocks

The device features asymmetrically blocked architecture. M59DR016 has an array of 39 blocks and is divided into two banks A and B, provid ing Dual

(1)

(2)

–40 to 85 °C

–0.5 to V

DDQ

+0.5

Bank A, read operations are possible into Bank B or vice versa. The memory also features an erase suspend allowing to read or program in another block within the same bank. Once suspended the erase can be resumed. The Bank Size and Sectorization are summarized in Table 7. Parameter Blocks are located at the top of the m emory address space for the M59DR016C, and at the bottom for the M59DR016D. The memory maps are shown in Tables 3, 4, 5 and 6.

The Program and Erase operation s are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. All blocks are protected at Power Up. Instructions are provided to protect or unprotect any block in the application. A second register locks the protection status while WP

is low (see B lock Locking description). The Reset command does not affect the configurati on of unprotected blo cks and the Configuration Register status.

Bank operations. While programming or erasing in

3/37

M59DR016C, M59DR016D

Table 3. Bank A, Top Boot Block Addresses M59DR016C

14 4 0FF000h-0FFFFFh 13 4 0FE000h-0FEFFFh 12 4 0FD000h-0FDFFFh 11 4 0FC000h-0FCFFFh 10 4 0FB000h-0FBFFFh

9 4 0FA000h-0FAFFFh 8 4 0F9000h-0F9FFFh 7 4 0F8000h-0F8FFFh 6 32 0F0000h-0F7FFFh 5 32 0E8000h-0EFFFFh 4 32 0E0000h-0E7FFFh 3 32 0D8000h-0DFFFFh 2 32 0D0000h-0D7FFFh 1 32 0C8000h-0CFFFFh 0 32 0C0000h-0C7FFFh

Size

(KWord)

Address Range

Table 4. Bank B, Top Boot Block Addresses M59DR016C

23 32 0B8000h-0BFFFFh 22 32 0B0000h-0B7FFFh 21 32 0A8000h-0AFFFFh 20 32 0A0000h-0A7FFFh 19 32 098000h-09FFFFh 18 32 090000h-097FFFh 17 32 088000h-08FFFFh 16 32 080000h-087FFFh 15 32 078000h-07FFFFh 14 32 070000h-077FFFh 13 32 068000h-06FFFFh 12 32 060000h-067FFFh 11 32 058000h-05FFFFh 10 32 050000h-057FFFh

9 32 048000h-04FFFFh 8 32 040000h-047FFFh 7 32 038000h-03FFFFh 6 32 030000h-037FFFh 5 32 028000h-02FFFFh 4 32 020000h-027FFFh 3 32 018000h-01FFFFh 2 32 010000h-017FFFh 1 32 008000h-00FFFFh 0 32 000000h-007FFFh

Size

(KWord)

Address Range

Table 5. Bank B, Bottom Boot Block Addresses M59DR016D

23 32 0F8000h-0FFFFFh 22 32 0F0000h-0F7FFFh 21 32 0E8000h-0EFFFFh 20 32 0E0000h-0E7FFFh 19 32 0D8000h-0DFFFFh 18 32 0D0000h-0D7FFFh 17 32 0C8000h-0CFFFFh 16 32 0C0000h-0C7FFFh 15 32 0B8000h-0BFFFFh 14 32 0B0000h-0B7FFFh 13 32 0A8000h-0AFFFFh 12 32 0A0000h-0A7FFFh 11 32 098000h-09FFFFh 10 32 090000h-097FFFh

9 32 088000h-08FFFFh 8 32 080000h-087FFFh 7 32 078000h-07FFFFh 6 32 070000h-077FFFh 5 32 068000h-06FFFFh 4 32 060000h-067FFFh 3 32 058000h-05FFFFh 2 32 050000h-057FFFh 1 32 048000h-04FFFFh 0 32 040000h-047FFFh

Size

(KWord)

Address Range

Table 6. Bank A, Bottom Boot Block Addresses M59DR016D

14 32 038000h-03FFFFh 13 32 030000h-037FFFh 12 32 028000h-02FFFFh 11 32 020000h-027FFFh 10 32 018000h-01FFFFh

9 32 010000h-017FFFh 8 32 008000h-00FFFFh 7 4 007000h-007FFFh 6 4 006000h-006FFFh 5 4 005000h-005FFFh 4 4 004000h-004FFFh 3 4 003000h-003FFFh 2 4 002000h-002FFFh 1 4 001000h-001FFFh 0 4 000000h-000FFFh

Size

(KWord)

Address Range

4/37

Table 7. Bank Size and Sectorization

Bank Size Parameter Blocks Main Blocks

Bank A 4 Mbit 8 blocks of 4 KWord 7 blocks of 32 KWord Bank B 12 Mbit - 24 blocks of 32 KWord

M59DR016C, M59DR016D

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1. Address Inputs (A0-A19). The address inputs

for the memory array are latched during a write operation on the falling edge of Chip Enable E Write Enable W

, whichever occurs last.

Data Input/Output (DQ0-DQ15). The Input is data to be programm ed in the memory array or a command to be written to the Command Interface (C.I.) Both input data and commands are latc hed on the rising edge of Write Enable W

. The Ouput is data from the Memory Array, the Common Flash Interface, the Electronic Signature Manufacturer or Device codes, the Block Protection status, the Configuration Register status or the Status Register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5. The data bus is high impedance when the chip is deselected, Output Enable G

is at VIH, or RP is at VIL.

Chip Enable (E

). The Chip Enable input acti-

vates the memory control logic, input buffers, decoders and sense amplifiers. E

at VIH deselects the memory and red uces the power consumption to the standby level. E

can also be used to control writing to the command register and to the memory array, while W

Output Enable (G

remains at VIL.

). The Output Enable gates the outputs through the data buffers during a read operation. When G

is at VIH the outputs are High im-

pedance.

Write Enable (W

). This input controls writing to

the Command Register and Data latches. Data are latched on the rising edge of W

Write Protect (WP

). This input gives an addition-

al hardware protection level against program or erase when pulled at V

, as described in the Block

Lock instruction description.

Reset/Power Down Input (RP

). The RP input

provides hardware reset of the memory (without affecting the Configuration Register status ), and/ or Power Down functions, depending on the Configuration Register status. Reset/Power Down of the memory is achieved by pulling RP least t

. When the reset pul se is given, if the

PLPH

to VIL for at

memory is in Read, Erase Suspend Read or Standby, it will output new valid data in t ter the rising edge of RP

. If the memory is in Erase

PHQ7V1

af-

or Program modes, the oper ation will be aborted

and the reset recovery will take a maximum ot t

. The memory will recover from Power

PLQ7V

Down (when enabled) in t edge of RP

and V

. See Tables 25, 26 and Figure 9.

Supply Voltage (1.65V to 2.2V).

DDQ

PHQ7V2

after the rising

The main power supply for all operations (Read, Program and Erase). V

and V

must be at

DDQ

the same voltage.

Programming Voltage (11.4V to 12.6V ). Used

to provide high voltage for fast factory programming. High voltage on V

pin is required to use

the Double Word Program instruction. It is also possible to perform word program or erase instructions with V

Ground. VSS is the reference for al l the vol t-

pin grounded.

age measurements.

DEVICE OPERATIONS

The following operations can be performed using the appropriate bus cycles: Read Array (Random, and Page Modes), Write command, Output Disable, Standby, Reset/Power Down and Block Locking. See Table 8.

Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register, the CFI, the Block Protection Status or the Configuration Register status. Read operation of the memory array is performed in asynchronous page mode, that provides fast access time. Data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by A0-A1 address inputs. Read operations of the Electroni c Signature, th e Status Register, the CFI, the Block Protection Status, the Configuration Register status and the Security Code are performed as single asyncronous read cycles (Random Read). Both Chip Enabl e E Output Enable G

must be at VIL in order to read the

and

output of the memory. Write. Write operations are used to give I nstruc-

tion Commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable E at V

with Output Enable G at VIH. Addresses are

latched on the falling edge of W

and Write Enable W are

or E whichever occurs last. Commands and Input Data are latched on the rising edge of W Noise pulses of less than 5ns typical on E

signals do not start a write cycle.

or E whichever occurs first.

, W and

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M59DR016C, M59DR016D

Table 8. User Bus Operations

(1)

Operation E G W RP WP DQ15-DQ0

Write Output Disable Standby

Reset / Power Down X X X Block Locking

Note: 1. X = Don’t care.

V V V V V

Table 9. Read Electronic Signature (AS and Read CFI instructions)

Code Device E

Manufacturer Code

M59DR016C

Device Code

M59DR016D

G W A0 A1 A7-A2

V V V

0 Don’t Care 00h 20h

0 Don’t Care 22h 93h

0 Don’t Care 22h 94h

Table 10. Read Block Protection (AS and Read CFI instructions)

Block Status E

Protected Block Unprotected Block Locked Block

G W A0 A1 A19-A12 A7-A2

ILVILVIHVILVIH

Block Address 0 Don’t Care 1 0 0000h Block Address 0 Don’t Care 0 0 0000h Block Address 0 Don’t Care X 1 0000h

Addresses

Other

Addresses

Other

Data Input

Hi-Z Hi-Z Hi-Z

DQ15-DQ8 DQ7-DQ0

DQ0 DQ1 DQ15-DQ2

Table 11. Read Configuration Register (AS and Read CFI instructions)

Function E G W A0 A1 A7-A2 Other Addresses DQ10

Reset Reset/Power Down

Dual Bank Operations. The Dual Bank allows to read data from one bank of memory while a program or erase operation is in progress in the other bank of the memory. Read and Write cycles can be initiated for simultaneous operations in different banks without any d elay. Status Register du ring Program or Erase must be monitored using an address within the bank being modified.

Output Disa bl e . The data outputs are high impedance when the Output Enable G Write Enable W

at VIH.

is at VIH with

Standby. The mem ory is in standby when Ch ip Enable E

is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G

or Write Enable W input s.

V V

0 Don’t Care 0 Don’t Care

0 Don’t Care 1 Don’t Care

Automatic Standby. When in Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus.

Power Down. The memory is in Power Down when the Configuration Register is set for Power Down and RP

is at VIL. The power consumption is reduced to the Power Down level, and Outputs are in high impedance, independent of the Chip Enable E

, Output Enable G or Write Enable W inputs.

Block Locking. Any combination of blocks can be temporarily protected against Program or Erase by setting the lock register and pulling WP to VIL (see Block Lock instruction).

DQ9-DQ0

DQ15-DQ11

6/37

M59DR016C, M59DR016D

INSTRUCTIONS AND COMMANDS

Seventeen instructions are defined (see Table

14), and the internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Dat a Polling, Toggle, Error bits can be read at any time, during programming or erase, to monitor the progress of the operation.

Instructions, made up of one or more com mands written in cycles, can be given to the Program/ Erase Controller through a Command Interface (C.I.). The C.I. latches comma nds written to the memory. Commands are made of address and data sequences. Two Coded Cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The Coded Sequence consists of writing the dat a AAh at the address 555h during the f irst cycle and the data 55h at the address 2AAh during the second cycle.

Instructi ons a re co mpose d of up to si x cycles. The first two cycles input a Coded Sequence to the Command Interface which is common to all instructions (see Table 14). T he third cycle inputs the instruction set-up command. Subseq uent cycles output the addressed data, Elect ronic Signature, Block Protection, Configuration Register Status or CFI Query for Read operations. In order to give additional data protection, the instructions for Block Erase and Bank Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For a Double Word Programming instruction, the fourth and fifth co mmand cycles input the address and data to be programmed. For a Block Eras e and Bank Erase instructions, the fourth and fifth cycles input a further Coded Sequence before the Erase confirm command on the sixth cycle. Any combination of blocks of the same memory bank can be erased. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied the command interface is reset to Read Array.

Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The inc reased number of cycles has been chosen to ensure maximum data security.

Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded Cycles. Subsequent read operations will r ead the memory array a ddressed and output the data read.

CFI Query (RCFI) Instruction. Common Flash Interface Query mode is entered writing 98h at address 55h. The CFI data structure gives information on the device, such as the sectorization, the command set and some el ectrical specifications. Tables 15, 19, 20 and 21 show the addresses used to retrieve each data. The CFI data structure contains also a se curity area; in this section, a 64 bit unique security number is written, starting at address 80h. This area can be accessed only in read mode by the final user and there are no ways of changing the code after it has been written by ST. Write a read instruction (RD) to return to Read mode.

Table 12. Commands

Hex Code Command

00h Bypass Reset 10h Bank Erase Confir m 20h Unlock Bypass 30h Block Erase Resume/Confirm 40h Double Word Program

Block Protect, or

60h

80h Set-up Erase

90h

98h CFI Query A0h Program B0h Erase Suspend F0h Read Array/Reset

Block Unprotect, or Block Lock, or Write Configuration Register

Read Electronic Signature, or Block Protection Status, or Configuration Register Status

7/37

M59DR016C, M59DR016D

Auto Select (AS) Instruction. This instruction

uses two Coded Cycles followed by one write cycle giving the command 90h to address 555h for command set-up. A subsequent read will output the Manufacturer or the Device Code (Electronic Signature), the Block Protection status or the Configuration Register status depending on the levels of A0 and A1 (see Tables 9, 10 and 11). A7-A2 must be at V

, while other address input are ig-

nored. The bank address is don’t care for this instruction. The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of M59DR016. The Manufacturer Code is output when the address lines A0 and A1 are at V put when A0 is at V

, the Device Code is out-

with A1 at VIL.

The codes are output on DQ0-DQ7 with DQ8DQ15 at 00h. The AS instruction also allows the access to the Block Protection Status. After giving the AS inst ructio n, A 0 is s et to V

with A1 at VIH,

while A12-A19 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected.

The AS Instruction finally allows the access to the Configuration Register status if both A0 and A1 are set to V is active as RP

. If DQ10 is '0' only the Reset function

is set to VIL (default at power-up). If DQ10 is '1' both the Reset and the Power Down functions will be achieved by pulling RP

to VIL. The other bits of the Configuration Register are reserved and must be ignored. A reset command puts the device in read array mode.

Write Configuration Register (CR) Instruction. This instruction uses t wo Coded Cyc les fol-

lowed by one write cycle giving the command 60h to address 555h. A further write cycle giving the command 03h writes the conte nts of address bi ts A0-A15 to the 16 bits configuration register. Bits written by inputs A0-A9 and A11-A15 are reserved for future use. Address input A10 defines the status of the Reset/Power Down functions. It must be set to V V

to enable only the Reset function and to

to enable also the Power Down function. At Power Up all the Con figuration Register bits are reset to '0'.

Enter Bypass Mode (EBY) Instruction. This instruction uses the two Coded cycles f ollowed by one write cycle giving the command 20h to address 555h for mode set-up. Once in Bypass mode, the device will accept the Exit Bypass

(XBY) and Program or Double Word Program in Bypass mode (PGBY, DPGBY) commands. The Bypass mode allows to reduce the overall programming time when large memory arrays need to be programmed.

Exit B y pa ss Mode (XBY) Ins t r u c t i o n. This instruction uses two write cycles. The first inputs to the memory the command 90h and the second inputs the Exit Bypass mode confirm (00h). After the XBY instruction, the device resets to Read Memory Array mode.

Program in Bypass Mode (PGBY) Instruction. This instruction uses two write cycles. The

Program command A0h is written to any Address on the first cycle and the second write cycle latches the Address on t he falling e dge of W or E and the Data to be written on the rising edge and starts the P/E.C. Read operations within the same bank output the Status Regist er bits after th e programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits D Q6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error.

Program (PG) Instruction. This ins truction uses four write cycles. The Program command A0h is written to address 555h on the third cycle after two Coded Cycles. A fourth write operation latches the Address and the Dat a to be writte n a nd starts the P/E.C. Read operations within the same bank output the Status Register bits after the programming has started. Memory program ming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Programming at an address not in blocks being erased is also possible during erase suspend.

Double Word Program (DPG) Instruction. This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. High voltage (11.4V to 12.6V) on V

pin is required. This instruction uses five write cycles. The double word program command 40h is written to address 555h on the third cycle after two Coded Cycles. A fourth write cycle latches the address and data to be written to the first location. A fifth write cycle latches the new data to be written to the second location and starts the P/E.C.. Note that the two locations must have the same address except for the address bit A0. The Double Word Program can be executed in Bypass mode (DPGBY) to skip the two coded cycles at the beginning of each command.

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M59DR016C, M59DR016D

Table 13. Protection States

(2)

Current State

, DQ1, DQ0)

(WP

100 yes 101 100 111 000 101 no 10 1 100 111 001 110 yes 111 110 111 011 111 no 11 1 110 111 011 000 yes 001 000 011 100 001 no 00 1 000 011 101

011 no 01 1 011 011

Note: 1. All blo cks are protected at power-up, so the default configuration i s 001 or 101 acc ording to WP status.

2. Cur rent state and Next st at e gi ves the protection s ta tus of a bloc k. The protection sta tus is define d by the writ e protect pin and by DQ1 (= 1 for a loc ked block) an d DQ0 (= 1 for a prot ected block ) as read in the A ut oselect inst ruction with A1 = V

3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP its logic value.

4. A WP

transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

Program/Erase

Allowed

Block Protect (BP), Blo ck Unprotect (BU), Block Lock (BL) Instructions. All blocks are

protected at power-up. Each block of the array has two levels of protection against program or erase operation. The first level is set by the Block Protect instruction; a protected block cannot be programmed or erased until a Block Unprotect instruction is given for that block. A second l evel of protection is set by the Block Lock instruction, and requires the use of the WP following scheme:

– when WP

is at VIH, the Lock status is overridden

and all blocks can be protected or unprotected;

– when WP

is at VIL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Bloc ks that are not locked can still change their protection status, and program or erase accordingly;

– the lock status is cleared for all blocks at power

up; once a block ha s been locke d state can be cleared only with a reset command. The protection and lock status can be monit ored for each block using the Autoselect (AS) instruction. Protected blocks will output a ‘1’ on DQ0 and locked blocks will output a ‘1’ on DQ1.

Refer to Table 13 for a list of the protection states. Block Erase (BE) Instruction. This instruction

uses a minimum of six write cycles. The Erase Set-up command 80h is written to ad dress 555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles and an address within the block to be erased is given and latched into the memory.

(1)

Protect Unprotect Lock WP transition

pin, according to t he

Next State After Event

(3)

111 or 110

Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks i n paral l el, wit h out fu rthe r Co ded cycles. All blocks must belong to the same bank of memory; if a new block belonging to the other bank is given, the operation is aborted. The erase will start after an erase timeout period of 100µs. Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the in ternal timer can be monitored through the level of DQ3, if DQ3 is '0' the Block Erase Command has been given and the timeout is running, if DQ3 is '1', the timeout has expired and the P/E.C. is erasing the Block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do t his a uto matically before erasing to FFh. Read operations within the same bank, after the sixth rising edge of W or E, output the status register bits.

During the execution of the erase by the P/E.C., the memory accepts only the Erase Suspend ES instruction; the Read/Reset RD instruction is accepted during the 100µs time-out period. Data Polling b it DQ7 retur ns '0' while the erasur e is in progress and '1' when it has com pleted. The Toggle bit DQ6 toggles during the erase operation, and stops when erase is completed.

After completion the Status Re gister bit DQ5 returns '1' if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C.

(4)

and A0 = VIL.

has changed

9/37

M59DR016C, M59DR016D

Bank Erase (BKE) Instruction. This instruction

uses six write cycles and is used to e rase all the blocks belonging to the selected bank. The Erase Set-up command 80h is written to ad dress 555h on the third cycle after the two Coded cycles. The Bank Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles at an address within the selected bank. If the second command gi ven is not an erase confirm or if the Coded cy cles are wrong, the instruction aborts and the device is reset to Read A rray. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations within the same bank after the sixth rising edge of W

or E output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The Toggle bit DQ6 toggles during erase operation and stops when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure.

Erase Suspend (ES) Instruction. In a dual bank memory the Erase Suspend instruction is used to read data within the bank where erase is in

progress. It is also possible to program data in blocks not being erased.

The Erase Suspend in struction con sists o f writing the command B0h without any s pecific address. No Coded Cycles are requ ired. Erase s uspend is accepted only during the Block Erase i nstruction execution. The Toggle bit DQ6 stops toggling

when the P/E.C. is suspended within 15µs after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is suspended, a Read from blocks being erased will output DQ2 toggling and DQ 6 at '1'. A Read from a block not being erased returns valid data. During suspens ion the memory w ill respond only to the Erase Resume ER and the Program PG instructions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in DQ6 toggling when the data is being programmed.

Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously exec uted, the erase operation may be resumed by giving the command 30h, at an address within the bank being erased and without any Coded Cycle.

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M59DR016C, M59DR016D

Table 14. Instructions

(1,2)

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.

Read/Reset

(4)

Memory Array

(3)

Addr.

Data F0h Addr. 555h 2AAh 555h

Data AAh 55h F0h

Read Memory Array until a new write cycle is initiated.

Addr. 55h

RCFI CFI Query 1+

Read CFI data until a new write cycle is initiated.

Data 98h Addr. 555h 2AAh 555h Read electronic Signature or

(4)

Auto Select 3+

Configuration

Data AAh 55h 90h

Addr. 5 55h 2AAh 555h

Block Protection or Configuration Register Status until a new cycle is initiated.

Configuration Data

Data AAh 55h 60h 03h

Program Address

Program

Data

Program

Address 1

Program

Data 1

Read Data Polling or Toggle Bit until Program completes.

Program

Address 2

Note 6, 7

Program

Data 2

PG Program 4

EBY

XBY

Double Word Program

Enter Bypass Mode

Exit Bypass Mode

DPG

Addr. 555h 2AAh 555h

Data AAh 55h A0h

Addr. 5 55h 2AAh 555h

Data AAh 55h 40h

Addr. 555h 2AAh 555h

Data AAh 55h 20h Addr. XX

Data 90h 00h

PGBY

Program in Bypass Mode

Double Word

DPGBY

Program in Bypass Mode

BP Block Protect 4

BU Block Unprotect 1

Addr. X

Data A0h

Addr. X

Program Address

Program

Data

Program

Address 1

Read Data Polling or Toggle Bit until Program completes.

Program

Address 2

Data 40h

Program

Data 1

Program

Data 2

Addr. 555h 2AAh 555h

Data AAh 55h 60h 01h

Addr. 555h 2AAh 555h

Data AAh 55h 60h D0h

Note 6, 7

Block

Address

Block

Address

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M59DR016C, M59DR016D

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.

BL Block Lock 4

Addr. 555h 2AAh 555h

Data AAh 55h 60h 2Fh

Block

Address

BE Block Erase 6+

Addr. 555h 2AAh 555h 555h 2AAh

Data AAh 55h 80h AAh 55h 30h

Addr. 555h 2AAh 555h 555h 2AAh

BKE Bank Erase 6

Data AAh 55h 80h AAh 55h 10h

ES Erase Suspend 1

ER Erase Resume 1

(3)

Addr. Data B0h

Addr.

Bank

Address

Read until Toggle stops, then read all the data needed from any Blocks not being erased then Resume Erase.

Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time

Data 30h

Note: 1. Commands not interpreted in this table will default to read array mode.

2. For Coded cycl es address inp uts A11-A19 are don’t care.

3. X = Don’t Care.

4. The first cycles of th e RD or AS in st ructions are follo wed by read operations. Any number of read cycles can occur after the command cycl e s.

5. Dur i ng Erase Suspend, Read and Data Program functions are allowed in blocks not bei ng erased.

6. Program Address 1 and Program Address 2 must be consecutive a ddresses dif f eri ng only for address bit A0.

7. High voltage on V

(11.4V to 12.6V) is required for th e proper execution of t he Double Wo rd P rogram instruction .

Block

Address

Bank

Address

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