SGS Thomson Microelectronics M59DR008F, M59DR008E Datasheet

M59DR008E
M59DR008F
8 Mbit (512Kb x1 6, Dual Bank, Pa ge) Low Voltag e Flash Memor y
PRODUCT PREVIEW
SUPPLY VOLTAGE
= V
DD
Erase and Read
= 12V: o ptional Supply Voltage for fast
PP
Program and Erase
ASYNCHRONOUS PAGE MODE READ
– Page Width: 4 words – Page Access: 35ns – Random Access: 100ns
PROGRAMMING TIME
– 10µs by Word typical – Double Word Programming Option
MEMORY BLOCKS
– Dual Ba nk Memory Ar ray: 4 M b i t - 4 Mbit – Parameter Blocks (Top or Bott o m location) – Main Blocks
DUAL BANK OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
BLOCK PROTECTION/UNPROTECTION
– All Blocks protected at Power Up – Any combination of Blocks can be protected
for Block Locking
–WP
COMMON FLASH INTERFACE (CFI)
64 bit SECURITY CODE
ERASE SUSPEND and RESUME MODES
100,000 PROGRAM/ER ASE CYCL ES per
BLOCK
20 YEARS DATA RETENTI ON
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h – Device Code, M59DR008E: A2h – Device Code, M59DR008F: A3h
= 1.65V to 2.2V: for Program,
DDQ
TSOP48 (N)
12 x 20mm
Figure 1. Logic Diagram
V
V
DDQVPP
DD
19
A0-A18
W
E
G
RP
WP
M59DR008E M59DR008F
V
SS
BGA
FBGA48 (ZB)
8 x 6 solder balls
16
DQ0-DQ15
AI03212
October 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/37
M59DR008E, M59DR008F
Figure 2A. FBGA Connections (Top View)
87654321
A
B
C
D
E
F
V
DDQ
SS
Figure 2B. TSOP Connections
A15
1 A14 A13 A12 A11 A10 DQ14
A9
A8 NC NC
W
RP
12
M59DR008E
V
WP
A18 A17
PP
NC
A7
A6
A5
A4
A3
A2
A1
M59DR008F
13
24 25
AI03214
DQ15
DQ7V
48
37 36
A16 V
DDQ
V
SS
DQ15 DQ7
DQ6 DQ13 DQ5 DQ12 DQ4 V
DD
DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G V
SS
E A0
A8A11A13
DQ13
PP
RP A18
DQ11
DQ12
DQ4
WP DU
DQ2
DD
Table 1. Signal Names
A0-A18 Address Inputs DQ0-DQ15 Data Input/Outputs, Command Inputs E G W RP WP V
DD
V
DDQ
V
PP
V
SS
NC Not Connected Internally DU Don’t use as internally connected
A7V
A5A17WA10A14
DQ0DQ9DQ3DQ6
DQ1DQ10V
A4
A2
A1A3A6DUDUA9A12A15
A0EDQ8DQ5DQ14A16
V
SS
G
AI03213B
Chip Enable Output Enable Write Enable Reset/Power Down Write Protect Circuitry Supp ly Voltage Input/Output Buffers Supply Voltage Optional Supply Voltage for
Fast Program & Erase Ground
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M59DR008E, M59DR008F
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(3)
V
IO
, V
V
DD
DDQ
V
PP
Note: 1. Except for th e rating "Operating Temperature Range", stresses above those listed i n the Tabl e "Absolute M aximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c ondi­tions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ­ity docum en ts .
2. Depends on range.
3. Minim um Voltage may undershoot to –2V duri ng transit i on and for less than 20ns.
Ambient Operating Temperature
Temperature Under Bias –40 to 125 °C Storage Temperature –55 to 155 °C
Input or Output Voltage Supply Voltage –0.5 to 2.7 V
Program Voltage –0.5 to 13 V
DESCRIPTION
The M59DR008 is an 8 Mbit non-volatile Flash memory that m ay be erased electrically a t block level and programmed i n-system on a Word-by­Word basis using a 1.65V to 2.2V V the circuitry. For Program and Erase operations the necessary high voltages are g enerated inter­nally. The device supports asynchronous page mode from all the blocks of the memory array.
The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against pro­gramming and erase at Power Up. Blocks can be unprotected to make changes in the application and then reprotected.
Instructions for Read/Reset, Auto Select, Write Configuration Register, Programming, Block Erase, Bank Erase, Erase Suspend, Erase Re­sume, Block Protect, Block Unprotect, Block Lock­ing, CFI Query, are written to the memory through a Command Interface using standard micropro­cessor write timings.
The device is offered in TSOP48 (12 x 20 mm) and in FBGA48 0.75 mm ball pitch packages.
When shipped all bits of the M59DR008 device are
at the logical level ‘1’.
Organization
The M59DR008 is organ ized as 512Kb x16 bits. A0-A18 are the address l ines, DQ0 -DQ15 are the Data Input/Output. Memory control is provided by Chip Enable E W
inputs.
, Output Enable G and Write Enable
(1)
supply for
DD
(2)
–40 to 85 °C
Reset RP
–0.5 to V
is used to reset all the memory circuitry
DDQ
+0.5
V
and to set the chip in power down mode if this function is enabled by a proper setting of the Con­figuration Register. Erase and Program operations are controlled by an internal Program/Erase Con­troller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, DQ6 and DQ2 provide Toggle signals and DQ5 provides error bit to indicate the state of the P/E.C operations.
Memory Blocks
The device features asymmetrically blocked archi­tecture. M59DR008 has an array of 23 blocks and is divided into two banks A and B, prov iding D ual Bank operations. While programming or erasing in Bank A, read operations are possible into Bank B or vice versa. The memory also features an erase suspend allowing to read or program in another block within the same bank. Once suspended the erase can be resumed. The Bank Size and Sector­ization are summarized in Table 7. Parameter Blocks are located at the top of the m emory ad­dress space for the M59DR008E, and at the bo t­tom for the M59DR008F. The memory maps are shown in Tables 3, 4, 5 and 6.
The Program and Erase operation s are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. All blocks are protected at Power Up. In­structions are provided to protect or unprotect any block in the application. A second register locks the protection status while WP
is low (see B lock Locking description). The Reset command does not affect the configurati on of unprotected blo cks and the Configuration Register status.
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M59DR008E, M59DR008F
Table 3. Bank A, To p B oot Block Ad dress
Size (KWord) Address Range
4 7F000-7FFFF 4 7E000-7EFFF 4 7D000-7DFFF 4 7C000-7CFFF 4 7B000-7BFFF 4 7A000-7AFFF 4 79000-79FFF
4 78000-78FFF 32 70000-77FFF 32 68000-6FFFF 32 60000-67FFF 32 58000-5FFFF 32 50000-57FFF 32 48000-4FFFF 32 40000-47FFF
Table 5. Bank B, Bottom Boot Block Address
Size (KWord) Address Range
32 78000-7FFFF 32 70000-77FFF 32 68000-6FFFF 32 60000-67FFF 32 58000-5FFFF 32 50000-57FFF 32 48000-4FFFF 32 40000-47FFF
Table 6. Bank A, Bottom Boot Block Address
Size (KWord) Address Range
32 38000-3FFFF 32 30000-37FFF 32 28000-2FFFF 32 20000-27FFF 32 18000-1FFFF
Table 4. Bank B, To p B oot Block Ad dress
Size (KWord) Address Range
32 38000-3FFFF 32 30000-37FFF 32 28000-2FFFF 32 20000-27FFF 32 18000-1FFFF 32 10000-17FFF 32 08000-0FFFF 32 00000-07FFF
32 10000-17FFF 32 08000-0FFFF
4 07000-07FFF 4 06000-06FFF 4 05000-05FFF 4 04000-04FFF 4 03000-03FFF 4 02000-02FFF 4 01000-01FFF 4 00000-00FFF
4/37
Table 7. Bank Size and Sectorization
Bank Size Parameter Blocks Main Blocks
Bank A 4 Mbit 8 blocks of 4 KWord 7 blocks of 32 KWord Bank B 4 Mbit - 8 blocks of 32 KWord
M59DR008E, M59DR008F
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1. Address Inputs (A0-A18). The address inputs
for the memory array are latched during a write op­eration on the falling edge of Chip Enable E Write Enable W
, whichever occurs last.
or
Data Input/Output (DQ0-DQ15). The Input is data to be programm ed in the memory array or a command to be written to the Command Interface (C.I.) Both input data and commands are latc hed on the rising edge of Write Enable W
. The Ouput is data from the Memory Array, the Common Flash Interface, the Electronic Signature Manufacturer or Device codes, the Block Protection status, the Configuration Register status or the Status Regis­ter Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5. The data bus is high im­pedance when the chip is deselected, Output En­able G
is at VIH, or RP is at VIL.
Chip Enable (E
). The Chip Enable input acti-
vates the memory control logic, input buffers, de­coders and sense amplifiers. E
at VIH deselects the memory and red uces the power consumption to the standby level. E
can also be used to control writing to the command register and to the memo­ry array, while W
Output Enable (G
remains at VIL.
). The Output Enable gates the outputs through the data buffers during a read op­eration. When G
is at VIH the outputs are High im-
pedance.
Write Enable (W
). This input controls writing to
the Command Register and Data latches. Data are latched on the rising edge of W
Write Protect (WP
). This input gives an addition-
.
al hardware protection level against program or erase when pulled at V
, as described in the Block
IL
Lock instruction description.
Reset/Power Down Input (RP
). The RP input
provides hardware reset of the memory (without affecting the Configuration Register status ), and/ or Power Down functions, depending on the Con­figuration Register status. Reset/Power Down of the memory is achieved by pulling RP least t
. When the reset pul se is given, if the
PLPH
to VIL for at
memory is in Read, Erase Suspend Read or Standby, it will output new valid data in t ter the rising edge of RP
. If the memory is in Erase
PHQ7V1
af-
or Program modes, the oper ation will be aborted
and the reset recovery will take a maximum ot t
. The memory will recover from Power
PLQ7V
Down (when enabled) in t edge of RP
and V
V
DD
. See Tables 25, 26 and Figure 9.
Supply Voltage (1.65V to 2.2V).
DDQ
PHQ7V2
after the rising
The main power supply for all operations (Read, Program and Erase). V
and V
DD
must be at
DDQ
the same voltage.
V
Programming Voltage (11.4V to 12.6V ). Used
PP
to provide high voltage for fast factory program­ming. High voltage on V
pin is required to use
PP
the Double Word Program instruction. It is also possible to perform word program or erase instruc­tions with V
Ground. VSS is the reference for al l the vol t-
V
SS
pin grounded.
PP
age measurements.
DEVICE OPERATIONS
The following operations can be performed using the appropriate bus cycles: Read Array (Random, and Page Modes), Write command, Output Dis­able, Standby, Reset/Power Down and Block Locking. See Table 8.
Read. Read operations are used to output the contents of the Memory Array, the Electronic Sig­nature, the Status Register, the CFI, the Block Protection Status or the Configuration Register status. Read operation of the memory array is per­formed in asynchronous page mode, that provides fast access time. Data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by A0-A1 address inputs. Read operations of the Electroni c Signature, th e Status Register, the CFI, the Block Protection Status, the Configuration Register status and the Security Code are performed as single asyncronous read cycles (Random Read). Both Chip Enabl e E Output Enable G
must be at VIL in order to read the
and
output of the memory. Write. Write operations are used to give I nstruc-
tion Commands to the memory or to latch Input Data to be programmed. A write operation is initi­ated when Chip Enable E at V
with Output Enable G at VIH. Addresses are
IL
latched on the falling edge of W
and Write Enable W are
or E whichever oc­curs last. Commands and Input Data are latched on the rising edge of W Noise pulses of less than 5ns typical on E
signals do not start a write cycle.
G
or E whichever occurs first.
, W and
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M59DR008E, M59DR008F
Table 8. User Bus Operations
(1)
Operation E G W RP WP DQ15-DQ0
Write Output Disable Standby
V
IL
V
IL
V
IH
Reset / Power Down X X X Block Locking
Note: 1. X = Don’t care.
V
IL
V
IH
V
IH
V
IL
V
IH
XX
XX
V V V V V
Table 9. Read Electronic Signature (AS and Read CFI instructions)
Code Device E
Manufacturer Code
M59DR008E
Device Code
M59DR008F
G W A0 A1 A7-A2
V
V
V
IL
IL
V
V
IL
IL
V
V
IL
IL
V
IH
IL
V
V
IH
IH
V
V
IH
IH
V V V
0 Don’t Care 00h 20h
IL
0 Don’t Care 00h A2h
IL
0 Don’t Care 00h A3h
IL
Table 10. Read Block Protection (AS and Read CFI instructions)
Block Status E
Protected Block Unprotected Block Locked Block
G W A0 A1 A18-A12 A7-A2
V
ILVILVIHVILVIH
V
ILVILVIHVILVIH
V
ILVILVIHVILVIH
Block Address 0 Don’t Care 1 0 0000h Block Address 0 Don’t Care 0 0 0000h Block Address 0 Don’t Care X 1 0000h
Addresses
IH
IH
IH
IL
IH
Other
Addresses
Other
V
IH
V
IH
V
IH
V
IH
V
IL
Data Input
Hi-Z Hi-Z Hi-Z
X
DQ15-DQ8 DQ7-DQ0
DQ0 DQ1 DQ15-DQ2
Table 11. Read Configuration Register (AS and Read CFI instructions)
RP
Function E G W A0 A1 A7-A2 Other Addresses DQ10
V
V
V
V
Reset Reset/Power Down
IL
IL
IH
IH
V
V
V
IL
IL
V
IH
IH
Dual Bank Operations. The Dual Bank allows to read data from one bank of memory while a pro­gram or erase operation is in progress in the other bank of the memory. Read and Write cycles can be initiated for simultaneous operations in different banks without any d elay. Status Register du ring Program or Erase must be monitored using an ad­dress within the bank being modified.
Output Disa bl e . The data outputs are high im­pedance when the Output Enable G Write Enable W
at VIH.
is at VIH with
Standby. The mem ory is in standby when Ch ip Enable E
is at VIH and the P/E.C. is idle. The pow­er consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G
or Write Enable W input s.
V V
0 Don’t Care 0 Don’t Care
IH
0 Don’t Care 1 Don’t Care
IH
Automatic Standby. When in Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically en­ters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while out­puts still drive the bus.
Power Down. The memory is in Power Down when the Configuration Register is set for Power Down and RP
is at VIL. The power consumption is reduced to the Power Down level, and Outputs are in high impedance, independent of the Chip En­able E
, Output Enable G or Write Enable W inputs.
Block Locking. Any combination of blocks can be temporarily protected against Program or Erase by setting the lock register and pulling WP to VIL (see Block Lock instruction).
DQ9-DQ0
DQ15-DQ11
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M59DR008E, M59DR008F
INSTRUCTIONS AND COMMANDS
Seventeen instructions are defined (see Table 14A), and the internal P /E.C. automatically han­dles all timing and verification of the Pr ogram and Erase operations. The Status Register Dat a Poll­ing, Toggle, Error bits can be read at any time, dur­ing programming or erase, to monitor the progress of the operation.
Instructions, made up of one or more com mands written in cycles, can be given to the Program/ Erase Controller through a Command Interface (C.I.). The C.I. latches comma nds written to the memory. Commands are made of address and data sequences. Two Coded Cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The Coded Sequence consists of writing the dat a AAh at the address 555h during the f irst cycle and the data 55h at the address 2AAh during the second cycle.
Instructi ons a re co mpose d of up to si x cycles. The first two cycles input a Coded Sequence to the Command Interface which is common to all in­structions (see Table 14A). T he third cycle inputs the instruction set-up command. Subseq uent cy­cles output the addressed data, Elect ronic Signa­ture, Block Protection, Configuration Register Status or CFI Query for Read operations. In order to give additional data protection, the instructions for Block Erase and Bank Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For a Double Word Program­ming instruction, the fourth and fifth co mmand cy­cles input the address and data to be programmed. For a Block Eras e and Bank Erase instructions, the fourth and fifth cycles input a fur­ther Coded Sequence before the Erase confirm command on the sixth cycle. Any combination of blocks of the same memory bank can be erased. Erasure of a memory block may be suspended, in order to read data from another block or to pro­gram data in another block, and then resumed. When power is first applied the command interface is reset to Read Array.
Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The inc reased number of cycles has been chosen to ensure maximum data security.
Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded Cycles. Subsequent read opera­tions will r ead the memory array a ddressed and output the data read.
CFI Query (RCFI) Instruction. Common Flash Interface Query mode is entered writing 98h at ad­dress 55h. The CFI data structure gives informa­tion on the device, such as the sectorization, the command set and some el ectrical specifications. Tables 15, 16, 17 and 18 show the addresses used to retrieve each data. The CFI data structure contains also a se curity area; in this section, a 64 bit unique security number is written, starting at address 80h. This area can be accessed only in read mode by the final user and there are no ways of changing the code after it has been written by ST. Write a read instruction (RD) to return to Read mode.
Table 12. Commands
Hex Code Command
00h Bypass Reset 10h Bank Erase Confir m 20h Unlock Bypass 30h Block Erase Resume/Confirm 40h Double Word Program
Block Protect, or
60h
80h Set-up Erase
90h
98h CFI Query A0h Program B0h Erase Suspend F0h Read Array/Reset
Block Unprotect, or Block Lock, or Write Configuration Register
Read Electronic Signature, or Block Protection Status, or Configuration Register Status
7/37
M59DR008E, M59DR008F
Auto Select (AS) Instruction. This instruction
uses two Coded Cycles followed by one write cy­cle giving the command 90h to address 555h for command set-up. A subsequent read will output the Manufacturer or the Device Code (Electronic Signature), the Block Protection status or the Con­figuration Register status depending on the levels of A0 and A1 (see Tables 9, 10 and 11). A7-A2 must be at V
, while other address input are ig-
IL
nored. The bank address is don’t care for this in­struction. The Electronic Signature can be read from the memory allowing programming equip­ment or applications to automatically match their interface to the characteristics of M59DR008. The Manufacturer Code is output when the address lines A0 and A1 are at V put when A0 is at V
, the Device Code is out-
IL
with A1 at VIL.
IH
The codes are output on DQ0-DQ7 with DQ8­DQ15 at 00h. The AS instruction also allows the access to the Block Protection Status. After giving the AS inst ructio n, A 0 is s et to V
with A1 at VIH,
IL
while A12-A18 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected.
The AS Instruction finally allows the access to the Configuration Register status if both A0 and A1 are set to V is active as RP
. If DQ10 is '0' only the Reset function
IH
is set to VIL (default at power-up). If DQ10 is '1' both the Reset and the Power Down functions will be achieved by pulling RP
to VIL. The other bits of the Configuration Register are re­served and must be ignored. A reset command puts the device in read array mode.
Write Configuration Register (CR) Instruc­tion. This instruction uses t wo Coded Cyc les fol-
lowed by one write cycle giving the command 60h to address 555h. A further write cycle giving the command 03h writes the conte nts of address bi ts A0-A15 to the 16 bits configuration register. Bits written by inputs A0-A9 and A11-A15 are reserved for future use. Address input A10 defines the sta­tus of the Reset/Power Down functions. It must be set to V V
IH
to enable only the Reset function and to
IL
to enable also the Power Down function. At Power Up all the Con figuration Register bits are reset to '0'.
Enter Bypass Mode (EBY) Instruction. This in­struction uses the two Coded cycles f ollowed by one write cycle giving the command 20h to ad­dress 555h for mode set-up. Once in Bypass mode, the device will accept the Exit Bypass
(XBY) and Program or Double Word Program in Bypass mode (PGBY, DPGBY) commands. The Bypass mode allows to reduce the overall pro­gramming time when large memory arrays need to be programmed.
Exit B y pa ss Mode (XBY) Ins t r u c t i o n. This in­struction uses two write cycles. The first inputs to the memory the command 90h and the second in­puts the Exit Bypass mode confirm (00h). After the XBY instruction, the device resets to Read Memo­ry Array mode.
Program in Bypass Mode (PGBY) Instruc­tion. This instruction uses two write cycles. The
Program command A0h is written to any Address on the first cycle and the second write cycle latch­es the Address on t he falling e dge of W or E and the Data to be written on the rising edge and starts the P/E.C. Read operations within the same bank output the Status Regist er bits after th e program­ming has started. Memory programming is made only by writing '0' in place of '1'. Status bits D Q6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error.
Program (PG) Instruction. This ins truction uses four write cycles. The Program command A0h is written to address 555h on the third cycle after two Coded Cycles. A fourth write operation latches the Address and the Dat a to be writte n a nd starts the P/E.C. Read operations within the same bank out­put the Status Register bits after the programming has started. Memory program ming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Pro­gramming at an address not in blocks being erased is also possible during erase suspend.
Double Word Program (DPG) Instruction. This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. High voltage (11.4V to 12.6V) on V
PP
pin is required. This instruction uses five write cy­cles. The double word program command 40h is written to address 555h on the third cycle after two Coded Cycles. A fourth write cycle latches the ad­dress and data to be written to the first location. A fifth write cycle latches the new data to be written to the second location and starts the P/E.C.. Note that the two locations must have the same address except for the address bit A0. The Double Word Program can be executed in Bypass mode (DPG­BY) to skip the two coded cycles at the beginning of each command.
8/37
M59DR008E, M59DR008F
Table 13. Protection States
(2)
Current State
, DQ1, DQ0)
(WP
100 yes 101 100 111 000 101 no 10 1 100 111 001 110 yes 111 110 111 011 111 no 11 1 110 111 011 000 yes 001 000 011 100 001 no 00 1 000 011 101
011 no 01 1 011 011
Note: 1. All blocks are protected at power-up, s o th e default configuration is 001 or 101 ac cording to WP status.
2. Current state a nd Next state gi ves the pr ot ection sta t us of a block . The protec tion status is defined by the write pr otect pin and by DQ1 (= 1 for a loc ked block) an d DQ0 (= 1 for a prot ected block ) as read in the A ut oselect inst ruction with A1 = V
3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP its logic value.
4. A WP
transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
Program/Erase
Allowed
Block Protect (BP), Blo ck Unprotect (BU), Block Lock (BL) Instructions. All blocks are
protected at power-up. Each block of the array has two levels of protection against program or erase operation. The first level is set by the Block Protect instruction; a protected block cannot be pro­grammed or erased until a Block Unprotect in­struction is given for that block. A second l evel of protection is set by the Block Lock instruction, and requires the use of the WP following scheme:
– when WP
is at VIH, the Lock status is overridden
and all blocks can be protected or unprotected;
– when WP
is at VIL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Bloc ks that are not locked can still change their protection status, and pro­gram or erase accordingly;
– the lock status is cleared for all blocks at power
up; once a block ha s been locke d state can be cleared only with a reset command. The protec­tion and lock status can be monit ored for each block using the Autoselect (AS) instruction. Pro­tected blocks will output a ‘1’ on DQ0 and locked blocks will output a ‘1’ on DQ1.
Refer to Table 13 for a list of the protection states. Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase Set-up command 80h is written to ad dress 555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles and an address within the block to be erased is given and latched into the memory.
(1)
Protect Unprotect Lock WP transition
pin, according to t he
Next State After Event
(3)
111 or 110
IH
Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks i n paral l el, wit h out fu rthe r Co d­ed cycles. All blocks must belong to the same bank of memory; if a new block belonging to the other bank is given, the operation is aborted. The erase will start after an erase timeout period of 100µs. Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the in ter­nal timer can be monitored through the level of DQ3, if DQ3 is '0' the Block Erase Command has been given and the timeout is running, if DQ3 is '1', the timeout has expired and the P/E.C. is erasing the Block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do t his a uto mati­cally before erasing to FFh. Read operations with­in the same bank, after the sixth rising edge of W or E, output the status register bits.
During the execution of the erase by the P/E.C., the memory accepts only the Erase Suspend ES instruction; the Read/Reset RD instruction is ac­cepted during the 100µs time-out period. Data Polling b it DQ7 retur ns '0' while the erasur e is in progress and '1' when it has com pleted. The Tog­gle bit DQ6 toggles during the erase operation, and stops when erase is completed.
After completion the Status Re gister bit DQ5 re­turns '1' if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to de­termine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C.
(4)
and A0 = VIL.
has changed
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M59DR008E, M59DR008F
Bank Erase (BKE) Instruction. This instruction
uses six write cycles and is used to e rase all the blocks belonging to the selected bank. The Erase Set-up command 80h is written to ad dress 555h on the third cycle after the two Coded cycles. The Bank Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles at an address within the selected bank. If the second command gi ven is not an erase con­firm or if the Coded cy cles are wrong, the instruc­tion aborts and the device is reset to Read A rray. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations within the same bank after the sixth rising edge of W
or E output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit DQ7 re­turns ’0’, then ’1’ on completion. The Toggle bit DQ6 toggles during erase operation and stops when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure.
Erase Suspend (ES) Instruction. In a dual bank memory the Erase Suspend instruction is used to read data within the bank where erase is in
progress. It is also possible to program data in blocks not being erased.
The Erase Suspend in struction con sists o f writing the command B0h without any s pecific address. No Coded Cycles are requ ired. Erase s uspend is accepted only during the Block Erase i nstruction execution. The Toggle bit DQ6 stops toggling
when the P/E.C. is suspended within 15µs after the Erase Suspend (ES) command has been writ­ten. The device will then automatically be set to Read Memory Array mode. When erase is sus­pended, a Read from blocks being erased will out­put DQ2 toggling and DQ 6 at '1'. A Read from a block not being erased returns valid data. During suspens ion the memory w ill respond only to the Erase Resume ER and the Program PG instruc­tions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in DQ6 toggling when the data is being programmed.
Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously exec uted, the erase operation may be resumed by giving the command 30h, at an address within the bank be­ing erased and without any Coded Cycle.
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M59DR008E, M59DR008F
Table 14A. Instructions
(1,2)
Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.
RD
Read/Reset
(4)
Memory Array
(3)
Addr.
1+
Data F0h Addr. 555h 2AAh 555h
3+
Data AAh 55h F0h
X
Read Memory Array until a new write cycle is initiated.
Read Memory Array until a new write cycle is initiated.
Addr. 55h
RCFI CFI Query 1+
Read CFI data until a new write cycle is initiated.
Data 98h Addr. 555h 2AAh 555h Read electronic Signature or
AS
(4)
Auto Select 3+
Configuration
CR
Register Write
Data AAh 55h 90h
Addr. 555h 2AAh 5 55h
4
Block Protection or Configuration Register Status until a new cycle is initiated.
Configura­tion Data
Data AAh 55h 60h 03h
Program
Address
Program
Data
Program
Address 1
Program
Data 1
Read Data Polling or Toggle Bit until Program completes.
Program
Address 2
Note 6, 7
Program
Data 2
PG Program 4
EBY
XBY
Double Word Program
Enter Bypass Mode
Exit Bypass Mode
DPG
Addr. 555h 2AAh 555h
Data AAh 55h A0h
Addr. 555h 2AAh 5 55h
5
Data AAh 55h 40h
Addr. 555h 2AAh 555h
3
Data AAh 55h 20h Addr. XX
2
Data 90h 00h
PGBY
Program in Bypass Mode
Double Word
DPGBY
Program in Bypass Mode
BP Block Protect 4
BU Block Unprotect 1
Addr. X
2
Data A0h
Addr. X
Program Address
Program
Data
Program
Address 1
Read Data Polling or Toggle Bit until Program completes.
Program
Address 2
3
Data 40h
Program
Data 1
Program
Data 2
Addr. 555h 2AAh 555h
Data AAh 55h 60h 01h
Addr. 555h 2AAh 555h
Data AAh 55h 60h D0h
Note 6, 7
Block
Address
Block
Address
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M59DR008E, M59DR008F
Table 14B. Instructions
(1,2)
Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.
BL Block Lock 4
Addr. 555h 2AAh 555h
Block
Address
Data AAh 55h 60h 2Fh
BE Block Erase 6+
Addr. 555h 2AAh 555h 555h 2AAh
Address
Data AAh 55h 80h AAh 55h 30h
BKE Bank Erase 6
Addr. 555h 2AAh 555h 555h 2AAh
Address
Data AAh 55h 80h AAh 55h 10h
ES Erase Suspend 1
ER Erase Resume 1
(3)
Addr. Data B0h
Addr.
X
Bank
Address
Read until Toggle stops, then read all the data needed from any Blocks not being erased then Resume Erase.
Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time
Data 30h
Note: 1. Commands not interpreted in this table will default to read array mode.
2. For Coded cycles address input s A 11-A20 are don’t care.
3. X = Don’t Care.
4. The fi rst cycles of the RD or AS inst ructions are followed by read operations. Any number of read cycles can occur after the com­mand cycl e s.
5. During Erase Suspend, Read and Data Program functions are allow ed in blocks not bei ng erased.
6. Pr ogram Address 1 and Program Address 2 mus t be consecut i ve addresse s differing only for addre ss bit A0.
7. High voltage on V
(11.4V to 12.6V) is required for th e proper execution of t he Double Wo rd P rogram instruction .
PP
Block
Bank
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