SGS Thomson Microelectronics M5913 Datasheet
COMBINEDSINGLE CHIP PCM CODEC AND FILTER
SYNCHRONOUSCLOCKS ONLY
AT&TD3/D4 ANDCCITT COMPATIBLE
TWOTIMING MODES:
FIXED DATA RATE MODE 1.536MHz,
1.544MHz,2.048MHz
VARIABLEDATA MODE:64KHz- 4.096MHz
PIN SELECTABLE µ-LAW OR A-LAW OPERATION
NO EXTERNAL COMPONENTS FOR SAMPLE-AND-HOLD AND AUTO ZERO FUNCTIONS
LOW POWER DISSIPATION:
0.5mW POWER DOWN
70mW OPERATING
EXCELLENTPOWERSUPPLY REJECTION
DESCRIPTION
The M5913 is fully integrated PCM (pulse code
modulation)codecs and transmit/receivefilter using CMOS silicon gate technology.
The primary applications for the M5913 are telephone systems :
- Switching - M5913-Digital PBX’s and Central
M5913
DIP 20
ORDERING NUMBER: M5913B1
Office Switching Systems
- Concentration- M5913 SubscriberCarrier and
Concentrators.
The wide dynamic range (78dB) and the minimal
conversion time make it ideal products for other
applicationssuchas:
- Voice Store and Forward
- SecureCommunicationsSystems
- Digital Echo Cancellers
- SatelliteEarth Stations.
BLOCK DIAGRAM
December 1993
This is advanced information on a new productnow in development or undergoing evaluation. Details are subject to change without notice.
1/17
M5913
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
V
BB
GRDD, GRDA In Such Case : 0 ≤ V
V
I/O
V
O DIG
P
tot
T
stg
PIN CONNECTION(Top view)
With Respect GRDD, GRDA = 0V – 0.6 to 7 V
With Respect GRDD, GRDA = 0V -0.6 to – 7 V
≤ + 7V, – 7V ≤ VBB≤ 0V ± 0.3 V
CC
Analog Inputs, Analog Outputs and Digital Inputs VBB – 0.3 ≤ VIN/V
OUT
≤ VCC+
0.3
Digital Outputs GRDD – 0.3 ≤ V
≤ VCC+ 0.3 V
OUT
TotalPower Dissipation 1 W
Storage Temperature Range -65 to 150 °C
V
PIN NAMES
Symbol Parameter Symbol Parameter
V
BB
PWRO+, PWRO- Power Amplifier Outputs VF
GS
R
Power (-5V) GS
X
I-, VFXI+ Analog Inputs
X
Gain Setting Input for receive Channel GRDA Analog Ground
PDN Power Pown Select NC No Connected
CLKSEL Master Clock Select SIG
X
LOOP Analog Loop Back ASEL µ or A-law Select
SIG
R
DCLK
R
D
R
FS
R
GRDD Digital Ground CLK
V
CC
SignalingBit Output TS
Receive Data Rate Clock DCLK
Receive Channel Input D
X
X
X
Receive Frame Synchronization Clock FSX Transmit Frame Synchronization Clock
X Transmit Master Clock
Power (+5V) CLK
R
2/17
Gain Control
Transmit Digital Signaling Input
Digital Output - Timeslot Strobe
Transmit Data Rate Clock
Transmit (Digital) Output
Receive Master Clock
PIN DESCRIPTION
Symbol Function
V
BB
PWRO+ Non-inverting Output of Power Amplifier. Can drive transformer hybrids or high impedance loads
PWRO - Inverting Output of Power Amplifier. Functionally identical and complementary to PWRO+.
GS
R
PDN Power Down Select. When PDN is TTL high, the device is active.When low, the device is powered
CLKSEL input which must be pinstrapped to reflect the master clock frequency at CLK
LOOP Analog Loopback. When this pin is TTL high, the receive output (PWRO+)is internally connected
SIG
R
DCLK
R
D
R
FS
R
GRDD Digital Ground for all Internal Logic Circuits. Not internally tied to GRDA.
CLK
R
CLK
X
FS
X
D
X
TS
/DCLK
X
SIG
/ASEL A dual purpose selects µ-law and pin. When connected to VBB. A law operation is selected. When it
X
NC Not Connected.
GRDA Analog ground return for all internal voice circuits.Not internally connected to GRDD.
I+ Non inverting analog input to uncommitted transmit operational amplifier.
VF
X
I- Invertinganalog input to uncommitted transmit operational amplifier.
VF
X
GS
X
V
CC
Most Negative Supply. Input voltage is -5 volts ±5%.
directly in either a differentialor single ended configuration.
Input to the gain Setting Network on the Output Power Amplifier, Transmission level can be
adjusted over a 12dB range depending on the voltage at GS
.
R
down.
, CLKR.
CLKSEL = V
BB
2.048MHz
X
CLKSEL = GRDD 1.544MHz
CLKSEL = V
to VF
CC
I+, GSRis internally connected to PWRO-, and VFXI- is internally connected to GSX.
X
A 0dBm0 digital signal input at D
1.536MHz
is returned as a +3dBm0 digital signal output at DX.
R
Signalling Bit Output, Receive Channel. In fixed data rate mode. SIGRoutputs the logical state of
the eighth bit of the PCM wordin the most recent signaling frame.
Selects the fixed or variable data rate mode. When DCLKR is connected to VBB, the fixed data rate
mode is selected.
When DCLK
mode DCLK
is not connected to VBB, the device operates in the variable data rate mode. In this
R
becomes the receive data clock wich operates at TTL levels from 64kB to 4.096MB
R
data rates
Receive PCM Input. PCM data is clocked in on this lead on eight consecutive negative transitions
of the receive data clock: CLKR inthe fixed data rate mode and DCLK
in variable data rate mode.
R
8kHz frame synchronization clock input/timeslot enable, receive channel. A multifunction input
which in fixed data rate mode distinguishes between signaling and non-signaling frames by means
of a double or single wide pulse respectively. In variable data rate mode this signal must remain
high for the entire length of the timeslot. The receive channel enters the standby state whenever
FSR is TTL low for 30 miliseconds
Receive master and data clock for the fixed data rate mode; receive master clock only in variable
data rate mode.
Transmit master anddata clock for the fixed data rate mode; transmit master clock only in variable
data rate mode.
8kHz frame synchronization clock input/timeslot enable, transmit channel. Operates independently
but in an analogous manner to FSR. The transmit channel enters the standby state whenever FS
is TTL low for 30 milliseconds.
Transmit PCM Output. PCM data is clocked out on this lead on eightconsecutive positive
transitionsof the transmit data clock : CLK in fixed datarate modeand DCLK
invariable datarate
X
mode.
Transmit channel timeslot strobe (output) or data clock (input) for the transmit channel. In fixed
X
data rate mode, this pin becomes the transmit data clock which operates at TTL levels from 64kB
to 4.096MB datarates.
is not connected to V
the eighth bit of the PCM wordduring signaling frames on the D
pin is a TTL level input for signaling operation. This input is transmitted as
BB
X
lead.
Output terminal of on-chip uncommitted op amp. Internally, this is the voice signal input to the
transmit filter.
Most positive supply ; input voltage is + 5 volts ±5%
M5913
X
3/17
M5913
FUNCTIONAL DESCRIPTION
The M5913 provides the analog-to-digitaland the
digital-to-analogconversion and the transmit and
receive filtering necessary to interface a full duplex (4 wires) voice telephone circuit with the
PCM highway of a time division multiplexed
(TDM) system. It is intended to be used at the
analogterminationof a PCM line.
The following major functions are provided :
Bandpass filtering of the analog signals prior to
encodingand afterdecoding
Encoding and decoding of voice and call progressinformation
Encoding and decoding of the signaling and
supervisioninformation
GENERALOPERATION
SystemReliability Features
The combo-chip can be powered up by pulsing
FS
and/or FSRwhile a TTL high voltage is ap-
X
plied to PDN, provided that all clocks and supplies are connected. The M5913 has internal resets on power up (or when V
or VCCare
BB
re-applied)in order to ensure validity of the digital
outputs and thereby maintain integrity of the PCM
highway.
On the transmit channel, digital outputs D
are held in a high impedance state for ap-
TS
X
proximatelyfour frames(500µs) after power up or
application of V
TS
will be functional and will occur in the proper
X
timeslot. The analog circuits on the transmit side
or VCC. After this delay, DXand
BB
X
and
require approximately 40 milliseconds to reach
their equilibrium value due to the autozero circuit
setting time. Thus, valid digital information, such
as for on/off hook detection, is available almost
immediately,while analog information is available
aftersome delay.
On the receive channel, the digital output SIG
R
also held low for a maximum of four frames after
power up or application of V
or VCC, SIGRwill
BB
remain low thereafter until it is updated by a signalingframe.
To furtherenhance systemreliability, TS
will be placed in a high impedance state approximately 20µs after an interruption of CLK
and D
X
. Simi-
X
Table 1: PowerDown Methods
larly SIG
ter an interruption of CLK
will be held low approximately 20µs af-
R
These interruptions
R.
could possibly occur with some kind of fault condition.
PowerDown And Standby Modes
To minimizepower consumption,two power down
modes are provided in which most M5913 functions are disabled. Only the power down, clock,
and frame sync buffers, which are required to
powerup the device, are enabled in thesemodes.
Asshown in table 1, the digital outputs on the appropriate channels are placed in a high impedance state until the device returns to the active
mode.
The Power Down mode utilizes an external control signal to the PDN pin. In this mode, power
consumptionis reduced to an average of 0.5mW.
The device is active when the signal is high and
inactive when it is low. In the absence of any signal, the PDN pin floats to TTL high allowing the
deviceto remain active continuously.
The Standby mode leaves the user an option of
powering either channel down separately or powering the entire down by selectivelyremoving FS
and/or FSR. With both channels in the standby
state, power consumptionis reduced to an average of 1mW. If transmit only operation is desired,
should be applied to the device while FSRis
FS
X
held low. Similarly, if receiveonly operation is desired, FS
should be applied while FSXis held
R
low.
Fixed Data Rate Mode
Fixed data rate timing, is selected by connecting
DCLK
CLK
FS
CLK
is
to operate the codec and filter sections and bit
to VBB. It employs master clock CLKX,and
R
, frame synchronization clocks FSXand
R
, and outputTSX.
R
, and CLKR, serve both as the master clock
X
clocks to clock the data in and out from the PCM
highway. FS
andFSRare 8kHz inputs which set
X
the sampling frequency and distinguish between
signaling and non-signaling frames by thir pulse
X
width.A frame synchronizationpulse which is one
master clock wide designates a non-signaling
frame, while a double wide sync pulse enables
X
Device Status Power Down Methods Digital Outputs Status
Power Down Mode PDN = TTL low TS
Stand-by Mode FS
Only transmit is on stand-by FS
Only receive is on stand-by FS
4/17
and FSRare TTL low TSXand DXare placed in a high impedance state and
X
is TTL low TSXand DXare placed in a high impedance state
X
is TTL low SIGRis placed in a TTL low state within 30ms.
R
and DXare placed in a high impedance state and
X
SIG
isplaced in a TTL low state within 10µs.
R
SIG
is placed in a TTL low state 30ms after FSXand
R
FS
are removed.
R
within 30ms.
M5913
the signaling function. TSXis a timeslot
strobe/bufferenable output which gates the PCM
word onto the PCM highway when an external
buffer is used to drive the line.
Data is transmitted on the highway at D
first eight positive transitions of CLK
the rising edge of FS
. Similarly, on the receive
X
on the
X
following
X
side, data is received on the first eight falling
edgesof CLK
. Thefrequencyof CLKXand CLK
R
is selected by the CLKSEL pin to be either 1.536,
1.544 or 2.048MHz. No other frequency of operationis allowed in the fixed data rate mode.
VariableData Rate Mode
Variable data rate timing is selected by connecting DCLK
highway rather than to V
clocks CLK
DCLK
to the bit clock for the receive PCM
R
and CLKR, bit clocks DCLKRand
X
and frame synchronization clocks FS
X
. It employes master
BB
and FSX.
Variable data rate timing allows for a flexible data
frequency. It provides the ability to vary the frequency of the bit clocks, from 64kHz to 4096MHz.
Master clocks inputs are still restricted to 1.536,
1.544, or 2.048MHz.
In this mode, DCLK
and DCLKXbecome the
R
data clocks for the receive and transmit PCM
highways. While FS
is high, PCM data from D
X
is transmitted onto the highway on the next eight
consecutive positive transitions of DCLK
larly, while FS
highway is received by D
is high, each PCM bit from the
R
on the next eight con-
R
secutivenegativetransitions of DCLK
. Simi-
X
.
R
On the transmit side, the PCM word will be repeated in all remaining timeslots in the 125µs
frame as long as DCLK
is pulsed and FSXis
X
held high. This featureallows the PCM word to be
transmitted to the PCM highway more than once
per frame, if desired, and is only available in the
variable data rate mode. Conversely, signaling is
only allowed in the fixed data rate mode since the
variable mode provides no means with which to
specifya signaling frame.
PrecisionVoltageReferences
No external components are required with the
combochip to provide the voltage reference function. Voltage references are generated on-chip
and are calibrated during the manufacturing process. The technique use the bandgap principle to
derive a temperature and bias stable reference
voltage.These references determinethe gain and
dynamicrange characteristicsof the device.
Separate references are supplied to the transmit
and receive sections. Transmit and receive section are trimmed independentlyin the filter stages
to a final precision value. With this method the
combochip can achieve manufacturingtolerances
of typically ± 0.04dB in absolutegain for each half
channel, providing the user a significant margin
for error in other board components.
ConversionLaws
The M5913 is designed to operate in both µ-law
and A-law systems. The user can select either
conversion law according to the voltage present
on the SIG
R
and decoder process a companded 8-bit PCM
/ASEL pin . In each case the coder
X
word following CCITT recommandation G.711 for
µ-law and A-law conversion. If A-law operation is
desired, SIG
should be tied to VBB. Thus, signal-
X
ing is not allowed during A-law operation. If µ =
255-lawoperation is selected,then SIG
level input which modifies the LSB on the PCM
output in signaling frames
TRANSMIT OPERATION
R
Transmit Filter
The input section provides gain adjustment in the
passband by means of an on-chip uncommitted
operational amplifier. This operational amplifier
has a commonmode range of 2.17V,a maximum
DC offset of 25mV, a minimum voltage gain of
5000, and a unity gain bandwidth of typically
1MHz. Gain of up to 20dB can be set without degrading the performance of the filter. The load im-
X
pedanceto ground (GRDA)at the amplifier output
) must be greater than 10kΩ in parallel high
(GS
X
less than 50pF. The input signal on lead VF
can be either AC or DC coupled. The input op
amp can also be used in the inverting mode or
differentialamplifiermode (see figure 3).
A low pass anti-aliasing section is included onchip. This section typically provides 35dB attenuation at the sampling frequency. No external components are required to provide the necessary
anti-aliasing function for the switched capacitor
sectionof the transmit filter.
Thepassband section provides flatness and stopband attenuation which fulfills the AT&T D3/D4
channel bank transmission specification and
CCITTrecommendation G.712.
The M5913 specifications meet or exceed digital
class 5 central office switching systems requirements. The transmit filter transfer characteristics
and specifications will be within the limits shown
the relative table.
A high pass section configuration was chosen to
reject low frequency noise from 50 and 60Hz
power lines, 17Hz European electric railroads,
ringing frequencies and their harmonics, and
otherlow frequencynoise.
Even though there is high rejection at these frequencies, the sharpness of the band edge gives
low attenuation at 200Hz. This feature allows the
use of low-cost transformer hybrids without external components.
is a TTL
X
I+
X
5/17
M5913
Figure3: Transmit Filter Gain Adjustment.
Encoding
The encoder internally samples the output of the
transmit filter and holds each sample on an internal sample and hold capacitor.
The encoder then performs an analog to digital
conversion on a switched capacitor array. Digital
data representing the sample is transmitted on
the first eight data clockbits of thenext frame.
An on-chip autozero circuit corrects for DC-offset
on the input signal to the encoder. This autozero
circuit uses the sign bit averaging technique. In
this way, all DC offset is removed from the encoderinput waveform.
RECEIVEOPERATION
Decoding
The PCM word at the D
lead is serially fetched
R
on the first eight data clockbits of the frame.
A D/A conversion is performed on the digital word
and the corresponding analog sample is held on
Figure4: Gain Setting Configuration.
an internal sample and hold capacitor. This sample is then transferredto the receive filter.
ReceiveFilter
The receive section of the filter provides passband flatness and stopband rejection which fulfills
both the AT&T D3/D4 specification and CCITT
recommendationG.712. The filter contains the required compensation for the (sin X)/X response of
such decoders. The receive filter characteristics
and specificationsare shown in the relative table.
ReceiveOutput PowerAmplifiers
A balancedoutput amplifier is provided in order to
allow maximum flexibility in output configuration.
Either of the two outputs can be used single
ended (referenced to GRDA) to drive single
ended loads. Alternatively, the differential output
will drive a bridged load directly. The output stage
is capable of driving loads as low as 300 ohms
singleended to a levelof 12dBmor 600 ohms differentiallyto a levelof 15dBm.
The receive channel transmission level may be
adjusted between specified limits by manipulation
of the GS
an analog gain setting network. When GS
input. GSRis internally connected to
R
is
R
strapped to PWRO–, the receive level is minimized;when it is tied to PWRO+, the level is minimized. The output transmission level interpolates
between 0 and -12dB as GSR is interpolated
(with potentiometer) between PWRO- and
PWRO+. The use of the output gain set is illustratedin figure 4.
Transmission levels are specified relative to the
receive channel output under digital milliwatt conditions, that is, when the digital input at D
R
is the
eight-code sequence specified in CCITT recommendationG.711.
6/17
Loading...