SGS Thomson Microelectronics M58MR064D, M58MR064C Datasheet

64 Mbit (4Mb x16, Mux I/O, Dual Bank, Burst)

■ SUPPLY VOLTAGE

–V

Erase and Read

–V

■ MULTIPLEXED ADDRESS/DATA

■ SYNCHRONOUS / ASYNCHRONOUS READ

= 12V for fast Program (optional)

– B urs t mode Read: 54MHz – P age mode Read (4 Words Page) – Random Access: 100ns

■ PROGRAMMING TIME

– 10µs by W ord typical – Two or four words program ming option

■ MEMORY BLOCKS

– Dual Bank Memo ry Array: 16/48 Mbit – Parameter Blocks (T op or Bottom location)

■ DUAL OPERATIONS

– Read within one Bank while Program or

Erase within the other

– No delay between Read andWrite operations

■ PROTECTION/SECURITY

– A ll Blocks protected at Power-up – Any combination of Blocks can be protected – 64 bit unique device identifier – 64 bit user programmable OTP cells – One parameter block permanently l oc ka ble

■ COMMON FLASH INTERFACE (CFI)

■ 100,000 PROGRAM/ER ASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Top Device Code, M58MR064C: 88DCh – B ottom Device Code, M58MR064D: 88DDh

= 1.65V to 2.0V for Program,

DDQ

M58MR064C M58MR064D

1.8V Supply Flash Memory

FBGA

TFBGA48 (ZC)

10 x 4 ball array

Figure 1. Logic Diagram

DDQVPP

A16-A21

M58MR064C M58MR064D

ADQ0-ADQ15

WAIT

BINV

AI90087

1/52March 2002

M58MR064C, M58MR064D

Figure 2. TFBGA Connections (Top view th rough package)

87654321

DDQ

ADQ15

A21

ADQ14

KWAIT

ADQ13 ADQ12

WPRPBINVLA20A16V

ADQ2ADQ3ADQ6ADQ7V

ADQ10ADQ11ADQ4ADQ5V

109

A19

A18

DDQ

A17

ADQ8

ADQ1

ADQ9

1211

ADQ0

1413

AI90088

DESCRIPTION

The M58MR064 is a 64 Mbit non-v olatile Flash memory that may be erased electrically a t block level and programmed in-system on a Word-byWord basis using a 1.65V to 2.0V V

supply for

the circuitry. For Program and Erase operations the necessary high voltages are generated internally. The device suppo rts synchronous burst read and asynchronous read from all the blocks of the memory array; at power-up the device is configured for page mode read. In synchronous burst mode, a new data is output at e ach clock cycle for frequencies up to 54MHz.

The a rray matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power-up.

Blocks can be unprotected to make changes i n the application and then re-protected.

A parameter block "Secu rity bl ock" can be permanently protected against programming and erasing

2/52

in order to increase the data security. An optional 12V V

power supply is provided to speed up the

program phase at costumer production. An internal command interface (C.I.) decodes the instructions t o access/modify the memory content. The program/erase controller (P/E.C.) automatically executes the algorithms taking care of the tim ings necessary for program and erase operations. Two status registers indicate the state of each bank.

Instructions for Read Array , Read Elec tronic Signature, Read Status Register, Clear Status Register, Write Read Configuration Register, Program, Block Erase, Bank Erase, Program Suspend, Program Resume, Erase Suspend, Erase Resume, Block Protect, Bloc k Unprotect, Block Locking, Protection P r ogram, CFI Query, are written to the memory through a Com mand Interface ( C.I.) using standard micro-processor write timings.

The memory is offered in TFBGA48, 0.5 mm ba ll pitch packages and it is supplied with all t he bits erased (set to ’1’).

M58MR064C, M58MR064D

Table 1. Signal Names

A16-A21 Address Inputs

ADQ0-ADQ15

E G W RP

Data Input/Outputs or Address Inputs, Command Inputs

Chip Enable Output Enable Write Enable Reset/Power-down

Organization

The M58M R064 is organized as 4Mb by 16 bits. The first sixteen address lines are multiplexed with the Data Input/Output signals on the mul tiplexed address/data bus A D Q0-ADQ15. The remaining address lines A16-A21 are the MSB addresses.

Chip Enable E

inputs provide memory control.

, Outp ut Enable G and WriteEnable

The clock K input synchronizes the mem ory to the microprocessor during burst read.

Reset RP

is used to reset all t he memory circuitry and to set the chip inpower-down mode if a proper setting of the Read Configuration Register en-

WP K Burst Clock L

Write Protect

Latch Enable

ables this function.

output indicates to the microprocessor the

WAIT status of the memory during the burst mode operations.

Memory Blocks

WAIT BINV Bus Invert V

DDQ

Wait Data in Burst Mode

Supply Voltage Supply Voltage for Input/Output

Buffers Optional Supply Voltage for

Fast Program & Erase

The d ev ice features asymmetrically blocked architecture. M58MR064 has an array of 135 blocks and is di vided into two banks A and B, prov iding Dual Bank operations. Whil e programming or erasing in Bank A, read operations are possible into Bank B or vice versa. Only one bank at the time is allowed to be in progra m or erase mode. It is possible to perform burst reads that cross bank boundaries.

The memory features an erase suspend allowing reading or programming in another block. Once

DU Don’t Use as Internally Connected NC Not Connected Internally

Ground

suspended the erase can be resumed. Program can be suspended to read data in another block and then res umed. The B ank Size and sectorizationaresummarizedinTable3.ParameterBlocks are located at the top of the memory address space for the M58MR064C, and at the bottom for the M58MR064D. The memory maps are shown in Figure 3.

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

Ambient Operating Temperature

(1)

(2)

–40 to 85 °C

BIAS

STG

(3)

DD,VDDQ

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditionsforextended periods mayaffectdevice reliability.Referalso to theSTMicroelectronicsSURE Program andotherrelevantquality documents.

2. Depends on range.

3. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

Temperature Under Bias –40 to 125 °C Storage Temperature –55 to 155 °C

Input or Output Voltage Supply Voltage –0.5 to 2.7 V

Program Voltage –0.5 to 13 V

–0.5 to V

DDQ

+0.5

3/52

M58MR064C, M58MR064D

The architecture includes a 128 bits Protection register t hat is di vided into two 64-bits segments. In the f irst one is written a unique device number, while the second one is programmable by the user. The user programmable segment can be permanently protec ted programming the bit 1 of the Protection Lock Register (see protection register and Security Block). The parameter block (# 0) is a security block. It can be permanently protected

Table3.BankSizeandSectorization

Bank Size Parameter Blocks Main Blocks

Bank A 16 Mbit 8 blocks of 4 KWord 31 blocks of 32 KWord Bank B 48 Mbit - 96 blocks of 32 KWord

Figure 3. Memory Map

Top Boot Block

Address lines A21-A0

000000h

007FFFh

Bank B

512 Kbit or

32 KWord

Total of 96 Main Blocks

by the user programmingthe bit2 of the Protection Lock Register.

Block protection against Program or Erase provides additional data security. All blocks are protected and unlocked at Power-up. Instructions are provided to protect o r un-protect any block in t he application. A second register locks the protection status while WP

islow (see BlockLocking descrip-

tion).

Bottom Boot Block

Address lines A21-A0

000000h

000FFFh

64 Kbit or

4 KWord

Total of 8 Parameter Blocks

Bank A

2F8000h

2FFFFFh

300000h

307FFFh

3F0000h

3F7FFFh

3F8000h

3F8FFFh

3FF000h

3FFFFFh

512 Kbit or

32 KWord

512 Kbit or

32 KWord

512 Kbit or

32 KWord

64 Kbit or

4 KWord

64 Kbit or

4 KWord

Total of 31 Main Blocks

Total of 8 Parameter Blocks

Bank A

Bank B

007000h

007FFFh

008000h

00FFFFh

0F8000h

0FFFFFh

100000h

107FFFh

3F8000h

3FFFFFh

64 Kbit or

4 KWord

512 Kbit or

32 KWord

Total of 31 Main Blocks

512 Kbit or

32 KWord

512 Kbit or

32 KWord

Total of 96 Main Blocks

512 Kbit or

32 KWord

AI90089

4/52

M58MR064C, M58MR064D

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs or Data I nput/Output (ADQ0ADQ15). When Chip Enable E

put Enable G

is at VIHthe multiplexed address/

is at VILand Out-

data bus is used to input addresses for the memory array, data to be program med in the memory array or commands to be written to the C.I. T he address inputs for the memory array are latched on the rising edge of Latch Enable L latch is trans parent when L

is at VIL. In synchro-

. The address

nous operat ions the address is also latched on the first rising/falling edge of K (depe nding on clock configuration) when L

is low. Bot h input dat a and commands are latched on the rising edge of Write Enable W able G

. When Chip Enable E and Output En-

are at VILthe address/data b us outputs data from the Memory Array, the Electronic Signature Manufacturer or Dev ice codes , the Block Protection status the Read Configuration Register status, the protection register or the Status Register. The address/data bus is high impedance when the chip is des elected, Output Enable G or RP

is at VIL.

is at VIH,

Address Inputs (A16-A21). ThefiveMSBaddresses of the memory array are latched on the rising edge of Latch Enable L

. In synchronous operation these inputs are also latched on the first rising/falling edge of K (depending on clock configuration) when L

Chip Enable (E

is low.

). The C hip Enable input a ctivates the memory control logic, input buffers, decoders and sense amplifiers. E

at VIHdeselects the m emory and reduces t he power consumption to the standby level. E

canalsobeusedtocontrol writing to the command register and to the memory array, while W

Output Enable (G

remains at VIL.

). The Output Enable gates the outputs through the data buf fers during a read operation. When G

is at VIHthe outputs are High im-

pedance.

WriteEnable(W

). This input controls writing to

theCommand Register and Dat a latches. Data are latched on the rising edge of W

Write Protect (WP

). This input gives an addition-

al hardware protection level against program or erase when pulled at V

, as described in the Block

Lock instruction des cripti on.

Reset/Power-down Input (RP

). The RP input

provides hardware reset of the memory, and/or Power-down functions, depending on the Read Configuration Regi ster status. Reset/Power-down of the memory is achieved by pul ling RP

to VILfor

at least t

. When the reset pulse is given, the

PLPH

memory wi ll recover from Power-down (when enabled) in a minimum of t

PHEL,tPHLL

or t

PHWL

(see Table 31 and Figure 15) after the rising edge of RP

. Exit from Reset/Power-down changes the contents of the Read Configuration Register bits 14 and 15, setting the memory in async hronous page mode read and power save function disabled. All b locks are protected and unlocked after a Reset/Power-down.

Latch Enable (L

). L latches the address bits

ADQ0-ADQ15 and A16-A2 1 on its rising edge. The address latch is transparent when L

is at V

and it is inhibited w hen L is at VIH. Clock (K). The c lock input synchronizes the

memory to the micro controller during burst mode read operation; the address is latched on a K edge (risingor falling, according to the configurat ion settings) when L

is at VIL. K is don't care during asyn-

chronous page mode read and in write operations.

Wait (WAIT

). WAIT is an output signal used dur-

ing burst mode read, indicating whether the data on the output bus are valid or a wait state must be inserted. This output is high impedance when E G

arehighorRPis at VIL, and can be configured

to be active during the wait cycle or one c lock cycle in advance.

Bus Invert (BINV). BINV is an input/output signal used to reduce the amount of power needed to switch the ex ternal address/data bus. The power saving is achieved by inverting the data output on ADQ0-ADQ15 every time this gives an advantage in terms of number of toggling bits. In burst mode read, each new data output from the memory is compared with the previou s data. If the number of transitions required on the data bus is in excess of 8, the data is inverted and the BINV signal will be driven by the memory at V

to inform the receiv-

ing system that data mus t be inverted before any further process ing. By doing so, the actual tr ans itions on the data bus will be less than 8.

In a similar way, when a command is given, BINV may be driven by the system at V

to inform the

memory that the data input must b e inverted. Like the other input/output pins, BINV is high im-

pedance when the chip is deselected, output enable G

is at VIHor RP is at VIL;whenusedasan input, BINV must follow t he same set-up and hold timings of the data inputs.

and V

is the main power supply for all operations

(Read, P rogram and Erase). V

Supply Voltage (1.65V to 2.0V).

DDQ

is the supply

DDQ

voltage for Input and Output.

5/52

M58MR064C, M58MR064D

VPPProgram Supply Voltage (12V). VPPis both

a cont rol input and a power supply pin. The two functions are selected by the voltage range applied to the pin; if V (0 to 2V) V

is kept ina low voltage ra nge

is seen as a control input, and the current absorption is lim ited to 5µA (0.2µA typical). In this case with V

PP=VIL

protection against program or erase; with V V

these functions are enab led (see Table 26).

PP1

value is only sampled during p rogram or

we obtain an absolute

erase write cycle s; a change in its value after the

operation has been started does not have any effect and program or erase are carried on regularly. If V

is used in the 11.4V to 12.6V range (V

then the pin acts as a power supply (see Table

26). This supply voltage must remain stable as long as program or erase are running. In read mode the current sunk is less then 0.5mA, while during program and erase operations the current

may increase up to 10mA.

Ground. VSSis the reference for all the volt-

age measurements.

PPH

)

6/52

M58MR064C, M58MR064D

DEVICE OPERATIONS

The f ollowing operations can be performed using the appropriate bus cycles: Address Latch, Read Array (Random, and Page Modes), Write command, Output Disable, Standby, res et/Powerdown and Block Locking. See Table 4.

Address Latch. In asynchronous operation, the address is latched on the rising edge of L

input. In burst mode the address is la tched either onthe rising edge of L

or on the first rising/falling edge of K (depending on configuration settings) when L low.

Read. Read operations are used to output the contents of the Memory A rray , the Electronic Sig-

Table 4. User Bus Operations

(1)

nature, the Status Register, the CFI, the Block Protection Status, the Read Configurat ion Register status and the Protection Register.

Read operation of the Memory Array may be performed in asynchronou s page mode or synchronous burst mode. In asynchronous page mode data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by ADQ0 and ADQ1 ad dres s inputs.

According to the device configuration the f ollowing

Read operat ions: Electronic Signature - Status Register - CFI - Block Protection Status - Read Configuration Register Status - Protection Register must be accessed as asynchronous read or as single synchronous read (see Figure 4).

Operation E G W L RP WP ADQ15-ADQ0

Address Latch

Write Output Disable Standby

XX X Reset / Power-down X X X X Block Locking

Note: 1. X = Don't care.

XX X

(rising edge)

X X

Address Input

Data Input

Hi-Z Hi-Z Hi-Z

(3)

(1)

ADQ0

Table 5. Read Electronic Signature (AS and Read CFI instructions)

Code Device E

Manufacturer Code

M58MR064C

G W

ADQ1

Device Code

M58MR064D

Note: 1. Addresses are latched on the rising edge of L input.

2. EA means Electronic Signature Address (see Read Electronic Signature)

3. Value during address latch.

Table 6. Read Block Protection (AS and Read CFI instructions)

Block Status E

Protected and unlocked Unprotected and unlocked Protected and locked

Unprotected and locked

Note: 1. Addresses are latched on the rising edge of L input.

2. AlockedblockcanbeunprotectedonlywithWP

3. Value during address latch.

4. BA means Block Address. First cycle command address should indicate the bank of the block address.

(2)

G W

at V

IH.

ADQ1

V V V V

(1)

(3)

ADQ0

(3)

Other

Address

(2)

Other

Address

(4)

(2)

ADQ15-0

0020h 88DCh 88DDh

ADQ15-0

0001 0000 0003 0002

7/52

M58MR064C, M58MR064D

Table 7. Read Protection Register (RSIG and RCFI Instruction)

(1)

Word E G W A21-17 ADQ15-8 ADQ7-0 ADQ15-8 ADQ7-3 ADQ2 ADQ1 ADQ0

Lock

Unique ID 0

Unique ID 1

Unique ID 2

Unique ID 3

OTP 0

OTP 1

OTP 2

OTP 3

Note: 1. Addresses are latched on the rising edge of L input.

ILVILVIH X

ILVILVIH

2. X = Don't care.

(2)

80h 00h 00000B

Security

prot.data

81h ID data ID data ID data ID data ID data

82h ID data ID data ID data ID data ID data

83h ID data ID data ID data ID data ID data

84h ID data ID data ID data ID data ID data

85h OTP data

86h OTP data

87h OTP data

88h OTP data

OTP data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

prot.data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

Table 8. Dual Bank Operations

(1,2,3)

Commands allowed in the other bank

Status of one

bank

Read Array

Read

Status

Read

ID/CFI

Program

Erase/

Erase

Resume

Program Suspend

Erase

Suspend

Protect

Unprotect

Idle Yes Yes Yes Yes Yes Yes Yes Yes Reading –––––––– Programming Yes Yes Yes ––––Yes Erasing Yes Yes Yes ––––Yes Program

Suspended Erase

Suspended

Note: 1. For detailed description of command see Table 33 and 34.

2. There is a status register for each bank; status register indicates bank state, not P/E.C. status.

3. Command must be written to an address within the block targeted by that command.

YesYesYes––––Yes

Yes Yes Yes Yes – Yes – Yes

8/52

M58MR064C, M58MR064D

Figure 4. Single Synchronous Read Sequence (RSIG, RCFI, RSR instructions)

A21-A16

ADQ15-ADQ0

VALID ADDRESS

CONF. CODE 2

VALID ADDRESS VALID DATA NOT VALID

CONFIGURATION CODE 3

VALID ADDRESS VALID DATA

CONFIGURATION CODE 4

VALID ADDRESS NOT VALID

Both Chip E nable E and Output Enable G must be at V

in order to read the output of t he memory.

Read array is the default state o f the device when exiting power down or after power up.

Burst Read. The device also supports a burst read. In this mode a burst sequence is started at the first clock edge (rising or falling according to configuration settings) after the falling edge of L After a configurable delay of 2 to 5 clock cycles a new data is output at each clock cycle. The burst sequence may be configured for linear or interleaved order and for a length of 4, 8 words or for continuous burst mode. Wrap and no-wrap modes are also supported.

AWAIT

signal may be ass erted to indicate to the system that an output delay wil l occur. This delay will depend on the starting address of the burst sequence; t he worst case delay will occur w hen the sequence is crossing a 64 word boundary and the starting address w as at the end of a four word boundary. See the Write Read Configuration Register (CR) Instruction for more details on all the possible settings for the synchronous burst read (see Table 14). It is possible to perform burst read across bank boundary ( all banks in read array mode).

Write. Wri te operations are used to give I ns truction Commands to the memory or to latch Input Data to be programmed. A w rite operation is initiated when Chip Enable E at V

with Output Enable G at VIH. Addresses are

latched on the rising edge of L put Data are latched on the rising edge of W

and Write Enable W are

. Co mm ands and In-

or E

whichever occ urs first. Noise pulses of less than

5ns typical on E

NOT VALID

VALID DATA

,Wand G signals do not start a

NOT VALID

write cycle. Write ope rations are asynchronous and clock is ignore d during write.

Dual Bank Op erations. The Dual Bank allows to run different operations simultaneously in the two banks. It is possible to read array data from one bank while the other is programming, erasing or reading any data (CFI, status register or electronic

signature). Read and write cycles c an be initiated for simulta-

neous operations in different banks without any delay. Only one bank at a tim e is allowed to be in program or erase mode, while the other must be in one of the rea d modes (see Table 8).

Commands m ust be written to an address within the block targeted by that command.

Output Disable. The data outputs are high impedance when t he Output Enable G

Write Enable W

at VIH.

is at VIHwith

Standby. The memory is in standby when Chip Enable E

is at VIHand the P /E. C. is idle. The power consumption is reduced to t he standby level and the outputs are high impedance, inde pendent of the Output Enable G

or Write Enable W inputs.

Automatic Standby. When in Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus. The automatic standby feature is not available when th e dev ice is configured for synchronous burst mode.

AI90090

9/52

M58MR064C, M58MR064D

Table 9. Identifier Codes

Code Address (h) Data (h)

Manufacturer Code Bank Address + 00 0020

Device Code

Top Bank Address + 01 88DC Bottom Bank Address + 01 88DD Protected and Unlocked

Block Protection

Die Revision Code Bank Address + 03 Read Configuration Register Bank Address + 05 Lock Protection Register Bank Address + 80

Protection Register

Note: 1. DRC means Die Revision Code.

CR means Read Configuration Register. LPR means Lock Protection Register. PR means Unique Device Number and User Programmable OTP.

Reset/Power-down. The memory is in Powerdown when the Read Configuration Register is set for Power-down and RP sumption is reduced to the Power-down level, and Outputs are in high impedanc e, independent ofthe Chip Enable E

inputs. The memory is in reset when the Read

, Output Enable G or Write Enable

Configuration Register is set for Reset and RP at VIL

. The power cons umption is the same of the standby and the outputs a re in high impedance. After a Reset/Power do wn the device defaults to

Unprotected and Unlocked 0000 Protected and Locked 0003 Unprotected and Locked 0002

Bank Address + 02

Bank Address + 81 Bank Address + 88

Block Locking. Any combination of blocks can be temporarily protected against Program or

is at VIL. The p ower con-

Erase by setting the lock register and pulling WP to VIL. The following summarizes the locking operation. All blocks are prot ec ted on power-up. They can then be unprotected or protected with the Unprotect and Protect c ommands. T he Lock com-

mand protects a block and prevents it from being unlocked when WP overridden. Lock is cleared only w hen the device

is reset o r powered-down (see Protect instruction). read array mode, the status register is set to 80h and the read configuration register defaults to asynchronous read.

0001

(1)

DRC

(1)

LPR

(1)

=0.WhenWP= 1, Loc k is

10/52

M58MR064C, M58MR064D

INSTRUCTIONS AND COMMANDS

Eighteen instructions are available (see Tables 10 and 11) t o perform Read Memory Array, Read Status Re giste r, Read Electronic Signature, CFI Query,Block Erase, Bank Erase, Program,Tetra Word Program, Double Word Program, Clear Status Register, Program/Erase Suspend, Pro gram/ Erase Resume, Block Protect, B lock Unprotect, Block Lock , Protection Register Program, Read Configuration Register and Lock Protection Program.

Status R egister output may be read at any time, during programming or erase, to monitor the progress of the operation.

An internal Command Interface (C.I.) decodes the instructions while an internal Program / Erase Controller (P/E.C.) handles all timing and verifies the correct execution of the Program and Erase instructions. P/E.C. provides a Status Regi ster whose bits indicate operation and exit status of the internal algorithms. The Com mand Interface is reset to Read Array when power is first applied, when exiting from Reset or whenever V than V

. Command sequence must be followed

LKO

is lower

exactly. Any invalid combination of commands will reset the device to Read Array.

Read (RD)

The Read instruction consists of one write cycle (refer to Device Operat ions section) and places the addressed bank in Read Array mode. When a device reset occurs, the memory is in Read Array as default. A read array command will be ig nored while a bank is programming or erasing. However inthe other bank a read array command wi ll be accepted.

Read Status Register (RS R)

A bank's Status Register indicates when a program or erase operation is complete and th e success or failure of operation itself. Issue a Read Status Register Instruction (70h) to read t he Status Register content of the addressed bank. The status of the other bank is not affect ed by the command. The Read Status Regist er instruction may be issued at any t ime, also when a Program/Erase operation is ongoing. The following Read operations output the content of the Status Register of the addressed bank. The S tatus Register is latched on the falling edge of E canbereaduntilE G

must be toggled to update the latched data.

or G returns to VIH. Either E or

or G signals, and

Read Electronic Signatu re (RSIG)

The Read Electronic Signature instruction consists of one write c y cle (refer to Dev ice Operat ions section) giving the command 90h to an address

Table 10. Commands

Hex Code Command

00h Invalid Reset 01h Protect Confirm

03h

10h Alternative Program Set-up

20h Block Erase Set-up 2Fh Lock Confirm 30h Double Word Program Set-up 40h Program Set-up 50h Clear Status Register 55h Tetra Word Program Set-up

60h

70h Read Status Register 80h Bank Erase Set-up 90h Read Electronic Signature 98h CFI Query B0h Program/Erase Suspend

C0h

D0h

FFh Read Array

Write Read Configuration Register Confirm

Protect Set-up and Write Read Configuration Register

Protection Program and Lock Protection Program

Program/Erase Resume, Erase Confirm or Unprotect Confirm

within the bank A. A subsequent read in the address of bank A will output the Manufacturer Code, theDeviceCode,theprotectionStatusofBlocks of bank A, the Die Revision Code, the Protect ion Register, or the Read Configuration Register (see Table 9).

If the first write cycle of Read E lectronic Signature instruction is issued to an address within the bank B, a subsequent read in an address of bank B wi ll output the prot ec ti on Status of Blocks of bank B. The status of t he other bank is not affected by the command (see Tabl e 8).

See Tables 5, 6, 7 and 8 for the valid address. The Electronic Signat ure can be read from the me mory allowing programming equipment or applications to aut omatically match their interface to the characteristics of M58MR064C and M58MR06 4D.

11/52

M58MR064C, M58MR064D

Table 11. Ins t ructi ons

Instruction Cyc. Operation

Read

Memory Array

1+ Write BKA FFh

Address

(1,2)

Data

(3)

Operation

(1)

Read

Address

(1,2)

Read

Address

Data

(3)

RSR

Read Status Register

1+ Write BKA 70h

Read

RSIG

READ

Electronic

1+ Write EA 90h

Read

(1)

BKA

EA ED

Signature

RCFI Read CFI 1+ Write CA 98h

Clear Status

CLRS

(5)

1 Write BKA 50h

Read

(1)

CA CD

EE Block Erase 2 Write BA 20h Write BA D0h BE Bank Erase 2 Write BKA 80h Write BKA D0h

PG Program 2 Write WA 40h or 10h Write WA WD

DPG

Double Word Program

3 Write WA1 30h Write WA1 WD1

Write WA2 WD2

TPG

Tetra Word Program

5 Write WA1 55h Write WA1 WD1

Write WA2 WD2 Write WA3 WD3

PROGRAM/ERASE

Write WA4 WD4

Program

PES

Erase

1 Write BKA B0h

Suspend Program

PER

Erase

1 Write BKA D0h

Resume

BP Block Protect 2 Write BA 60h Write BA 01h

Block

Unprotect

PROTECT

BL Block Lock 2 Write BA 60h Write BA 2Fh

2 Write BA 60h Write BA D0h

Status

CONFIGURATION

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PRP

LPRP

Protection Register Program

Lock Protection Register Program

Write Read Configuration Register

2 Write PA C0h Write PA PD

2 Write LPA C0h Write LPA LPD

2 Write RCA 60h Write RCA 03h

M58MR064C, M58MR064D

Note: 1. First cycle command address should be the same as the operation's target address. The first cycle of the RD, RSR, RSIG or RCFI

CFI Query (RCFI)

The CFI Query Mode is as sociated to bank A. T he address of t he first write cycle must be within t he bank A. The status ofthe other bank is not affected bythe com mand (see Table 8). Wr iting 98h the device enters the Common Flash Interface Query mode. Next read operations in the bank A will read the CFI data. Write a read instruction to return to Read mode (refer to the C omm on Flash Interface section).

Clear Status Register (CLS R)

The Clear Status Register uses a single write operation,which resets bits b1, b3, b4 e b5 of the status register. The Clear Status Register is executed writing the co mm and 50h independently of the applied V the device returns to read array mode. The Clear Status Register command clears on ly the status register of the address ed bank.

Block Erase (EE)

Block erasure sets all the bits within the selected block to '1'. One block at a time can be erased. It is not necessary t o pre-program the block as the P/E.C. will do it automatically before erasing. This instruction use two w rites cycles. The first command written is the Block Erase Set up command 20h. The sec ond command is the Erase Confirm command D0h. An address within t he block to be erased should be given to the mem ory during the two cycles command. If the second com mand given is not an erase confirm, the status register bits b4 and b5 a re s et and the instruc tion aborts.

instruction is followed by read operations in the bank array or special register. Any number of read cycles can occur after one command cycle.

2. BKA means Address within the bank; BA means BlockAddress; EA means Electronic SignatureAddress; CA means Common Flash Interface Address; WA means Word Address; PA means ProtectionRegister Address (see Table7); LPA means Lock Protection Register Address (see Table 7); RCA means Read Configuration Register Address.

3. PD means Protection Data; CD means Common Flash Interface Data; ED means Electronic Signature Data; WD means Data to be programmed at the address location WA; LPD means Lock protection Register Data

4. WA1, WA2, WA3 and WA4 must be consecutive address differing only for address bits A1-A0.

5. Read cycle after e CLSR instruction will output the memory array.

After w riting the command, the device outputs status register data when any address within the bank is read. Atthe end of the operation the bank will remain in read status register until a read array command is written.

Status Register bit b7 is '0' while the eras ure is in progress and '1' when it has completed. After completion the Status Register bit b5 returns '1' if t here has been an Erase Failure. Status register bit b1 returns'1'iftheuserisattemptingtoeraseaprotected bl ock. Status Register bit b3 ret urns a '1' if

is below V

. A s data integrity cannot be guaranteed when

. Erase aborts if RP turns to

PPLK

the erase operation is aborted, the erase must be repeated (see Table 12). A Clear Status Register

voltage. After executing this command

instruction must be issued to reset b1, b3, b4 and b5 of t he Status Register. During the execution of the erase by the P/E.C., the bank with the block in erase accepts onl y the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. See figure 19 for Erase Flowchart and Pseudo Code.

Bank Erase (BE)

Bank erase sets all the bits within the s elected bank to ’1’. It is not necessary to pre-program t he block as t he P/E.C. wil l do it automat ically before erasing.

This instruction uses two writes cycles. The first command writt en is the Bank Erase set-up command 80h. The second command is the Erase Confirm command D0h. An address within the bank to be erased should b e given to the memory during the two cycles command. See the Block Erase com mand sec tion for status register bit details.

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M58MR064C, M58MR064D

Table 12. Status Register Bits

Mnemonic Bit Name

P/ECS 7 P/ECS

Status

Logic

Level

1 Ready Indicates the P/E.C. status, check during

0 Busy

Definition Note

Program or Erase, and on completion before checking bits b4 or b5 for Program or Erase Success.

ESS 6 Erase

ES 5 Erase Status 1 Erase Error ES bit is set to ’1’ if P/E.C. has applied the

PS 4 Program

VPPS 3 V

PSS 2 Program

BPS 1 Block

0 Reserved

Note: Logic level’1’ is VIHand ’0’ is VIL.

Suspend Status

Status

Suspend Status

Protection Status

1 Suspended

In Progress or

Completed

0 Erase Success 1 Program Error

Program

Success VPPInvalid,

Abort V

0 1 Suspended

In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

On an Erase Suspend instruction P/ECS and ESS bits are set to ’1’. ESS bit remains ’1’ until an Erase Resume instruction is given.

maximum number of erase pulses to the block without achieving an erase verify.

PS bit set to ’1’ if the P/E.C. has failed to program a word.

VPPS bit is set if the VPPvoltage is below

when a Program or Erase instruction is

PPLK

executed. V beginning of the erase/program operation.

On a program Suspend instruction P/ECS and PSS bits are set to ’1’. PSS remains ’1’ until a Program Resume Instruction is given.

BPS bit is set to ’1’ if a Program or Erase operation has been attempted on a protected block.

is sampled only at the

Program (PG)

The Program instruction programs the array on a word-by-word basis. The first command must be given to the target block and only one partition can be programmed at a time; the other partition must be in one of the read modes or in t he eras e suspended mode (s ee Table 8).

This instruction uses two write cycles. The first command written is the Program Set-up c ommand 40h (or 10h). A second write operation latches the Address and the Data to be written a nd starts the P/E.C.

Read operations in the targeted bank output the Status Register content after the programmi ng has started.

The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns'1' if there has been a Program Failure (s ee

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Table 12). Status register bit b1 returns '1' if the user is attempting to pro gram a protected block. Status Register bit b3 ret urns a '1' if V V

. Any attempt to write a ’1’ to an already pro-

PPLK

is below

grammed bit will result in a program fail (status register bit b4 set) if V nored if V

PP=VPP1

Programming aborts if RP

=V goes to VIL.Asdatain-

and will be ig-

PPH

tegrity cannot be guaranteed when the program operation is aborted, the block contain ing the memory location must be eras ed and reprogrammed. A Clear Status Register instruction must be issue d to reset b5, b4, b3 and b1 of the Status Register.

During the execution of the program by the P/E.C., the bank in programming accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. S ee Figure 16 for Program Flowchart and Pseudo Code.

Figure 5. Security Block Memory Map

Parameter Block # 0

88h

85h 84h

81h 80h

M58MR064C, M58MR064D

User Programmable OTP

Unique device number

Protection Register Lock 2 1 0

AI90091

Table 13. Protection States

(2)

Current State

(WP, DQ1, DQ0)

Program/Erase

Allowed

(1)

Next State After Event

(3)

Protect Unprotect Lock WP transition

100 Yes 101 100 111 000 101 No 101 100 111 001

110 Yes 111 110 111 011 111 No 111 110 111 011

000 Yes 001 000 011 100 001 No 001 000 011 101

011No011011011

Note: 1. Allblocksare protectedatpower-up,sothedefaultconfigurationis001 or 101 accordingto WP status.

2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect in and by DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Read Electronic Signature instruction with A1 = V and A0 = VIL.

3. Next state is the protection status of a block after aProtect orUnprotect or Lock command has been issued or after WP its logic value.

4. A WP

transition to VIHon a locked block will restore the previous DQ0 value, giving a 111 or 110.

111 or 110

(4)

has changed

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M58MR064C, M58MR064D

Double W ord Program (DPG)

Thisfeature is offered to improve the programmi ng throughput, writing a page of two adjacent words in parallel. The first command mu st be given to the target block and only one partition can be programmed at a time; the other partition must be in one of t he read modes or in the erase suspended mode (see Table 8).

The two words must differ only for the address A0. Programming should not be attempted when V is not atV if V

is below V

. The operation can also be executed

PPH

but result could be uncertain.

PPH

These instruction uses three write cycles. The first command written is the Double Word Program Set-Up command 30h. A sec ond write operation latches the Address and the Data of the first word to be written, the third w rite operation latche s the Address and the Data of the second word to be written and starts the P/E.C. (see Table 11).

Read operations in the targeted bank output the Status Register content after the programmi ng has sta rted. The Status Register bit b7 returns '0' while t he programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure. Status register bit b1 returns '1' if the user is attempting to program a pro tected block. Status Register bit b3 returns a '1' if V

is below V

PPLK

Any attempt to write a ’1’ t o an already programmed bit will result in a program fail (status register bit b4 set). (See Table 12).

Programming aborts if RP

goes to VIL.Asdataintegrity cannot be guaranteed when the program operation is aborte d, the memory location must be erased and reprogramm ed. A Clear Statu s Register instruction must be iss ued to reset b5, b4, b3 and b1 of the Stat us Register. D uring the execution of the program by the P/E .C., the bank in programming accepts only the RSR (Read Status Register) instruction. See Figure 17 for Doub le Word Program Flowchart and Pseudo c ode.

Tetra Word Program (TPG)

Thisfeature is offered to improve the programmi ng throughput, writing a page of four adjacent words in parallel. The first command mu st be given to the target block and only one partition can be programmed at a time; the other partition must be in one of t he read modes or in the erase suspended mode (see Table 8).

The four words must differ only for the addresses A0 and A1. Programming should not be attempted when V

is not at V

be executed if V

. The operation can also

PPH

is below V

but result could

PPH

be uncertain. These instruction uses five write cycles. The first com mand written is the Tetra Word Program Set-Up command 55h. A second write operation latches the Address and the D ata of the firstwordtobewritten,thethirdwriteoperation

latches the Address and t he Data of the second word to be written, the fourth write operation latches the Address and the Dataof the third word to be written, the fifth write operation latche s the A ddress and the Data of the fourth word to be written and starts the P/E.C. (s ee Table 11).

Read operations in the targeted bank output the Status Register content after the programming has sta rted. The Status Register bit b7 returns '0' while t he programming is in progress and '1' w hen it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure. Status register bit b1 returns '1' if the user is attempting to program a pro tected block. Status Register bit b3 returns a '1' if V

is below V

Any attempt to write a ’1’ t o an already programmed bit will result in a program fail (status register bit b4 set). (See Table 12).

Programming aborts if RP

goes to VIL.Asdataintegrity cannot be guaranteed when the program operation is aborte d, the memory location must be erased and reprogramm ed. A Clear Statu s Register instruction must be iss ued to reset b5, b4, b3 and b1 of the Stat us Register. D uring the execution of the program by the P/E .C., the bank in programming accepts only the RSR (Read Status Register)instruction. See Figure 17 for Tetra Word Program Flowchart and Pseudo code.

Erase Suspend/Resume (PES/PER)

The Erase Suspend freezes, aft er a certain latencyperiod (within 25us), the eras e operation andallows read in another block withinthe t arget ed bank or program in the other block.

This instruction uses one write cycle B0h and the address should be w ithin the bank with the block in erase (see Table 11). The device continues to output status register data after the erase suspend is issued. The status register bit b7 and bit b6 are set to ’1’ then the erase operation has been suspended. Bit b6is set to '0' in case the erase is completed or in progress (see Table 12).

The valid commands while erase is suspended are: Program/Erase Resume, Program, Read Memory Array, Read S t atus Register, Read Electronic Signature, CFI Query, Block Protect, Block Unprotect and Block Lock. The us er can protect the Block being erased issuing the Block Protect or Block Lock c ommands.

During a block erase suspend, t he device goes into standby mode by taking E

toVIH, which reducesactive current draw. Erase is aborted ifRP to V

If an Er as e Suspend instruction w as previously ex ecuted, the erase operation may be resumed by issuing the command D0h using an addres s within thesuspended bank. The status register bitb6 and bit b7 are cleared when erase resu mes and read

PPLK

turns

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