13/63
M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A18). The Address Inputs
are used to select the cells to access in the mem ory array during Bus Read operations either to
read or to program data to. During Bus Write operations they control the commands sent to the
Command Interface of the internal state m achine.
Chip Enable must be low when selecting the addresses.
The address inputs are latched on the rising edge
of Latch Enable L
or Burst Clock K, whichever occurs first, in a read operation.The address inputs
are latched on the rising edge of Chip Enable,
Write Enable or Lat ch Enable, whichever o ccurs
first in a Write operation. The address latch is
transparent when Latch Enable is low, V
IL
. The address is internally latched in a n E rase or P rogram
operation.
Data Inputs/Outputs (DQ0-DQ31). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. During Bus Write operations they represent the commands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
When Chip Enable and Output Enable are both
low, V
IL
, and Output Disable is at V
IH,
the data bus
outputs data from the memory array, the Electronic Signature, the CFI Information or the contents of
the Status Register. The data bus is high impedance when the device is deselected with Chip Enable at V
IH
, Output E na ble at VIH, Outp u t Di sa b le
at V
IL
or Reset/Power-Down at VIL. The Status
Register content is output on DQ0-DQ7 and DQ8DQ31 are at V
IL
.
Chip Enable (E
). The Chip Enable, E, input acti-
vates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E
, at
V
IH
deselects the memory and reduces the power
consumption to the Standby level.
Output Enable (G
). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation, whe n Output Disable GD
is at
V
IH
. When Output Enable G is at VIH, the outputs
are high impedance in dependentl y of Output Disable.
Output Disable (GD
). The Output Disable, GD,
deactivates the data output buffers. W hen Output
Disable, GD
, is at VIH, the outputs are driven by
the Output Enable. When Output Disable, GD
, is at
V
IL
, the outputs are high impedance independent-
ly of Output Enable. The Output Disable pin must
be connected to an external pull-up resistor as
there is no internal pull-up resistor to drive the pin.
Write Enable (W
). The Write Enable, W, input
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Wri te Enable (also see Latch Enable, L
).
Reset/Power-Down (RP
). The Reset/Power-
Down, RP
, is used to apply a hardware reset to the
memory. A hardware reset is achie ved by hold ing
Reset/Power-Down Low, V
IL
, for at least t
PLPH
.
Writing is inhibited to protect data, the Command
Interface and the Program/Erase Controller are reset. The Status Register information is cleared and
power consumption is reduced to deep powerdown level. The device acts as deselected, that is
the data outputs are high impedance.
After Reset/Power-Down goes High, V
IH
, the
memory will be ready for Bus Read operations after a delay of t
PHEL
or Bus Write operat ions after
t
PHWL
.
If Reset/Power-Down goes low, V
IL
, during a Block
Erase, a Program or a Tuning Protection Program
the operation is aborted, in a time of t
PLRH
maxi-
mum, and data is altered and may be corrupted.
During Power-up power should be applied simulta-
neously to V
DD
and V
DDQ(IN)
with RP held at VIL.
When the supplies are stable RP
is taken to VIH.
Output Enable, G
, Chip Enable, E , and Write En-
able, W
, should be held at VIH during power-up.
In an application, it is recommended to associate
Reset/Power-Down pin, RP
, with the reset s ignal
of the microprocessor. Otherwise, if a reset operation occurs while the memory is performing an
erase or program operation, the memory may output the Status Register informa tion instead of being initialized to the default Asynchronous
Random Read.
See Table 21 a nd F igure 18, Reset , Po wer-Down
and Power-up Characteristics, for more details.
Latch Enable (L
). The Bus Interface can be con-
figured to latch the Address Inputs on the rising
edge of Latch Enable, L
, for Asynchronous Latch
Enable Controlled R ead or W rite or Synchronous
Burst Read operations. In Synchronous Burst
Read operations the address is latched on the active edge of the Clock when Latch Ena ble is Low,
V
IL
. Once latched, the addresses may change
without affecting the address used by the memory.
When Latch Enable is Low, V
IL
, the latch is trans-
parent. Latch Enable, L
, can remain at VIL for
Asynchronous Random Read and Write operations.
Burst Clock (K). The Burst Clock, K, is used to
synchronize the memory with the external bus dur-