SGS Thomson Microelectronics M491B Datasheet

M491B

SINGLE-CHIP VOLTAGE SYNTHESIS TUNING SYSTEM

WITH 1 ANALOG CONTROL

.

16-STATION MEMORY - 7-SEGMENT LED
DISPLAY

.

VOLTAGESYNTHESIZER: 13 BITS

.

4-BANDPRESETCAPABILITY

.

NON-VOLATILEMEMORY : 304 BITS

- 16 WORDS OF19 BITS FORTUNINGVOLT­AGE(13 bits)- BAND (2 bits) - FINEDETUN­ING (4 bits)

4

- 10

MODIFYCYCLESPER WORD

- MIN 10 YEARSDATARETENTION

.

PCM REMOTE CONTROL RECEIVER : DE­CODES SIGNAL TRANSMITTEDBY M708

.

VOLUMED/A : 6-BITRESOLUTION/ 8kHz

.

MEMORYSKIP FUNCTION

.

AUTOMATIC SEARCH WITH DIGITAL AFT
CONTROL

.

FINE DETUNING D/A ACTING ON AFT DIS­CRIMINATOR (16 steps) WITH SEPARATE
STORAGE FOR EACH MEMORY POSITION.
ALTERNATIVELYIT CAN BE USED TO CON­TROL BRIGHTNESS OR COLOUR SATURA­TION

.

MANUAL SEARCH WITH DIGITALAFT CON­TROL

.

MANUALSEARCHWITH LINEAR AFT

.

SWEEPSEARCHDISPLAYOUTPUT

.

SUPPLYVOLTAGES : VDD= + 5V,

=+ 25VFOR THE MEMORY

V

PP

.

CLOCKOSCILLATOR: 445TO 510kHz

.

INTEGRATED DIGITAL POWER ON RESET
(no externalinitializationcircuitry required)

DESCRIPTION

The M491B is a monolithic N-MOS LSI circuit in­cluding a Floating-gate Non-Volatile Memory for
storage of up to 16stations. Tuning of the station
is performedwith a 8192 step D/Aconverter,using
the principleof voltagesynthesis.It is designedfor
7-segmentLED displays. Direct memoryselection
is possibleonlyfromremotecontrol whileUp/Down
memory scanningis possible on the set and also
from remote control. An option input for 8 or 16
stations is available. The circuit also includes a
PCM remotecontrol receiveroperating in conjunc-

tionwith the transmitterM708. The highly reliable
transmissioncode ensureserror-free signal detec­tion even in presence of high noise conditions.
Search of the station is possible in automatic or
manual modes. The circuit can operate with a
DigitalorLinearAFTcontrol.TheDigitalAFTmode
isnecessary for automaticsearch and requires an
external circuit (TDA4433 or equivalent,e.g. dual
comparatorplus TVstationdetector)toconvertthe
AFC-S-curveintoan Up/Down command.Finetun­ing(detuning)is alsopossiblewithdifferentmodes
ofoperation.Thecircuitisassembledin 40-pindual
in-lineplastic package.

DIP40

(Plastic Package)

ORDER CODE : M491B1

PIN CONNECTIONS

(GND)

V

SS

MEMORYSUPPLY

MEMORYTIMING
FINE TUNING D/A

TUNINGD/A

DIGITALAFTSTATUS

OSC. IN

OSC. OUT

V

TEST

I.R.INPUT

AFT1
AFT2

SWEEPDISPLAY OUT

VOLUMED/A

LINEARAFT DEF.

DIGITALAFTEN.

1
2
3
4
5
6
7
8
9

DD

10
11
12
13
14
15
16
17
18

V3

19

V2

20

V1 X4

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

VHFI
VHFIII
CATV
UHF
SEGM.h + i
SEGM.g
SEGM.f
SEGM.e
V

(GND)

SS

OPT.8/16
SEGM.d
SEGM.c
SEGM.b
SEGM.a
MAINSON/OFF
MAINSON OPTION
X1
X2
X3

491B-01.EPS

September 1992

1/16

M491B

FUNCTIONAL DIAGRAM

+12V

UP

AFC-Scurve

(AFT1)

(AFT2)

DOWN

PP

V (25V)

OSC

445 to 510MHz

OSC

+5V

V

I V

or 8160

TDA2320

TEST

OUT

IN

SS MT MS

DDR

TUNING D/A

FINE TUNING D/A

VHF I

4

5

7 89 1011

1 23

31

32

SS

V

OPT. 8/16

4.5 to 13.2V

BAND OUT

UHF

CAT V

VHF III

39

40

b

a

f

h

37

38

c

g

d

e

i

AUTO SEARCH STOP

DIGITALAFT

SWEEP DISPLAYOUT

AFT1

14

DIGITAL AFT STATUS

AFT2

6

12

13

M491B

27282930333435

a

b

c

DIGITAL AFT ENABLE

17

d

LINEAR AFTDEFEAT

16

e

VOLUME D/A

MAINSON/OFF

MAINSONOPTION

15

25

26

23

24

X1 X2 X3 X4

181920 2122

V2 V3

V1

36

f

g

h - i

2/16

445 to

M708

510MHz

491B-02.EPS

M491B

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

DD

V

PP

V

V

O (off)

I

OL

t

pd

P

tot

T

stg

T

op

Stresses above thoselisted under”Absolute Maximum Ratings” maycause permanent damage to the device. This is a stress rating only and
functional operation ofthe device at these or any other conditions above those indicated in the operational sections of thisspecification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affectdevice reliability.

DC ELECTRICALCHARACTERISTICS

(T

amb

2-Memory Supply I

3–Write Timing Out
4–Fine Tuning D/A

5–Tuning D/A
6–Digital AFT Out

9–Power Supply I
11–I.R. Input V

12–AFT1
13–AFT2

14—Display Out

15–Volume D/A

16–Linear AFT Out

17–Digital AFT En­able

Supply Voltage – 0.3, + 7 V
Memory Supply Voltage – 0.3, + 26 V
Input Voltage – 0.3, + 15 V

I

Off State Input Voltage (except pin 3)

Pin 3

Output Low Current

Led Driver Outputs
Pins 6 – 14
Pins 4 – 5
All Other Outputs

15
28

mA
20
20

7.5
5

Max. Delay between Memory Timing and Memory Supply Pulses 5 µs
Total Package Power Dissipation 1 W
Storage Teperature – 25, + 125 °C
Operating Temperature 0, + 70 °C

=0 to + 70°C, VDD= +5V unless otherwisespecified)

Pin Symbol Parameter Test Conditions Min. Typ. Max. Unit

Memory Supply Current VPP= 25V

PP

R Pull Down Resistor 25 kΩ

V

I

O (off)

I

O (off)

V
V

I

O (off)

V

V

Output Low Voltage VDD= 4.75 V, IOL= 2.5 mA 8 V

OL

Output Leakage Current VDD= 4.75 V, V

VDD= 5.25 V, V

OL
OL

VDD= 4.75 V, IOL= 5 mA 1 V
VDD= 4.75 V, IOL= 20 mA 1.5 V
VDD= 5.25 V, V

Supply Current VDD= 5.25 V 100 mA

DD

Peak-to-Peak Voltage 0.5 13.2 V

IPP

Input low Voltage VDD= 5.25 V 1.5 V

IL

Input High Voltage VDD= 5.25 V 3.5 V

IH

Input Low Current VDD= 5.25 V, VIL= 1.5 V –0.4 mA

I

IL

R Pull-up Resistor 30 kΩ

V

I

O (off)

V

I

O (off)

V

I

O (off)

V
V

I

OL

OL

OL

IL
IH

IL

VDD= 4.75 V, IOL= 20 mA 1.5 V
VDD= 5.25 V, V
VDD= 4.75 V, IOL= 4 mA 1 V
VDD= 5.25 V, V
VDD= 4.75 V, IOL= 1 mA 0.4 V
VDD= 5.25 V, V

VDD= 5.25 V, VIL= 0.8 V –0.4 mA

R Pull-up Resistor 30 kΩ

Write Peak

Average

Erase Peak

Average

Read Peak

Average

= 26 V 100 µA

OUT

= 13.2 V 50 µA

O (off)

= 13.2 V 100 µA

O (off)

= 13.2 V 100 µA

O (off)

= 13.2 V 50 µA

O (off)

= 13.2 V 50 µA

O (off)

42
12

9
5
8

2.5

0.8 V

2.0 V

V
V

mA

491B-01.TBL

491B-02.TBL

3/16

M491B

DC ELECTRICALCHARACTERISTICS (continued)

Pin Symbol Parameter Test Conditions Min. Typ. Max. Unit

18–19–20
V3

Keyboard

V2

}

In

V1
21–22–23–24

X4

Keyboard

X3

}

X2

Out

X1

V

IL

V

IH

I

IL

R Pull-up Resistor 30 kΩ

V

OL

I

O(off)

1.5 V

3.5 V

VDD= 5.25 V, VIL= 0.8 V –0.4 mA

VDD= 4.75 V, IOL= 1 mA 0.4 V

V

= 5.5 V 25 µA

O (off)

V

IL

25–Mains On En­able

26–Mains On/Off

31–Z2
32–Z1
MPX for
Display Out

37–UHF
38–CATV
39–VHFIII
40–VHFI

27-28-29-30-33­34-35 Display Out

36-Display Out V
31-Memory 8/16

}

B
A
N
D

DESCRIPTION(All timingsat f

PIN 1 : V

SS

V

IH

I

IL

R Pull-up Resistor V

V

OL

I

O

V

OL

I

O(off)

V

OL

V

OH

V

IL

V

IH

I

O(off)

V

OL

OL

V

IH

V

IL

= 500kHz)

clock

Thesubstrateof theIC isconnectedto thispin.This
is thereferencepin for all parameters of the IC.

PIN 2 : MEMORY SUPPLYVOLTAGE
A supply voltage of 25 ± 1 V has to be appliedto
this pin duringthe modifyand read cycles.

MODIFYCYCLE
Amodify cycleconsistsof threesteps :

1.All”1”sarewritten inthebitsoftheselectedword.

2. All bits of the selectedword areerased (all ”0”s)

3. Thenew contentis written.
Thus a constantaging of all thebits of theword is

0.8 V

2.4 V

VDD= 5.25 V –0.4 mA

= 0.8 V 30 kΩ

IL

VDD= 4.75 V, IOL= 100 µA 0.4 V
VDD= 4.75 V, VO= 0.7 V –1.6 mA

VDD= 4.75 V, IOL= 1 mA 0.4 V

VDD= 5.25 V, V
VDD= 4.75 V, IOL= 1 mA 3 V

VDD= 4.75 V, IOH= – 150 µA 2.4 V

VDD= 5.25 V, V
VDD= 4.75 V, IOL= 20 mA 1.5 V

VDD= 4.75 V, IOL= 30 mA 1.5 V

= 13.2 V 50 µA

O (off)

3 V

= 13.2 V 50 µA

O (off)

2.0 V

0.3 V

0.8 V

obtained.
During both write and erase cycles the memory
status is checked continuously ; therefore after
eachwriteorerasepulseareadoperationiscarried
out. The write orthe erase operationsare stopped
as soon as the result of theread operationis valid.

WRITE CYCLE. The peak of the current flowing
throughpin 2 duringa writeoperation is shown in
fig. 1, while fig. 2 shows the envelopeof thesame
current.

The typical write time is 3-4 ms for the firstcycles
and increasesto about30 ms after1000 cycles.

491B-03.TBL

4/16

Figure1

M491B

40mA

12mA

6mA

64 32 44 116µs

256µs

Figure2

I (mA)

40

12

5

Typ.max. 20msec Typ.max. 8msec

ERASECYCLE
Figure3 showsthe timingand thewaveform of the
current flowing through Pin 2 during the erase
operation. The peak current is 7mA (max) during
the erase cycle and 6mA (max) during the read
cycle. The typical erase time is 10ms for a new
device and increases with the number of modify

Afterabout30msec

491B-03.EPS

t (ms)

491B-04.EPS

operationsup to200ms after 1000 cycles.
In orderto protect the memoryincase of failureof
some bits the modify operation is stopped after
1sec.
READCYCLE
Figure 4 shows the waveformofthe currentduring
a read operation.

Figure3

128µs 52

32 44

256µs

7mA

6mA

Figure4

491B-05.EPS

44

6mA

84µs

128µs

480µs

491B-06.EPS

5/16