SGS Thomson Microelectronics M36DR432C Datasheet

32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory

and 4 Mbit (256K x16) SRAM, Multiple Memo ry Product

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V

DDF=VDDS

–V

■ ACCE SS TIME: 8 5,100ns

■ LOW POWER CO NS UMPT ION

■ ELECTRONIC SIGNATURE

= 12 V for Fast Program (optional)

PPF

– Manufacturer Code: 20h
– Top Device Code, M36DR432C: 00A4h
– Bottom Device Code, M 36DR432D: 00A5h

FLASH MEMORY

■ 32 Mbit (2Mb x16)BOOT BLOCK

– Parameter Block s (Top or Bottom Location)

■ PROGRAMMING TIME

– 10µs typical
– Double Word Programming Option

■ ASYNCRONOUS PAGE MODE READ

– Page width: 4 Word
– Page Mode Access Time: 35ns

■ DUAL BANK OPERATION

– Read within one Bank while Program or

Erase within the other

– No Delay between Read and Write

Operations

■ BLOCK PROTECTION ON ALL BLOCKS

–WPF

■ COMMON FLASH INTERFACE

for Block Locking

– 64 bit Security Code

SRAM

■ 4 Mbit (256K x 16 bit)

■ LOW V

■ POWER DOWN FEATURES USING TWO

DDS

CHIP ENABLE INPUTS

=1.9V to 2.1V

DATA RETENTION: 1 V

M36DR432C
M36DR432D

PRELIMINARY DATA

Figure 1 . Packages

FBGA

Stacked LFBGA66 (ZA)

8 x 8 ball array

November 2001

This is preliminary information on anew product nowin development or undergoing evaluation. Details are subject to change without notice.

1/46

M36DR432C, M36DR432D

DESCRIPTION

The M36DR432 is a multichip memory device con­taining a 32 Mbit boot block Flash memory and a
4MbitofSRAM.ThedeviceisofferedinaStacked
LFBGA66 (0.8 mm pitch) pack age.

Thetwo components are distinguished by use with
three chip enable inputs: EF
and, E1S

and E2S for t he SRAM. The two c ompo­nents are also separately power supplied and
grounded.

Figure 2. Logic Diagram

fortheFlash memory

Table 1. Signal Names

A0-A17 Address Inputs
A18-A20 Address Inputs for Flash Chip only
DQ0-DQ15 Data Input/Output
V

V

V

DDF

PPF

SSF

Flash Power Supply
Flash Optional Supply Voltage for Fast

Program & Erase
Flash Ground

A0-A20

EF

GF

WF

RPF

WPF

E1S
E2S

GS

WS

UBS

LBS

21

V

V

DDF

M36DR432C
M36DR432D

V

SSF

PPF

V

V

DDS

SSS

16

DQ0-DQ15

AI05522

V

DDS

V

SSS

NC Not Connected Internally

Flash control functions

EF
GF
WF
RPF
WPF

SRAM control functions

, E2S Chip Enable input

E1S
GS
WS
UBS
LBS

SRAM Power Supply
SRAM Ground

Chip Enable input
Output Enable input
Write Enable input
Reset input
Write Protect input

Output Enable input
Write Enable input
Upper Byte Enable input
Lower Byte Enable input

2/46

Figure 3. LFBGA Connections (Top view through package)

M36DR432C, M36DR432D

#2#1

A

B

C

D

E

F

G

H

SSS

NC V

A8 A10

RPF

V

PPF

UBS

A17

A5

A15 A14

DQ11A19WPF

A13A11A20NCNC

DQ15A9A16

DQ9GSLBS

EFA0A4NCNC

A12

WS

DQ6DQ13NCWF

E2SDQ12V

DQ10

DQ8

A2A3A6A7A18

SSF

V

SSF

DQ14

DQ4

V

DDS

DQ7

DQ5

V

DQ3DQ2

DQ1DQ0

E1SA1

87654321

NC

DDF

NCNCGF

#4#3

NCNC

NC

AI90204

3/46

M36DR432C, M36DR432D

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

DDF

V

DDS

V

PPF

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi­tionsforextendedperiodsmayaffectdevice reliability.Referalsoto the STMicroelectronics SUREProgram and other relevant qual­ity documents.

2. Minimum voltage may undershoot to –2V during transition and for less than 20ns.

3. Depends on range.

4. V

DD=VDDS=VDDF

Ambient Operating Temperature
Temperature Under Bias –40 to 125 °C
Storage Temperature –55 to 150 °C

Input or Output Voltage
Flash Chip Supply Voltage –0.5 to 2.7 V
SRAM Chip Supply Voltage –0.2 to 2.6 V

Program Voltage –0.5 to 13.0 V

.

(3)

–40 to 85 °C

–0.2 to V

DD

(4)

+0.3

V

Figure 4. Functional Block Diagram

V

DDF

V

PPF

EF

GF

WF

RPF

WPF

A18-A20

A0-A17

E1S
E2S

GS

WS

UBS

LBS

Flash Memory

32 Mbit (x16)

V

DDS

SRAM

4 Mbit (x16)

V

SSF

DQ0-DQ15

4/46

V

SSS

AI90205

SIGNAL DESCRIPTIONS

See Figure 2 and Table 1.
Address Inputs (A0-A17). Address es A0 to A17

are common inputs for the Flas h chip and the
SRAM chip. The address inputs for the Flash
memory are latched during a write operation on
the falling edge of the Fla sh Chip Enable (EF
Write Enable (WF

), while address inputs for the

)or

SRAM array are latched during a write o peration
on the falling edge of the SRAM Chip Enable l ines

or E2S) or Write Enable (WS).

(E1S
Address Inputs (A18-A20). Address A18 to A20

are address inputs for the Flash chip. They are
latched during a write operation on the falling edge
of Flash Chip Ena ble (EF

) or Write Enable (WF).

Data Input/Outputs (DQ0-DQ15). The input is
data to b e programmed in the Flash or SRAM
memory array or a command to be written to the
C.I. of the Flash chip. B oth are latched on the ris­ing edge of Flash Chip Enable (EF
able (WF
E2S) or Write Enable (WS

) and, SRAM Ch ip Enable lines (E1S or

). The output is data

)orWriteEn-

from the Flash memory or SRAM array, the Elec­tronic Signature Manufacturer or Device codes or
the S tatus r egister Data Polling bit DQ7, the Tog­gle Bits DQ6 and DQ2, the Error bit DQ5 or the
Erase Timer bit DQ3. Outputs are valid when
Flash Chip Enable (E F
SRAM Chip Enable lines (E1S
Enable (GS

) are active. The output is high imped-

) and Outp ut Enable (GF)or

or E2S) and Output

ance when the both the Flash chip and the SRAM
chip are deselected or the outputs are disabled
and when Reset (RPF

Flash Chip Enable (EF

)isataVIL.

). The Chip Enable input
for Flash activates the memory control logic, input
buffers, decoders and sense amplifiers. E F

at V

IH

deselects t he memoryand reduces the power c on­sumption to the standby level and output do Hi-Z.

canalsobeusedtocontrolwritingtothecom-

EF
mand register and to the Flash memory array,
while WF

remains at VIL.ItisnotallowedtosetEF

at VIL,E1Sat VILand E2S at VIHat the same time.

Flash Write Enable (WF

). The Write Enable in-

put c ontrols writing to the Command Register of
theFlash chip and Address/Datalatches.D ata are
latched on the rising edge of WF

Flash Output Enable (GF

.

). The Output Enable
gates the outputs through the data buffers during
a read operation of the F lash chip. When GF
WF

are High the outputs are High impedance.

Flash Reset/Power Down Input (RPF

). The RPF

and

input provides hardware reset of the memory
(without af fecting the Configuration Register sta­tus), and/or Power Down functions, dep ending on
the Configuration Regis ter status. Reset/Power
Down of the memory is achieved by pulling RPF
V

for at least t

IL

. When the reset pulse is giv-

PLPH

to

M36DR432C, M36DR432D

en, ifthe memory is in Read, Erase Suspend Read
or Standby, it will out put new valid data in t
after the rising edge of RP F.Ifthememoryisin
Erase or Program modes, the operation will be
aborted and the reset recovery will take a maxi­mum of t
Power Down (when enabled) in t
rising edge of RPF

. The mem ory will recover from

PLQ7V

PHQ7V2

. See Tables 1, 26 and Figure

11.

Flash Write Protect (WP F

). Write Protect is an

input to protec t or unprotect the t w o lockable pa­rameter blocks of the Flash memory. When WPF
is at VIL, the lockable blocks are protected. Pro­gram or erase operations are not achievable.
When WPF

is at VIH, the lockable block s are un­protected and they can be programmed or erased
(refer to Table 17).

SRAM Chip Enable (E1S

,E2S). The Chip En-

able inputs for SRAM activate the memory c ontrol
logic, input bu ffers and decoders. E1S
E2S at V

deselects the memory and reduces the

IL

power consumption to the standby level. E1S
E2S can a lso be used to control writing to the
SRAM memory array, while WS
is not allowed to set EF

at the same time.

at V

IH

SRAMWriteEnable(WS

at VIL,E1Sat VILand E2S

). The Write Enable in-

remains at VIL.It

put controls writing to the SRAM memory array.
WS

is activelow.

SRAM Output Enable (GS

). T he Output Enable

gates the outputs through the data buffers during
a read operation of the SRAM chip. GS
low.

SRAM Upper Byte Enable (UBS

). Enable the

upper bytes for SRAM (DQ8-DQ15). UBS
low.

SRAM Lower Byte Enable (LBS

). Enable the

lower bytes for SRA M (DQ0-DQ7). LBS
low.

Supply Voltage (1.9V to 2.1V). Flash memory

V

DDF

power supply for all operations (Read, Program and
Erase).

Programming Voltage (11.4V to 12.6V).

V

PPF

Used to provide high voltage for fas t factory pro­gramming. High voltage on V

pin is required to

PPF

use the Double Word Program instruction. It is
also possible to perform word program or erase in­structions with V

Supply Voltage (1.9V to 2.1V). SRAM pow-

V

DDS

pin grounded.

PPF

er supply for all operations (R ead, Program).

V

SSF

and V

Ground. V

SSS

SSF

and V
reference for all v olt age measurements respec ­tively in the Flash and SRAM chips.

PHQ7V1

after the

at VIHor

is active

isactive

is active

are the

SSS

and

5/46

M36DR432C, M36DR432D

Table 3. Main Operation Modes

Operation

Mode

Read

Write

Block
Locking

Standby

Flash Memory

Reset X X X

Output
Disable

Read Flash must be disabled

Write Flash must be disabled

Standby/
Power
Down

SRAM

Data
Retention

Output
Disable

Note: X = VILor VIH,V

1. If UBS

and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.

GF WF RPF WPF

EF

V

ILVILVIHVIH

V

ILVIHVILVIH

V

IL

V

IH

XX

XX

V

V
V

V

ILVIHVIHVIH

Any Flash mode is allowable

Any Flash mode is allowable

Any Flash mode is allowable

=12V±5%.

PPFH

V

PPF

E1S E2S GS WS

UBS,LBS

X Don't care SRAM must be disabled

V

or

V

IH

V

IH

IL

X Don't care Any SRAM mode is allowable Hi-Z

IH

X Don't care Any SRAM mode is allowable Hi-Z

IL

DDF

V

PPFH

SRAM must be disabled Data Input

Don't care SRAM must be disabled X

X Don't care Any SRAM mode is allowable Hi-Z

V

ILVIHVILVIH

V

ILVIHVIHVIL

V

XXX X Hi-Z

IH

V

X

X X X Hi-Z

IL

XXXX

V

XXX X Hi-Z

IH

V

X

X X X Hi-Z

IL

XXXX

V

ILVIHVIHVIH

V

IL

V

IL

V

IH

V

IH

X Hi-Z

(1)

DQ15-DQ0

Data

Output

Data out

Word Read

Data in

Word Write

Hi-Z

Hi-Z

6/46

FLASH MEMORY COMPONENT
Organization

The Flash Chip is organized as 2Mb x16 bits. A0­A20 are the address lines, DQ0-DQ15 are the
Data Input/Output. Memory control is provided by
Chip Enable EF
able WF

inputs.

Reset RPF

, Output Enable GF and Write En-

is used to reset all the memory circuitry
and to set the chip in power down mode if this
function is e nabled by a p ro per setting of the Con­figuration Register. Erase and Program operations
are controlled by an internal Program/Erase Con­troller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, DQ6 and DQ2
provide Toggle signals and DQ5 provides error bit
to indicate the state of the P/E.C operations.

Memory Blocks

The device features asymmetrically blocked archi­tecture. The Flash Chip has an array of 71 blocks
and is divided into two banks A and B, providing
Dual Bank operations. While programming or
erasing in Bank A, read operations are possib le
into Bank B or vice versa. The m emory also fea­tures an erase suspend allowing to read or pro­gram in another block within the s ame bank. Once
suspended the erase can be resumed. The Bank
Size and Sectorization are s ummarized in Table 4.
Parameter Blocks are located at the top of the
memory address space for the Top version, and at
the bottom for the Bottom version. The memory
maps are shown in Tables 5, 6, 7 and 8.

The Program and E r as e operations are managed
automatically by the P/E.C. Block protection
against Program or Erase provides additio nal data
security. All blocks are protected at Po wer Up. I n­structions are provid ed to protect or unprotect any
block in the application. A second register locks
the protection status while WPF

is low (see Block
Locking description). The Reset command does
not affect the configuration of unprotected blocks
and the Configuration Register status.

Device Operatio ns

The following operations can be performed using
the appropriate bus cycles: Read Array (Random,
and Page Modes), Write command, Output Dis­able, Standby, Res et/Power Down and Block
Locking. See Table 9.

Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig­nature, t he Status Reg ister, the CFI, the Block
Protection Status or the Configurat ion Register
status. Read operation of the memory array is per­formed in asynchronous page mode, that provides
fast acc es s time. Data is internally read and stored
in a page buffer. The page has a size of 4 words

M36DR432C, M36DR432D

and is addressed by A0-A1 address inputs. Read
operations of the Electronic Signature, the Status
Register, the CFI, the Block P r otection Status, the
Configuration Register status and the Security
Code are performed as single asynchronous read
cycles (Random Read). Both Chip Enable EF
Output Enable GF

must be at VILin order to read

the output of the memory.
Write. Write operations are used to give Instruc-

tion Commands to the memory or to latch I nput
Data to be programmed. A write operation is initi­ated when Chip E nable EF

and Write Enable WF
are at VILwith Output Enable GF at VIH.Address­es are latched on the falling edge of W F
whichever occurs last. Commands and Input Data
are latched on the rising edge of WF

or EF which­ever occursfirst. Noise pulses of less than 5ns typ­ical on EF

,WFand GF signal s do not st art a write

cycle.
Dual Bank Operations. The Dual Bank allows to

read data from one bank of m emory while a pro­gram or erase operation is in progress in the other
bank of the memory. Re ad and Write cycles can
be ini tia ted for simultaneous operations in different
banks without any delay. Status Register during
Program or Erase m ust be monitored using an ad­dress within the bank being modified.

Output Disable. The data outputs are high im­pedance when the Output Enable GF
Write Enable WF

at VIH.

is at VIHwith

Standby. The memory is in standby when Chip
Enable EF

is at VIHand the P/E.C. is idle. T he
power c onsumption isreduced to the standbylevel
and the outputs are high impedance, independent
of the Output Ena ble GF

or Write Enable WF in-

puts.
Automatic Standby. When in Read mode, after

150ns of bus inactivity and when CMO S lev els are
driving the addresses, the chip automatically en­ters a pseudo-stan dby mode where consum ption
is reduced to the CMOS st andby value, while out­puts still drive the bus.

Power Down. The memory is in Power Down
when the C onfiguration Register is set for Power
Down and RPF

is at VIL. The power c onsumption
is reduced t o the Powe r Down level, and Outputs
are in high im pedance, independent of the Chip
Enable EF

, Output Enable GF or Write Enable WF

inputs.
Block Locking. Any c ombination of block s can

be temporarily protected again st Program or
Erase by setting the lock register and pulling WPF
to VIL(see Block Lock instruction).

and

or EF

7/46

M36DR432C, M36DR432D

Table4.BankSizeandSectorization

Bank Size Parameter Blocks Main Blocks

Bank A 8 Mbit 8 blocks of 4 KWord 15 blocks of 32 KWord
Bank B 24 Mbit - 48 blocks of 32 KWord

Table 5. Bank A, Top Boot Block Ad dresses
M36DR432C

#

22 4 1FF000h-1FFFFFh
21 4 1FE000h-1FEFFFh
20 4 1FD000h-1FDFFFh
19 4 1FC000h-1FCFFFh
18 4 1FB000h-1FBFFFh
17 4 1FA000h-1FAFFFh
16 4 1F9000h-1F9FFFh
15 4 1F8000h-1F8FFFh
14 32 1F0000h-1F7FFFh
13 32 1E8000h-1EFFFFh
12 32 1E0000h-1E7FFFh
11 32 1D8000h-1DFFFFh
10 32 1D0000h-1D7FFFh

9 32 1C8000h-1CFFFFh
8 32 1C0000h-1C7FFFh
7 32 1B8000h-1BFFFFh
6 32 1B0000h-1B7FFFh
5 32 1A8000h-1AFFFFh
4 32 1A0000h-1A7FFFh
3 32 198000h-19FFFFh
2 32 190000h-197FFFh
1 32 188000h-18FFFFh
0 32 180000h-187FFFh

Size

(KWord)

Address Range

Table 6. Bank B, Top Boot Block Ad dresses
M36DR432C

#

47 32 178000h-17FFFFh
46 32 170000h-177FFFh
45 32 168000h-16FFFFh
44 32 160000h-167FFFh
43 32 158000h-15FFFFh
42 32 150000h-157FFFh
41 32 148000h-14FFFFh
40 32 140000h-147FFFh
39 32 138000h-13FFFFh

Size

(KWord)

Address Range

38 32 130000h-137FFFh
37 32 128000h-12FFFFh
36 32 120000h-127FFFh
35 32 118000h-11FFFFh
34 32 110000h-117FFFh
33 32 108000h-10FFFFh
32 32 100000h-107FFFh
31 32 0F8000h-0FFFFFh
30 32 0F0000h-0F7FFFh
29 32 0E8000h-0EFFFFh
28 32 0E0000h-0E7FFFh
27 32 0D8000h-0DFFFFh
26 32 0D0000h-0D7FFFh
25 32 0C8000h-0CFFFFh
24 32 0C0000h-0C7FFFh
23 32 0B8000h-0BFFFFh
22 32 0B0000h-0B7FFFh
21 32 0A8000h-0AFFFFh
20 32 0A0000h-0A7FFFh
19 32 098000h-09FFFFh
18 32 090000h-097FFFh
17 32 088000h-08FFFFh
16 32 080000h-087FFFh
15 32 078000h-07FFFFh
14 32 070000h-077FFFh
13 32 068000h-06FFFFh
12 32 060000h-067FFFh
11 32 058000h-05FFFFh
10 32 050000h-057FFFh

9 32 048000h-04FFFFh
8 32 040000h-047FFFh
7 32 038000h-03FFFFh
6 32 030000h-037FFFh
5 32 028000h-02FFFFh
4 32 020000h-027FFFh
3 32 018000h-01FFFFh
2 32 010000h-017FFFh
1 32 008000h-00FFFFh
0 32 000000h-007FFFh

8/46

M36DR432C, M36DR432D

Table7. BankB,Bottom BootBlock Addresses
M36DR432D

#

47 32 1F8000h-1FFFFFh
46 32 1F0000h-1F7FFFh
45 32 1E8000h-1EFFFFh
44 32 1E0000h-1E7FFFh
43 32 1D8000h-1DFFFFh
42 32 1D0000h-1D7FFFh
41 32 1C8000h-1CFFFFh
40 32 1C0000h-1C7FFFh
39 32 1B8000h-1BFFFFh
38 32 1B0000h-1B7FFFh
37 32 1A8000h-1AFFFFh
36 32 1A0000h-1A7FFFh
35 32 198000h-19FFFFh
34 32 190000h-197FFFh
33 32 188000h-18FFFFh
32 32 180000h-187FFFh
31 32 178000h-17FFFFh
30 32 170000h-177FFFh
29 32 168000h-16FFFFh
28 32 160000h-167FFFh
27 32 158000h-15FFFFh
26 32 150000h-157FFFh
25 32 148000h-14FFFFh
24 32 140000h-147FFFh
23 32 138000h-13FFFFh
22 32 130000h-137FFFh
21 32 128000h-12FFFFh
20 32 120000h-127FFFh
19 32 118000h-11FFFFh
18 32 110000h-117FFFh
17 32 108000h-10FFFFh
16 32 100000h-107FFFh
15 32 0F8000h-0FFFFFh
14 32 0F0000h-0F7FFFh
13 32 0E8000h-0EFFFFh
12 32 0E0000h-0E7FFFh
11 32 0D8000h-0DFFFFh

Size

(KWord)

Address Range

10 32 0D0000h-0D7FFFh

9 32 0C8000h-0CFFFFh
8 32 0C0000h-0C7FFFh
7 32 0B8000h-0BFFFFh
6 32 0B0000h-0B7FFFh
5 32 0A8000h-0AFFFFh
4 32 0A0000h-0A7FFFh
3 32 098000h-09FFFFh
2 32 090000h-097FFFh
1 32 088000h-08FFFFh
0 32 080000h-087FFFh

Table8. BankA,Bottom BootBlock Addresses
M36DR432D

#

22 32 078000h-07FFFFh
21 32 070000h-077FFFh
20 32 068000h-06FFFFh
19 32 060000h-067FFFh
18 32 058000h-05FFFFh
17 32 050000h-057FFFh
16 32 048000h-04FFFFh
15 32 040000h-047FFFh
14 32 038000h-03FFFFh
13 32 030000h-037FFFh
12 32 028000h-02FFFFh
11 32 020000h-027FFFh
10 32 018000h-01FFFFh

9 32 010000h-017FFFh
8 32 008000h-00FFFFh
7 4 007000h-007FFFh
6 4 006000h-006FFFh
5 4 005000h-005FFFh
4 4 004000h-004FFFh
3 4 003000h-003FFFh
2 4 002000h-002FFFh
1 4 001000h-001FFFh
0 4 000000h-000FFFh

Size

(KWord)

Address Range

9/46

M36DR432C, M36DR432D

Table 9. User Bus Operations

(1)

Operation EF GF WF RPF WPF DQ0-DQ15

Write
Output Disable
Standby

V

IL

V

IL

V

IH

Reset / Power Down X X X
Block Locking

Note: 1. X = Don't care.

V

IL

V

IH

V

IH

V

IL

V

IH

XX

XX

V

IH

V

IH

V

IH

V

IL

V

IH

Table 10. Read Electronic Signature (AS and Read CFI instructions)

Code Device EF

Manufacturer Code

M36DR432C

Device Code

M36DR432D

Note: 1. t.b.a. to be announced.

GF WF A0 A1 A2-A7

V

V

V

IL

IL

V

V

IL

IL

V

V

IL

IL

IH

V

IHVIH

V

IHVIH

V

IL

V
V
V

0 Don't Care 20h 00h

IL

0 Don't Care

IL

0 Don't Care

IL

Table 11. Read Block Protection (AS and R ead CFI instructions)

Block Status EF GF WF A0 A1 A2-A7

Protected Block
Unprotected Block
Locked Block

V

ILVILVIHVILVIH

V

ILVILVIHVILVIH

V

ILVILVIHVILVIH

0 Don't Care Block Address 1 0 0000h
0 Don't Care Block Address 0 0 0000h
0 Don't Care Block Address X 1 0000h

Other

Addresses

A12-A20 DQ0 DQ1 DQ2-DQ15

Other

Addresses

V

IH

V

IH

V

IH

V

IH

V

IL

Data Input

Hi-Z
Hi-Z
Hi-Z

X

DQ0-DQ7 DQ8-DQ15

t.b.a.
t.b.a.

(1)

(1)

t.b.a.
t.b.a.

(1)

(1)

Table 12. Read Config ura tion Register (AS and Read CFI instructions)

RPF

Function EF GF WF A0 A1 A2-A7 Other Addresses DQ10

V

V

V

Reset
Reset/Power Down

10/46

V

IL

IL

IH

V

V

IL

V

IL

IH

V

IH

V

V

IH

0 Don't Care 0 Don't Care

IH

0 Don't Care 1 Don't Care

IH

DQ0-DQ9

DQ11-DQ15

INSTRUCTIONS AND CO MMANDS

Seventeen instructions are def ined (s ee Table

15), and the internal P/E.C. a utomat icall y handles
all timi ng and verification of the P rogram and
Erase operations. The Stat us Register Data Poll­ing, Toggle,Error bits can beread at any time, dur­ing programming or erase, to monitor the progress
of the operation.

Instructions, made up of one or more commands
writtenincycles,canbegiventotheProgram/
Erase Controller through a Command Interface
(C.I.). The C.I. latches commands written to t he
memory. Commands are made of address and
data sequences . Two Coded Cycles unlock the
Command Interface. Theyare followed by an input
command or a confirmation command. The Coded
Sequence consists of writing the data AAh at the
address 555h during the f irst cycle and the data
55h at t he address 2AAh during the second cycle.

Instructions are composed of up to six cycles. The
first two cycles input a Coded Sequence to the
Command Interface which is common to all in­structions (see Table 15). The third cycle inputs
the instruct ion set-up command. Subs equent cy­cles output t he add re ssed data, Electronic Signa­ture, Block Protection, C onfiguration Register
Status or CFI Query for Read operations. In order
to give additional data protection, the instruct ions
for Block Erase and Bank Eras e require further
command inputs. For a Program instruction, the
fourthcommand cycle inputsthe addressand data
to be programmed. For a Double W ord Program­ming inst ruc tion, the fourth and fifth command cy­cles input the address and data to be
programmed. For a B lock Erase and Bank Erase
instructions, the fourth and fifth c ycle s input a fur­ther Coded Sequence before the Erase co nfirm
command on the sixth cycle. Any combination of
blocks of the same mem ory bank can be erased.
Erasure of a memory block may be suspended, in
order to read data from another block or to pro­gram data in another block, and then resumed.
When power i s first applied the command interface
is reset t o Read Array.

Command sequencing must be f ollo wed exactly.
Any invalid combination of commands will reset
the device to Read A rray. The increased number
of cycles has been chosen to ensure maximum
data security.

M36DR432C, M36DR432D

Table 13. Commands

Hex Code Command

00h Bypass Reset
10h Bank Erase Confirm
20h Unlock Bypass
30h Block Erase Resume/Confirm
40h Double Word Program

Block Protect, or

60h

80h Set-up Erase

90h

98h CFI Query
A0h Program
B0h Erase Suspend

F0h Read Array/Reset

Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded Cycles. Subsequent read opera­tions will read the memory array addressed and
output the data read.

CFI Query (RCF I) Instruction. Common Flash
Interface Query mode is entered writing 98h at ad­dress 55h. The CFI data structure gives informa­tion on the device, suc h as the sectorization, the
command set and some electrical specifications.
Table 18, 19, 20 and 21 sh ow the addresses us ed
to retrieve each data. The CFI data structure con­tains also a security area; in this section, a 64 bit
unique security number is written, starting at ad­dress 80h. This area can be accessed only in read
mode by the final user and there are no ways of
changing the code afte r it has been written by ST.
Write a read instruction (RD) to return to Read
mode.

Auto Select (AS) Instruction. This instruction uses
two Coded Cycles followed by one write cycle giv­ing the comm and 90h to address 555h for com­mand set-up. A subsequent read will outpu t the
Manufacturer or the Dev ice Code (Electronic Sig­nature), the Block Protection status or the Config­uration Register status depending on the levels of
A0 and A1 (see Table 10, 11 and 12). A 7-A2 must
be at V

Block Unprotect, or
Block Lock, or
Write Configuration Register

Read Electronic Signature, or
Block Protection Status, or
Configuration Register Status

, w hile ot her address input are ignored.

IL

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M36DR432C, M36DR432D

The bank address is don’t care for this instruction.
The Electronic Signature can be read from the
memory allowing programming equipment or ap­plications to autom ati c ally match their interface to
the characteristics of Flash Chip. The Manufactur­er Code is output when the address lines A0 and
A1 are at V
is at V

, the Device Code is output when A0

IL

with A1 at VIL.

IH

The codes are output on DQ 0-DQ7 with DQ8­DQ15 at 00h. The AS instruction also allows the
access to the Block Protection Status. After giving
the A S inst ruction, A0 is set to V

with A1 at VIH,

IL

while A12-A20 define the address of the block t o
be verified. A read in these conditions w ill output a
01h if the block is protected and a 00h if the block
is not protected.

The AS Instruction final ly allows the access to the
Configuration Register status if both A0 and A1
are set to V
is active as RPF

. IfDQ 10 is '0' only the Reset function

IH

is set to VIL(default at power-up).
If DQ10 is '1' both the Reset and the Power Down
functions will be achieved by pulling RPF

to VIL.
The other bits of the Configuration Register are re­served and must be ignored. A reset command
puts the device in read array mode.

Write Configuration Register (CR) Instruc­tion. Th is instruction uses two Coded Cycles fol-

lowed by one write cycle giving the command 60h
to addres s 555h. A fu rther write cycle giving the
command 03h writes the contents of address bits
A0-A15 to the 16 bits configuration register. Bits
written by inputs A0-A9 and A11-A15 are reserved
for future use. Address input A10 defines the sta­tus of the Reset/Power Down funct ions. It must be
set to V
V

IH

to enable only the Reset function and to

IL

to enable also the Power Down function. At
Power Up all the Configuration Register bits are
reset to '0'.

Enter Bypass Mode (EBY) Instruction. This in­struction uses the two Coded cycles follo wed by
one write cycle giving the com mand 20h to ad­dress 555h for mode set-up. Onc e in By pas s
mode, the device will accept the Exit Bypass
(XBY) and Program or Double Word Program in
Bypass mode (PGBY, DPGBY) commands. The
Bypass mode allows to reduce th e overall pro­gramming time when large memory arrays need to
be programmed.

Exit Bypass Mode (XBY) Instruction. This in-
struction uses two write cycles. The first inputs to
the memory the command 90h and the second in­puts the Exit Bypass mode confirm (00h). After the
XBYinstruction, thedeviceresets to Read Memo­ry Array mode.

Program in Bypass Mode (PGBY) Instruc­tion. This instruction uses two write cycles. The

Program command A0h is written t o any Address
on the first cycle and the second write cycle latch-

esthe Address on the falling edge of WF

or EF and
the Data to be written on the rising edge and starts
the P /E. C . Read operations within the same bank
output the Status Register bits after the program­ming has started. Memory programming is m ade
only by writing '0' in place of '1'. Status bits D Q6
and DQ7 determine if programming is on-going
and DQ5 allows verification of any possible error.

Program (PG) Instruction. This instruction uses
four write cycles. The Program co mmand A0h is
written t o address 555h on the third cycle af ter two
Coded Cycles. A fourth write operation latches t he
Address and the Data to be written a nd starts the
P/E.C. Read operations within the same bank out­put the Status Register bits after the programming
has started. Memory programming is made only
by writing '0' in place of '1'. Status bits DQ6 and
DQ7 determine if programming is on-going and
DQ5 allows verification of any possible error. P ro­gramming at an address not in blocks being
erased is also possible during erase suspend.

Double Word Program (DPG) Instruction. This
feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel. High voltage (11.4V to 12.6V) on V

PP

pin is required. This instruction uses five write cy­cles. The double word program command 40h is
written t o address 555h on the third cycle af ter two
Coded Cycles. A fourth write cycle latches th e ad­dress and data to be written to the first location. A
fifth write cycle latches the new data to be written
to the second location and starts the P/E.C.. Note
thatthe two locations m us t have the same address
except for the address bit A0. The Double Word
Program can be executed in Bypass mode (DP G­BY) to skip the two coded cycles at the beginning
of each command.

Block Protect (BP), Block Unprotect (BU),
Block Lock (BL) Instructions. All blocks are

protected at power-up. Each block of the array has
two levels of protection against program or erase
operation. The first level is set by the Block Protect
instruction; a p rotect ed block cannot be pro­grammed or erased until a Block Unprotect in­struction is given for that block. A second level of
protection is set by the Block Lock instruction, and
requires the use of the WPF

pin, according to the

following scheme:
– when WP F

is at VIH, the Lock status is overrid­den and all blocks can be protected or unpro­tected;

– when WPF

is at VIL, Lock status is enabled; the
locked blocks are protecte d, regardless of their
previous protect state, and protection status
cannot be changed. Blocks that are not locked
can still change their protection status, and pro­gram or erase accordingl y;

12/46

M36DR432C, M36DR432D

– the lock status is cleared for all blocks at power

up; once a block has been locked state can be
cleared only with a reset command. The protec­tion and lock status can be monitored for each
block using the Autoselect (AS) instruction. Pro­tected blocks will output a ‘1’ on DQ0 and locked

blocks will output a ‘1’ on DQ1.
Refer to Table 14 for a list of the protection states.
Block Erase (BE) Instruc tion. This instruction

uses a m inimum of six write cycles. The Eras e
Set-up command 80h is written to address 555h
on third cycle after the two Coded cycles. The
Block Erase Confirm command 30h is similarly
written on the sixth cycle after another two Coded
cycles and an address wit hin the block to be
erased is given and latched into the memory.

Additional block Erase Confirm commands and
block addresses can be written subsequently to
erase other block s in parallel, witho ut further Cod­ed cycles. All blocks must belong to the same
bank of memory; if a new block belonging to the
other bank is given, t he operation is abort ed. The
erase will start a fter an erase timeout period of
100µs. Thus, additional Erase Confirm commands
for other blo cks must be given within this delay.
The input of a new Erase Confirm comman d will
restart the timeout period. The s tatus of the inter­nal timer can be monitored through the level of
DQ3, if DQ3 is '0' the B lock Erase Command has
been given and the timeout isrunning , if DQ3 is '1',
the t imeout has expired and the P/ E.C. is erasing
the B lock(s). If the second command given is not
an erase confirm or if the Coded cycles are wrong,
the instruction aborts, and the device is reset to
Read Array. It is not necessary t o program t he
block with 00h as the P/E.C. will do this automati­cally before erasing to FFh. Read operations with­in the same bank, after the sixth rising edge of WF
or EF, output the status register bits.

During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
instruction; t he Read/Reset RD instruction is ac­cepted during the 100µs time-out perio d. Data
Polling bit DQ7 returns '0' while the erasure is in
progress and '1' when it has completed. The Tog­gle bit DQ6 toggles during the erase operation,
and stops when erase is com pleted.

After c ompletion the Status Register bit DQ5 re­turns '1' if there has been an erase failure. In such
a situation, the Toggle bit DQ2 ca n be used to de­termine which block is not correctly eras ed. In the

case of erase failure, a Read/Reset RD instruction
is necessary in order to reset the P/E.C.

Bank Erase (BKE) Instruction. This instruction
uses six write cycles and is use d to erase all the
blocks belonging to the selected bank. The Er as e
Set-up command 80h is written to address 555h
on the third cycle after the two Coded cycles. The
Bank Erase Confirm command 10h is similarly
written on the sixth cycle after another two Coded
cycles at an address w ithin the sel ec ted bank. If
the second command given is not an erase con­firm or if the C oded cycles are wrong, t he instruc­tion aborts and the device is reset to Read Array.
It is not necessary to program the array with 00h
first as the P/E.C. will automatically do this before
erasing it t o FF h. Read operations within the same
bank after the sixth rising edge of WF

or EF output
the Status Register bits. During the execution of
the erase by the P/E.C., Data Polling bit DQ7 re­turns '0', then '1' on completion. The Toggle bit
DQ6 toggles during erase operation and stops
when erase is completed. A fter completion the
Status Register bit DQ5 returns '1' if there has
been an Erase Failure.

Erase Suspend (ES ) Instruction. In a dual bank
memory the Erase Suspend instruction is used to
read data within the bank where erase is in
progress. It i s also possibl e to program data in
blocks not being erased.

The Erase Sus pend instruction consists of writing
the command B0h without any specific address.
No Coded Cycles are required. Erase suspend is
accepted only during the Block Erase i nstruction
execution. The Toggle bit DQ6 stops toggling
when the P/E.C. is suspended within 15µs after
the Erase Suspend (ES) command has been writ­ten. The dev ice will then automatically be set to
Read Memory Array mode. When erase is sus­pended, a Read from bl oc ks being erased will out­put DQ2 toggling and DQ6 at '1'. A Read from a
block not being erased ret urns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instruc­tions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in DQ6 toggling when the data
is being programmed.

Erase Resume (ER) Instruction. I f an Erase
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at an address within the bank be­ing erased and without any Coded Cycle.

13/46

M36DR432C, M36DR432D

Table 14. Protection States

(2)

Current State
(WP, DQ1, DQ0)

Program/Erase

Allowed

(1)

Next State After Event

(3)

Protect Unprotect Lock WP transition

100 yes 101 100 111 000
101 no 101 100 111 001

110 yes 111 110 111 011

111 no 111 110 111 011
000 yes 001 000 011 100
001 no 001 000 011 101

011 no 011 011 011

Note: 1. Allblocks are protected at power-up, so the defaultconfiguration is 001 or 101 according to WPF status.

2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by
DQ1(=1foralockedblock)andDQ0(=1foraprotectedblock)asreadintheAutoselectinstructionwithA1=V

3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WPF
changed its logic value.

4. A WPF

Table 15. Instructions

transition to VIHon a locked block will restore the previous DQ0 value, giving a 111 or 110.

(1,2)

111 or 110

andA0=VIL.

IH

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.

RD

Read/Reset

(4)

Memory Array

(3)

Addr.

1+

Data F0h
Addr. 555h 2AAh 555h

3+

Data AAh 55h F0h

X

Read Memory Array until a new write cycle is initiated.

Read Memory Array until a new
write cycle is initiated.

Addr. 55h

RCFI CFI Query 1+

Read CFI data until a new write cycle is initiated.

Data 98h
Addr. 555h 2AAh 555h Read electronic Signature or

AS

(4)

Auto Select 3+

Configuration

CR

Register Write

Data AAh 55h 90h

Addr. 555h 2AAh 555h

4

Block Protection or Configuration
Register Status until a new cycle
is initiated.

Configura­tion Data

Data AAh 55h 60h 03h

(4)

has

PG Program 4

DPG

EBY

Double Word
Program

Enter Bypass
Mode

14/46

Addr. 555h 2AAh 555h

Data AAh 55h A0h

Addr. 555h 2AAh 555h

5

Data AAh 55h 40h

Addr. 555h 2AAh 555h

3

Data AAh 55h 20h

Program
Address

Program

Data

Program

Address 1

Program

Data 1

Read Data Polling or
Toggle Bit until
Program completes.

Program

Address 2

Note 6, 7

Program

Data 2