SGS Thomson Microelectronics M34C02-W, M34C02-R, M34C02-L Datasheet
FEATURES SUMMARY
■ Software Data Protection for lower 128 bytes
■ Two Wire I
■ 100kHz and 400kHz Transfer Rates
■ Single Supply Voltage:
2
C Serial Interface
– 2.5 to 5.5V up to 400kHz for M34C02-W
– 2.2 to 5.5V up to 400kHz for M34C02-L
– 1.8 to 5.5V up to 100kHz for M34C02-R
– 1.7 to 3.6V up to 100kHz for M34C02-F
■ BYTE and PAGE WRITE (u p to 16 by te s)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Tim e d P rogramming Cyc le
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Protection
■ More than 1 Million Erase/Write Cycles
■ More than 40 Year Data Retention
M34C02
2 Kbit Serial I²C Bus EEPROM
For DIM M Serial P resence Detect
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
VFDFPN8 (MM)
2x3mm² (MLP)
TSSOP8 (DW)
169 mil width
TSSOP8 (DS)
3x3mm² body size (MSOP)
1/26July 2003
M34C02
SUMMARY DESCRIPTION
The M34C02 is a 2 Kbit serial EEPROM memory
able to lock permanently the data in its first half
(from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs
(dual interline memory modules) with Serial
Presence Detect. All the information concerning
the DRAM module configuration (such as its
access speed, its size, its organization) can be
kept write protected in the first half of the memory.
This bottom half of the memory area can be writeprotected using a specially designed software
write protection mechanism. By sending the
device a specific sequence, the first 128 bytes of
the memory become permanently write protected.
Care must be taken w hen us i ng this s equence as
its effect cannot be reversed. In addition, the
device allows the entire m emory area to be write
protected, using the WC input (for example by
tieing this input to V
2
These I
C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 256x8 bits.
Figure 2. Logic Diagram
CC
).
Device Select Code and RW
bit (as described in
Table 2), terminated by an acknowledge bit.
When writing data to the memory, the memory
inserts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.
Figure 3. DI P, SO, TSSOP and VF D FPN Connections (Top View)
M34C02
1
E0 V
2
3
E2
4
SS
8
7
6
5
AI01932C
CC
WCE1
SCL
SDAV
V
CC
3
E0-E2 SDA
SCL
WC
2
C uses a tw o wire serial i nterface, comprising a
I
M34C02
V
SS
AI01931
bi-directional data line and a clock line. The device
carries a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
2
C bus definition to
access the memory area and a second Device
Type Identifier Code (0110) to access the
Protection Register. These codes are used
together with three chip enable inputs (E2, E1, E0)
so that up to eight 2 Kbit devices may be attached
to the I²C bus and selected individually.
The device behaves as a slave device in the I
2
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, gene rated by the
bus master. The START condition is followed by a
Note: 1. Se e the pages after page 19 for package dimens ions,
and how to ide ntify pin-1.
Table 1. Signal Names
E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC
V
CC
V
SS
Power On Reset: V
Write Control
Supply Voltage
Ground
Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
Write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
has reached the POR
CC
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
drops from the operating
CC
voltage, below the POR threshold value, all
operations are disabled and the device will not
C
respond to any command.
A stable and valid V
(as defined in Tables 6 to
CC
9) must be applied before applying any logic
signal.
2/26
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to V
. (Figure 4
CC
indicates how the valu e of the p ull-up resistor c an
be calculated). In most applications, thoug h, this
method of synchronization is no t employed, and
so the pull-up resistor is not necessary, provided
that the bus maste r has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
CC
. (Fig-
M34C02
ure 4 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
inputs must be t ied t o V
Device Select Code.
Write Control (WC
)
This input signal is provided for protecting the contents of the whole memory from inadvertent write
operations. Write Cont rol (WC
(when driven Low) or disable (when driven High)
write instructions to the entire memory area or to
the P rotecti on Regi ster.
When Write Control (WC
unconnected, the write protection of the first half of
the memory is determined by the status of the
Protection Register.
or VSS to establish the
CC
) is used to ena ble
) is tied Low or left
Figure 4. Maximum R
20
16
12
8
Maximum RP value (kΩ)
4
0
10 1000
Value versus Bus Capacitance (C
L
fc = 100kHz
fc = 400kHz
100
C
(pF)
BUS
) for an I2C Bus
BUS
MASTER
V
CC
R
SDA
SCL
R
C
BUS
L
C
BUS
AI01665
L
3/26
M34C02
Figure 5. I2C Bus Protocol
SCL
SDA
SCL
SDA
SCL
SDA
START
Condition
START
Condition
1 23 789
MSB
1 23 789
MSB ACK
SDA
Input
SDA
Change
STOP
Condition
ACK
STOP
Condition
AI00792B
Table 2. Device Select Code
Device Type Identifier
b7
Memory Area Select
Code (two arrays)
Protection Register
Select Code
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are com pared against the respective ext ernal pins on th e m em ory device.
1010E2E1E0RW
0110E2E1E0RW
b6 b5 b4 b3 b2 b1 b0
4/26
1
Chip Enable Address
2
RW
M34C02
DEVICE OPERATION
2
The device supports the I
C protocol. This is s ummarized in Figure 5. Any device that sends data on
to the bus is defined to be a transmitter, a nd any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, w h ic h will also provide the s er ial clock fo r
synchronization. The memory d evice is always a
slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The devi ce continuously
monitors (except duri ng a Write cycle ) Se ri a l Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is give n.
Stop Condition
Stop is identified by a rising edg e of Serial Data
(SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condi tion to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EEPROM Wr ite cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
th
clock pulse period, the receiver pulls Serial
9
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change
only
when Serial Clock (SCL) is driv-
en Low.
Memory Addressing
To start communication betwee n the bus master
and the slave device, the bus mas ter mus t initiate
a Start condition. Following this, t he bus master
sends the Device Select Code, shown in Tabl e 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, t he 4bit Device Type Identifier is 1010b; to address the
Protection Register, it is 0110b.
Up to eight memory devices can be connected on
a single I
2
C bus. Each one is given a uniq ue 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the
device only responds if the Chip E nable Address
is the same as the value on the Chip Enable (E0,
E1, E2) inputs.
th
The 8
bit is the Read/Write bit (RW). This bi t is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code , the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9
th
bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Standby mode.
Table 3. Operating Modes
Mode RW bit
Current Address Read 1 X 1 START, Device Select, RW
Random Address Read
Sequential Read 1 X
Byte Write 0 V
Page Write 0 V
Note: 1. X = V
IH
or V
.
IL
0X
1 X reSTART, Device Select, RW
WC
1
IL
IL
Bytes Initial Sequence
1
1 Similar to Current or Random Address Read
≥
1 START, Device Select, RW = 0
16 START, Device Select, RW
≤
START, Device Select, RW
= 1
= 0, Address
= 1
= 0
5/26
M34C02
Figure 6. Setting the Write Protection Register (WC = 0)
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
START
BYTE
Setting the Software Write-Protection
The M34C02 has a hardware write-protection
feature, using the Write Control (WC
) signal. This
signal can be driven High or Low, and must be
held constant for the whole instruction sequence.
When Write Control (WC
) is held Low, the whole
memory array (addresses 00h to FFh) is write
protected. When W r ite Control (WC
) is held High,
the write protection of the memory array is
dependent on whether software write-protection
has been set.
Software write-protection allows the bottom half of
the memory area (addresses 00h to 7Fh) to be
permanently write protected irrespective of
subsequent states of the Write Control (WC
signal.
WORD
ADDRESS
ACK
VALUE
(DON'T CARE)
DATA
ACK
VALUE
(DON'T CARE)
STOP
ACK
AI01935B
The write protection feature is activated by writing
once to the Protection Register. The Protection
Register is accessed with the device select code
set to 0110b (as shown in Table 2), and the E2, E1
and E0 bits set according to the states being
applied on the E2, E1 and E0 signals. As for any
other write command, Write Control (WC
be held Low. Address and data bytes must be sent
with this command, but their values are all ignored,
and are treated as Don’t Care. Once the
Protection Register has been written, the write
protection of the first 12 8 bytes o f the memory is
enabled, and it is not pos sible to unprotect t hese
128 bytes, even if the device is powered off and
on, and regardless the state of Write Control (WC
)
When the Protection Register has been written,
the M34C02 no longer responds to the device type
identifier 0110b in either read or write mode.
) needs to
).
Figure 7. Result of Setting the Write Protection
FFh
80h
7Fh
00h
6/26
Memory
Area
Standard
Array
Standard
Array
Default EEPROM memory area
state before write access
to the Protect Register
Standard
Array
Write
Protected
Array
State of the EEPROM memory
area after write access
to the Protect Register
FFh
80h
7Fh
00h
AI01936C
Figure 8. Write Mode Sequences in a Non Write-Protected Area
ACK ACK ACK
M34C02
BYTE WRITE DEV SEL BYTE ADDR
START
PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2
START
ACK ACK
DATA IN N
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW
bit rese t to 0 .
The device acknowledges this, as shown in Figure
8, and waits f or an address byte. Th e device responds to the address byte with an acknowle dge
bit, and then waits for the data byte.
When the bus mast er generates a Stop con dition
immediately after the Ack bi t (in t he “10
th
bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Da ta (SDA)
and Serial Clock (SCL) are ignored, and the device does not respond to any requests.
Byte Write
After the Device Select Code and the address
byte, the bus mast er sends one data byte. If the
addressed location is hardware write-protected,
the device replies to the data byte with NoAck, and
the location is not modified. If, instead, the addressed location is not Write-protected, the device
DATA IN
R/W
ACK ACK ACK
R/W
STOP
STOP
AI01941
replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown
in Figure 8.
Page Write
The Page Write mode allows u p to 16 by tes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant m emory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘ r ollover’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends fr om 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC
) is Low. If the addressed location is hardware write-protected, the device replies
to the data byte with NoAck, and the locations are
not modified. After each byte is transferred, the internal byte address counter (the 4 least significant
address bits only) is incremented. Th e transfer is
terminated by the bus master generating a Stop
condition.
7/26
M34C02
Figure 9. Wri te Cy cle Pol l in g Fl owchart using AC K
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
NO
Returned
First byte of instruction
with RW = 0 already
decoded by the device
ReSTART
STOP
YES
Next
Operation is
Addressing the
Memory
DATA for the
WRITE Operation
Continue the
WRITE Operation
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (t
) is shown in Tables
w
16 and 17, but the typical time is shorter. To make
use of this, a polling sequence can be used by the
bus master.
The sequence, as shown in Figure 9, is:
– Initial condition: a Write cycle is in progress.
YESNO
Send Address
and Receive ACK
START
Condition
YESNO
DEVICE SELECT
with RW = 1
Continue the
Random READ Operation
AI01847C
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
8/26
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