SGS Thomson Microelectronics M34116C1, M34116B1 Datasheet

AND TONE GENERATION CIRCUIT

HW ANDSW COMPATIBLEWITH M116
1 TO 64 SERIAL CHANNELS PER FRAME

(CONTROLLEDBY SYNC SIGNAL PERIOD)
29 MAXIMUMCONFERENCES
1 TO 64 SERIAL CHANNELS PER CONFER-

ENCES
3 SIMULTANEOUS OPERATION MODES

AVAILABLE:
CONFERENCE, TRANSPARENT AND TONE
GENERATION

TYPICALBIT RATES:
1536/1544/2048/4096Kbits/s

COMPATIBLE WITH ALL KINDS OF PCM
FORMAT

µ ANDA LAW (PINPROGRAMMABLE)
EQUALPRIORITYTO EVERY CHANNEL
ONE FRAME AND ONE CHANNEL DELAY

FROMSENDINGTO RECEIVING
OVERFLOWINFORMATIONFOR EACHCON-

FERENCE BY PIN OS (OVERFLOW SIGNAL­LING) AND ON DATA BUS ON MPU RE­QUEST

INSTRUCTION SET COMPATIBLEWITH M3488
PROGRAMMABLE INPUT AND OUTPUT AT-

TENUATION OR GAIN FROM 0 TO 15dB
WITHSTEP OF 1dB FOR EACH CHANNEL

TONE GENERATION FROM 3.9Hz TO
3938HzWITH MIN. STEP OF 3.9Hz

TOTAL OF 7 DIFFERENT TONE OUTPUTS
IN PARALLEL PROGRAMMABLE VIA MPU
(MAXIMUM 4 DIFFERENT FREQUENCIES
ANDDURATIONS)

1 MELODY OF MAXIMUM 32 PROGRAMMA­BLE FREQUENCIES AND DURATIONS

5V POWER SUPPLY
TTL COMPATIBLE INPUT LEVELS,

CMOS/TTL COMPATIBLEOUTPUTLEVELS
MAIN INSTRUCTIONS CONTROLLED BY MI-

CROPROCESSORINTERFACE:
– Channelconnectionto a conference
– Channelattenuation or gain
– Channeldisconnectionfromboth conference

andtransparentmodes
– Tone and melody generation
– Overflowstatus
– Operatingmode
– Channelstatus

M34116

PCM CONFERENCECALL

PRELIMINARY DATA

DIP24

ORDERING NUMBER: M34116B1

PLCC28

ORDERING NUMBER: M34116C1

DESCRIPTION

The M34116 is a productspecificallydesignedfor
applications in PCM digital exchanges. It is able
to handle up to 64 channels in any conferences
combination from 1 to 29 conferences in parallel
and to generate seven different tones and one
melody.

Theparties in a conferencemust previouslybeal­located through the Digital Switching Matrix
(M3488) in a single serial wire at M34116 PCM
input (IN PCMpin).

The M34116 is full pin and function compatible
with the M116. In addition, it has the capabilityto
generatetone directly coded in PCM.

For the conference function, each channelis con­verted inside the chip from PCM law to linear law
(14 bits). Then it is added to its conference, and
the sample of the previous frame is subtracted
fromthe conference.
In this way a new conferencesum signal is gener­ated.
The channel output signal will contain the infor­mation of all the other channels in its conference
exceptits own.

After the PCM encoding, the data is serialized by
the M34116 in the same sequence as the PCM
input frame, with one frame (plus one channel)
delayand will be reallocated by the DSM (M3488)
at the final channel and bus position.

A programmable attenuation or gain can be set
on each channel and for every function: confer­ence, tone generationand transparentmode.

January1995

This is advanced information on anew product now in development or undergoing evaluation. Details are subject to change without notice.

1/23

M34116

PIN CONNECTIONS (Topview)

DIP24

PLCC28

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

(*) Supply Voltage – 0.3 to 7 V

V

DD

V

V

O (off)

P

T

T

Stresses above those listed under ”Absolute Maximum Ratings” may causes permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in theoperational sectionsof this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Input Voltage – 0.3 to V

i

DD

Off State Output Voltage – 0.3 to 7 V
Total Power Dissipation 500 mW

tot

Storage Temperature – 65 to 150 °C

stg

Operating Temperature 0 to 70 °C

op

Figure1: PCMConference Call InsertionScheme

2/23

PINDESCRIPTION

M34116

DIP

N

PLCC

o

o

N

Pin Function

1 2 TD M116 operating mode only. Tone Duration input pin. When TD = 1, a PCM coded tone

(instead of PCM data) is sent out to all channels enabled by the IT bit. TD is latched by
the SYNC signal so that all channels have the same tone during the same number of
frames. TD = 0 fornormal operation.

2 3 TF M116 operating mode only. Tone Frequency input pin. When TF = 1, the tone amplitude

is high. When TF = 0, the tone amplitude is low. TF is latched by SYNC. The PCM coded
tone level corresponds to 1/10 of the full scale. For M34116 operating mode: Melody
waveform select input pin. When TF = 1, the PCM output of the melody represents a
square wave. When TF = 0, it represents a sine wave. In both cases, the rms level is the
same and is equal to – 6 dBm0 if no attenuation or gain is programmed.

3 4 RESET Master reset input pin. This pin is active low and must be used at the very beginning after

power up to initialize the device or when switching from A law to Mu law. The Internal
initialization routine takes 2 time frames starting from the rising edge of RESET. During
thisinitialization time, all data bus and PCM output are pulled to a high impedance state.

4 5 OS Overflow Signalling output pin. When OS = 0 one conference is in overflow. This signal is

anticipated over halftimeslot with respect to the output channel involved in the conference in
overflow. Example: if output channel 4 is one of the parties of one conference in
overflow, OS = 0 during the second half of the time slot corresponding to output channel 3
andduring the firsthalf of thetime slot corresponding to output channel 4.

5 6 OUT

PCM

PCM output pin. The bit rate is 4096Kbits/s max. The sign bit is the first bit of the serial
sequence. The first bit of the first channel is found at the rising edge of the CLOCK signal
preceding the rising edge of the SYNC signal. The output buffer is open drain to allow for
multiple connections.

6to13 7,

9 to 11,

13 to 16

D0 toD7Bidirectional Data bus pins. Data and instructions are transferred to or from the

microprocessor. D0 is the Least Significant Bit. The bus is tristate when RESET is low

and/orCS is high.
14 17 VDD +5V Supply input. 100nF decoupling capacitor recommended.
15 18 C/D Control Data input pin. In a write operation C/D = 0 qualifies any bus content as data

while C/D = 1 qualifies it as an opcode. For M116 operating mode only: in a read

operation, the overflow information of the first eight conferences is selected by C/D = 0,

the overflow of the last two conferences andthe status by C/D = 1.
16 19 CS Chip Select input pin. When CS = 0, data and instructions can be transferred to or from

the external microprocessor and when CS = 1 the data bus is in tristate.
17 20 RD Read control input pin. When RD = 0, read operation is performed. When match

conditions for the opcode exists, data is transferred to the external microprocessor on the

fallingedge of RD.
18 21 WR Write control input pin. Instructions and opcode from the external microprocessor are

latchedon the rising edge of WR.
19 23 SYNC Synchronization input pin. The rising edge of CLOCK preceding the rising edge of SYNC

corresponds to the first bit of the first channel except for PCM frame of 1544Kbits/s. In

thiscase, it corresponds to the Extra bit (193th).
20 24 CLOCK Master Clock input pin. Typ.operating Frequencies are:

3.072MHz for 24 PCM channels frame (192 bit/frame)

3.088MHz for 24 PCM channels frame with extra bit (193 bit/frame)

4.096MHz for 32 PCM channels frame (256 bit/frame)

8.192MHz for 64 PCM channels frame (512 bit/frame)
Both M34116 an M116 operating modes are possible up to 4.096MHz.
At 8.192MHz only M34116 operating mode is possible.

21 25 EC External Clock output pin. This pin provides the master clock for the Digital Switching

Matrix (M3488). Normally it is the same signal as applied to the CLOCK input (pin 20).
When the Extra bit is selected with the instruction 5, the first two periods of the master
clock are canceled in order to allow the operation of the M34116 and the DSM with PCM
frame with Extra bit (e.g.193 bit/frame with PCM I/O of 1544Kbits/s).

22 27 IN PCM PCM input pin. The max bit rate is 4096Kbits/s. The first bit of the first cahnnel is found at

the second rising edge of the CLOCK signal following the rising edge of the SYNC signal.
If Extra bit is selected, then the firstbit is shifted by two CLOCK periods.

23 28 A/MU A Lawor MU Lawselectpin. WhenA/MU=1, A Lawisselected. WhenA/MU= 0, MULawis

selected. The law selection must be done before initializing thedevice using the RESET pin.

24 1 Vss Ground.

3/23

M34116

RECOMMENDED OPERATINGCONDITIONS

Symbol Parameter Value Unit

V

CC

V

i

V

O

CLOCK Freq. Input Clock Frequency 3.072/3.088

SYNC Freq. Input Synchronization Frequency 8 KHz

T

op

CAPACITANCES (measurementsfrequency= 1MHz; 0 to 70°C; unusedpins tied to VSS)

Symbol Parameter Pin (**) Min. Typ. Max. Unit

C

I

C

I/O

C

O

SupplyVoltage 4.75 to 5.25 V
Input Voltage 0 to 5.25 V
Off State Output Voltage 0 to 5.25 V

4.096 / 8.192 (*)

Operating Temperature 0 to 70 °C

Input Capacitance 1 to 3; 15 to 20; 22 to 23 5 pF
I/O Capacitance 6 to 13 15 pF
Output Capacitance 4, 5, 21 10 pF

MHz
MHz

ELECTRICALCHARACTERISTICS (Tamb = 0 to 70°C, VCC=5V±5%)
AllDC characteristicare valid 250µs after V

Symbol Parameter Pins (**) Test Condition Min. Typ. Max. Unit

V

IL

V

IH

V

T–

V

T+

V

HY

V

OL

V

OH

V

OL

I

IL

I

OL

I

CC

(*) Only in M34116 Operating Mode.
(**) Pin numbersreferred to the DIP24.
(***) Schimitt-trigger inputs.

Input Low Level 1 to 3

15 to 20
22 to 23

Input High Level 1 to 3

15 to 20
22 to 23

Negative Threshold

6 to 13 (***) VCC= 5V 0.6 0.9 1.1 V

Voltage
Positive Threshold

6 to 13 (***) VCC = 5V 1.5 1.7 2 V

Voltage
Hysteresis 6 to 13 (***) VCC= 5V 0.4 0.8 V
Output Low Level 4,6 to 13,21 IOL= 2mA 0.4 V
Output High Level 4 to 13, 21 IOH = 1mA VCC-0.4 V
Output Low Level 5 IOL = 4.1mA 0.4 V
Input Leakage Current 1 to 3

6to13
15 to 20
22 to 23

Data Bus Leakage

6to13 VIN= 0 to V

Current
Supply Current 14 Clock Freq. = 4.096MHz 50 mA

andclock have been applied.

CC

V

= 0 to V

IN

CS = V

CC

CC

CC

– 0.3 +0.8 V

2.0 V

CC

10 µA

±10 µA

V

4/23

M34116

ELECTRICALCHARACTERISTICS (Tamb = 0 to 70°C, VCC=5V±5%)

All DC characteristic are valid 250µs after V
load and R

Signal Symbol Parameter Test Condition Min. Typ. Max. Unit

CK

Up to

4.096MHz

CK

8.192MHz

SYNC t

PCM
Input

PCM

Output

(Open

drain)

RESET t

WR t

RD t

Notes:

1. With Extra Bit operatingmode insert this time becomes 3 t

2. With Extra Bit operatingmode insert these times are 80ns longer.

3. With OPCODE (C/D = I), this time becomes 4tck (6tck if E = 1). E: extra bit indication in”operating mode” instruction.

4. For tone generation instruction, this time becomes 4tck (6tck if E =1) E: extra bit indication in ”operating mode” instruction.

5. With extra bit operating mode insert, this time becomes 6tck.

6. The initialization routine takes2 frames time starting from the rising edge of RESET - Anyaccess to the device should take place after the
initialization routine is completed. (2 frames time).

the test pull up resistor.

L

t

CK

t

WL

t

WH

t

R

t

F

t

CK

t

WL

t

WH

t

R

t

F

SL

t

HL

t

SH

t

WH

t

S

t

H

t

PD min.

Clock Period
Clock Low Level Width
Clock High Level Width
Rise Time
Fall Time

Clock Period
Clock Low Level Width
Clock High Level Width
Rise Time
Fall Time

Low Level Set-up Time
Low Level Hold Time
High Level Set-up Time
High Level Width

Set-up Time
Hold Time

Propagation Time Low
Level referred to CK

t

PD max.

Propagation Time High
level Referred to CK

t
t

t

t

t

REP

SL
HL

SH

WH

WL

WH

Low Level Set-up Time
Low Level Hold Time
High Level Set-up Time
High Level Width

Low Level Width
High Level Width
Repetition interval
between active pulses.

t

SH

High Level st-up time to
active read strobe.

t

HH

High Level hold time to
active read strobe.
Rise Time
Fall Time

Low Level Width
High Level Width
Repetition interval

t

t

REP

t
t

WL

WH

R

F

between active pulses.

t

SH

High Level st-up time to
active read strobe.

t

HH

High Level hold time to
active read strobe.

t

R

t

F

Rise Time
Fall Time

and clock have been applied. CLis the max. capacitive

CC

230
100
100

25
25

120

50
50

10
10

See note 1 30

30
30

t

CK

35
35

CL = 50pF RL=1KΩ 40

180

note 6 50

30
30

t

CK

150
200

note 3 and 4

500

0

20

60
60

180
200

note 5

4t

CK

0

20

60
60

.

CK

ns
ns
ns
ns
ns

ns
ns
ns
ns
ns

ns
ns
ns
ns

ns
ns

ns

ns

ns
ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns

ns
ns

ns
ns
ns

ns

5/23

M34116

ELECTRICALCHARACTERISTICS (continued)

Signal Symbol Parameter Test Condition Min. Typ. Max. Unit

CS

CD

OS t

EC t

TD/TF t

D0 to D7
(interface

bus)

t

SL (CS-WR)

t

HL (CS-WR)

t

SH (CS-WR)

t

HH (CS-WR)

t

SL (CS-RD)

t

HL (CS-RD)

t

SH (CS-RD)

t

HH (CS-RD)

t

S(C/D-WR)

t

H(C/D-WR)

t

S(C/D-RD)

t

H(C/D-RD)

PD(OS)

PD(EC)

S

t

H

t

S(BUS-WR)

t

H(BUS-WR)

Low level set-up time
to WR falling edge.
Low Level hold time from
WR rising edge.
High level set-up time to
WR falling edge.
High level hold time from
WR rising edge.
Low level set-up time
to RD falling edge.
Low Level hold time from
RD rising edge.
High level set-up time to
RD falling edge.
High level hold time from
RD rising edge.

Set-up time to write strobe
end.
Hold time from write
strobe end.
Set-up time to read strobe
start.
Hold time from read
strobe end.

Propagation time from
risingedge of CK.

Propagation time referred
to CK edges.

Set-up
Hold Time

Input set-up time to write
strobe end.

Input hold time from write
strobe end.

Active Case
Active Case
Inactive Case
Inactive Case
Active Case
Active Case
Inactive Case
Inactive Case

CL= 50pF 100 ns

CL= 50pF 30 ns

0

20

0

20

0
0
0
0

130

25
20
25

80
40

130

25

ns
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns
ns

ns
ns

ns

ns

t

PD(BUS)

Propagation time from
(active) falling edge of
read strobe.

t

HZ(BUS)

Propagation time from
(active) rising edge of
read strobe to high
impedance state.

A.C. TESTING, OUTPUT WAVEFORM

A.C. testing inputs are driven at 2.4V for a logic ”1” and 0.45V for a logic ”0”,timing

measurementare made at 2.0V for a logic ”1” and 0.8V for a logic ”0”.

6/23

CL = 200pF

120

80

ns

ns

Figure2: InsertionSchema of M34116in a 480 x 480 Non-BlockingDigital Switching Matrix

M34116

Figure3: Block Diagram

EC RESET

CLOCK

SYNC

IN PCM

TIMING

SR

FRAME

RAM

POWER

10

14

8

OS A/MU CS WR C/D RD

MPU INTERFACE

PCM

to

LOG LIN

14

ADDER

19

TONE

ROM

LIN

to

PCM

TONE

CONTROL

19

CONF

RAM

SR

DB(7:0)

TF

TD

OUT PCM

D94TL130

7/23