SGS Thomson Microelectronics M28C64C Datasheet

FASTACCESSTIME:150ns
SINGLE 5V±10%SUPPLYVOLTAGE
LOW POWERCONSUMPTION
FASTWRITE CYCLE
– 32 BytesPage Write Operation
– Byte or Page Write Cycle: 5ms
ENHANCEDENDOF WRITEDETECTION
– Ready/BusyOpenDrain Output

(for M28C64C product only)
– Data Polling
– ToggleBit
PAGELOAD TIMERSTATUS BIT
HIGH RELIABILITYSINGLE POLYSILICON,

CMOSTECHNOLOGY
– Endurance>100,000Erase/WriteCycles
– Data Retention >40 Years
JEDECAPPROVED BYTEWIDEPIN OUT

M28C64C

M28C64X

64 Kbit (8Kb x8) Parallel EEPROM

28

1

PDIP28 (P) PLCC32 (K)

28

1

SO28 (MS)

300 mils

TSOP28 (N)

8 x13.4mm

DESCRIPTION

The M28C64C is an 8 Kbit x8 low power Parallel
EEPROM fabricated with STMicroelectronics pro­prietary single polysilicon CMOS technology.The
device offers fast access time with low power dis­sipationandrequiresa 5Vpower supply.

The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
andsoftwarehandshakingmodewith Ready/Busy,
Data Polling and Toggle Bit. The M28C64C sup­ports32 byte page write operation.

Table1. SignalNames

A0 - A12 Address Input
DQ0 - DQ7 Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
RB Ready / Busy
V

CC

V

SS

Supply Voltage
Ground

Figure1. Logic Diagram

V

CC

13

A0-A12

W

E

G

M28C64C

V

SS

8

DQ0-DQ7

RB

AI00746B

February 1999 1/15

M28C64C, M28C64X

Figure2A. DIP Pin Connections

RB V

1

A12

2

A7

3

A6

4

A5

5

A4

6

A3

7
A2
A1
A0

DQ0

DQ2

SS

Warning: DU = Don’t Use.

M28C64C

8

9

10

11

12

13

14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI00747C

Figure2C. SO Pin Connections

CC

W
DU
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

Figure2B. LCC Pin Connections

CC

DU

DU

32

W

V

A8
A9
A11
NC
G

25

A10
E
DQ7
DQ6

DQ4

DQ5

AI00748D

RB

A7

A12

A6
A5
A4
A3
A2

9
A1
A0

NC

DQ0

DQ1

Warning: NC = Not Connected, DU = Don’tUse.

1

M28C64C

17

SS

V

DQ2DUDQ3

Figure2D. TSOP Pin Connections

RB

A12

DQ0
DQ1
DQ2

V

SS

Warning: DU = Don’t Use.

A7
A6
A5
A4
A3
A2
A1
A0

1
2
3
4
5
6
7

M28C64C

8
9
10
11
12
13
14

AI00876C

V

28
27
26
25
24
23 A11
22
21
20
19
18
17
16
15

CC

W
DU
A8
A9

G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3

PIN DESCRITPION
Addresses (A0-A12).

The address inputs select
an 8-bit memory location during a read or write
operation.

G

22

A11

A9
A8

DU

W

V

CC

RB

A12

Warning: DU = Don’t Use.

Chip Enable (E).

28

M28C64C

1

A7
A6
A5
A4
A3

78

The chip enable input must be

21

15
14

AI01016D

A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2

lowto enableall read/writeoperations.WhenChip
Enableis high,powerconsumptionis reduced.

OutputEnable (G).

The Output Enableinput con­trols the data outputbuffersand is usedto initiate
readoperations.

2/15

M28C64C, M28C64X

Table2. Absolute MaximumRatings

Symbol Parameter Value Unit

T

T

STG

V

CC

V

IO

V

V

ESD

Note:

Except for the rating ”Operating Temperature Range”, stressesabove those listed in the Table ”Absolute Maximum Ratings”may
cause permanent damage to thedevice. These are stressratings only andoperation of thedevice at these or any other conditions above
those indicated in theOperating sections of this specification is not implied. Exposure toAbsolute Maximum Rating conditions for extended
periods mayaffect device reliability.Refer also to the STMicroelectronics SURE Program and otherrelevant quality documents.

Ambient OperatingTemperature – 40 to 125 °C

A

Storage TemperatureRange – 65 to 150
Supply Voltage – 0.3 to 6.5 V
Input/Output Voltage – 0.3 to VCC+0.6 V
Input Voltage – 0.3 to 6.5 V

I

Electrostatic Discharge Voltage (Human Body model) 2000 V

C

°

Table3. OperatingModes

Mode E G W DQ0 - DQ7

Read V
Write V
Standby / Write Inhibit V
Write Inhibit X X V
Write Inhibit X V
Output Disable X V

Note:

X=V

or V

IH

IL

IL

IL

IH

V

IL

V

IH

X X Hi-Z

IL

IH

V

IH

V

IL

IH

X Data Out or Hi-Z
X Hi-Z

Data Out

Data In

Data Out or Hi-Z

DataIn/Out(DQ0-DQ7).

Datais writtentoorread

fromthe M28C64CthroughtheI/Opins.

WriteEnable(W).

TheWriteEnable inputcontrols

the writingof data to theM28C64C.

Ready/Busy (RB).

Ready/Busyis an open drain
output that can be used to detect the end of the
internalwrite cycle.

OPERATION

Inorderto prevent data corruptionandinadvertent
write operations during power-up, a Power On
Reset(POR)circuitresetsallinternalprogramming
cicuitry. Access to the memory in write mode is
allowedaftera power-upasspecifiedin Table6.

Read

The M28C64C is accessed like a static RAM.
When E and G are low with W high, the data
addressed is presented on the I/O pins. The I/O
pinsarehighimpedancewheneitherGor Eis high.

Write

Writeoperations are initiated when both W and E
arelow andG is high.TheM28C64Csupportsboth
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurslast andthe Data on the rising edge of E or
W which ever occursfirst. Once initiated the write
operationis internallytimed until completion.

Page Write

Page write allows up to 32 bytes to be consecu­tively latched into the memory prior to initiating a
programming cycle. All bytes must be located in a
single pageaddress, that is A5 - A12 mustbe the
samefor all bytes.The page writecan beinitiated
duringany bytewrite operation.

Following the first byte write instruction the host
may sendanotheraddressand dataup to a maxi­mumof 100µsaftertherisingedgeof EorW which
ever occurs first (t

). If a transition of E or W is

BLC

not detected within 100µs, the internal program­ming cyclewill start.

3/15

M28C64C, M28C64X

Figure3. Block Diagram

RB E G W

A5-A12

(Page Address)

A0-A4

VPPGEN RESET

ADDRESS

LATCH

ADDRESS

LATCH

Y DECODE

X DECODE

ATD & CONTROL LOGIC

64K ARRAY

SENSE AND DATA LATCH

I/O BUFFERS

DQ0-DQ7

PAGE

LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING

AI00877C

MicrocontrollerControl Interface

TheM28C64Cprovidestwo writeoperation status
bitsandonestatuspin thatcanbe usedtominimize
thesystemwritecycle. Thesesignals areavailable
on the I/O port bits DQ7 or DQ6 of the memory
duringprogrammingcycleonly,or asthe RB signal
on a separate pin.

Figure4. Status Bit Assignment

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

DP = Data Polling
TB = Toggle Bit
PLTS = Page Load TimerStatus

Data Polling bit (DQ7).

During the internal write
cycle, any attempt to read the last bytewritten will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin­ished the true logic value appears on DQ7 in the
readcycle.

4/15

Toggle bit (DQ6).

The M28C64C offers another
way for determining when the internal write cycle
iscompleted.DuringtheinternalErase/Writecycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequentattemptsto
readanyaddressinthe memory.Whenthe internal
cycle is completed the toggling will stop and the
device will be accessible for a new Reador Write
operation.

Page Load Timer Status bit (DQ5). In the Page
Writemode data may be latchedby E or W up to
100µs aftertheprevious byte. Up to 32 bytes may
be input. The Data output (DQ5) indicates the
status of the internal Page Load Timer. DQ5 may
be read by asserting Output Enable Low (t

PLTS

DQ5 Low indicates the timer is running, High
indicates time-out after which the write cycle will
start and no new data may be input.

Ready/Busypin. The RB pin provides a signalat
its open drain output which is low during the
erase/write cycle, but which is released at the
completionof theprogramming cycle.

).

M28C64C, M28C64X

Table4. AC MeasurementConditions

Input Rise and Fall Times

≤

20ns

Figure6. AC TestingEquivalent LoadCircuit

1.3V

Input Pulse Voltages 0.4V to 2.4V
Input and Output Timing Ref. Voltages 0.8V to 2.0V

Note thatOutput Hi-Z isdefined as the point where data is no
longer driven.

Figure5. AC TestingInput Output Waveforms

2.4V

0.4V

Table5. Capacitance

(1)

(TA=25°C, f =1 MHz)

2.0V

0.8V

AI00826

DEVICE
UNDER

TEST

CLincludes JIG capacitance

1N914

3.3kΩ

CL= 30pF

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only,not 100% tested.

Input Capacitance VIN=0V 6 pF
Output Capacitance V

=0V 12 pF

OUT

OUT

AI01129

Table6. Read ModeDC Characteristics

= 0 to70°Cor –40 to 85°C, VCC= 4.5Vto5.5V)

(T

A

Symbol Parameter TestCondition Min Max Unit

I

I

LO

I

CC

I

CC1

I

CC2

V
V

V

V

Note: 1. All I/O’s opencircuit.

Input Leakage Current 0V≤V

LI

Output Leakage Current 0V ≤ VIN≤ V

(1)

Supply Current (TTL and CMOS inputs) E = VIL,G=VIL,f=5MHz 30 mA

(1)

Supply Current (Standby) TTL E= V

(1)

Supply Current (Standby) CMOS E > VCC–0.3V 100
Input Low Voltage – 0.3 0.8 V

IL

Input High Voltage 2 VCC+0.5 V

IH

Output Low Voltage IOL= 2.1 mA 0.4 V

OL

Output High Voltage IOH= –400µA 2.4 V

OH

Table7. PowerUp Timing

(1)

=

(T

0to70°C or–40 to 85°C, V

A

V

≤

IN

CC

CC

IH

= 4.5V to 5.5V)

CC

10
10 µA

2mA

Symbol Parameter Min Max Unit

t

PUR

t

PUW

Note:

1. Sampled only,not 100% tested.

Time Delay to Read Operation 1 µs
Time Delay to Write Operation 10 ms

A

µ

A

µ

5/15