M28C16A
M28C17A
16 Kbit (2Kb x8) Parallel EEPROM
August 1998 1/19
AI02109
11
A0-A10
W
DQ0-DQ7
V
CC
M28C16A
M28C17A
G
E
V
SS
8
RB
Figure1. Logic Diagram
28
1
PDIP28 (BS) PLCC32 (KA)
A0-A10 Address Input
DQ0-DQ7 Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
RB Ready / Busy
V
CC
Supply Voltage
V
SS
Ground
Table1. SignalNames
FASTACCESSTIME:
– 150ns at 5V
– 250ns at 3V
SINGLE SUPPLYVOLTAGE:
–5V±10%forM28C16Aand M28C17A
– 2.7V to 3.6VforM28C16-xxW
LOW POWERCONSUMPTION
FASTWRITE CYCLE
– 32 BytesPage Write Operation
– Byte or Page Write Cycle: 5ms
ENHANCEDENDOF WRITEDETECTION
– Ready/BusyOpenDrainOutput
– Data Polling
– ToggleBit
PAGELOAD TIMERSTATUSBIT
HIGH RELIABILITYSINGLE POLYSILICON,
CMOSTECHNOLOGY
– Endurance>100,000Erase/WriteCycles
– Data Retention >40 Years
JEDECAPPROVED BYTEWIDEPIN OUT
DESCRIPTION
TheM28C16Aand M28C17Aare 2Kx8 low power
ParallelEEPROMfabricatedwithSTMicroelectronicsproprietarysinglepolysiliconCMOStechnology.
The device offers fast access time withlow power
dissipationand requiresa 5V or3V powersupply.
TSOP28 (NS)
8 x13.4mm
28
1
SO28 (MS)
300 mils
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
DU
A10
A8
A9
DQ7
W
NC
G
E
DQ5DQ1
DQ2
DQ3V
SS
DQ4
DQ6
NC
RB V
CC
AI02110
M28C17A
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
28
27
26
25
24
23
22
21
20
19
18
17
Figure2A. DIP Pin Connections
Warning: NC = Not Connected, DU = Don’t Use.
AI02111
DU
A8
A10
DQ4
17
A0
NC
DQ0
DQ1
DQ2NCDQ3
A6
A3
A2
A1
A5
A4
9
W
A9
1
RB or NC
(1)
NC
DQ6
A7
DQ7
32
DU
V
CC
M28C16A
M28C17A
NC
NC
DQ5
G
E
25
V
SS
Figure2B. LCC Pin Connections
Warning: NC = Not Connected, DU = Don’t Use.
Note:
1. Pin 2 is either RB for M28C17Aor NC
for M28C16A.
A1
A0
DQ0
A5
A2
A4
A3
A9
NC
DQ7
A8
G
E
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
DU
W
NC
A6
RB
V
CC
A7
AI02113
M28C16A
28
1
22
78
14
15
21
V
SS
A10
Figure2D. TSOP Pin Connections
Warning: NC = Not Connected, DU = Don’t Use.
DQ0
DQ1
A3
A0
A2
A1
A10
E
DU
DQ7
G
DQ5
V
CC
DQ4
A9
W
A4
RB
A7
AI02112
M28C17A
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
DQ2
V
SS
A6
A5
DQ6
28
27
26
25
24
23 NC
DQ3
1
NC
A8
Figure2C. SO Pin Connections
Warning: NC = Not Connected, DU = Don’t Use.
2/19
M28C16A, M28C17A
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature
(2)
–40to85 °C
T
STG
Storage TemperatureRange – 65 to 150
°
C
V
CC
Supply Voltage – 0.3 to 6.5 V
V
IO
Input/Output Voltage – 0.3 to VCC+0.6 V
V
I
Input Voltage – 0.3 to 6.5 V
V
ESD
Electrostatic Discharge Voltage (Human Body model) 3000 V
Notes:
1. Except for therating ”Operating Temperature Range”, stressesabove thoselistedin theTable ”AbsoluteMaximum Ratings”
may cause permanentdamage to thedevice. Theseare stress ratingsonly and operationof the deviceat these or any other
conditions above those indicated inthe Operatingsections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extendedperiods may affectdevice reliability.Refer also tothe STMicroelectronics SURE Programand other
relevant qualitydocuments.
2. Depends on range.
Table2. AbsoluteMaximum Ratings
(1)
Mode E G W DQ0 - DQ7
Read V
IL
V
IL
V
IH
Data Out
Write V
IL
V
IH
V
IL
Data In
Standby / Write Inhibit V
IH
X X Hi-Z
Write Inhibit X X V
IH
Data Out or Hi-Z
Write Inhibit X V
IL
X Data Out or Hi-Z
Output Disable X V
IH
X Hi-Z
Note:
X=V
IH
or V
IL
Table3. OperatingModes
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
andsoftwarehandshakingmode withReady/Busy,
Data Polling and Toggle Bit. The M28C16A/17A
supports32 bytepage write operation.
PIN DESCRITPION
Addresses (A0-A10).
The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E).
The chip enable input must be
lowtoenableall read/writeoperations.WhenChip
Enableishigh,power consumptionis reduced.
OutputEnable (G).
The OutputEnableinput controls the data output buffersand is used to initiate
readoperations.
DataIn/Out(DQ0-DQ7).
Datais writtentoorread
fromthe M28C16A/17Athroughthe I/O pins.
WriteEnable(W).
TheWriteEnableinputcontrols
the writingof data to the M28C16A/17A.
Ready/Busy (RB).
Ready/Busy is an open drain
output that can be used to detect the end of the
internalwritecycle.Ready/Busyisavailablefor the
M28C17Ain PDIP, PLCC and SO packages,and
for the M28C16Ain TSOPonly.
OPERATION
Inorderto preventdata corruptionand inadvertent
write operations during power-up, a Power On
Reset(POR)circuitresetsallinternalprogramming
cicuitry. Access to the memory in write mode is
allowedaftera power-upas specifiedin Table7.
Read
The M28C16A/17Ais accessedlike a staticRAM.
When E and G are low with W high, the data
addressed is presented on the I/O pins. The I/O
pinsarehighimpedancewheneitherGorEishigh.
DESCRIPTION
(cont’d)
3/19
M28C16A, M28C17A
AI01520
ADDRESS
LATCH
A6-A10
(Page Address)
X DECODE
CONTROL LOGIC
64K ARRAY
ADDRESS
LATCH
A0-A5
Y DECODE
VPPGEN RESET
SENSE AND DATA LATCH
I/O BUFFERS
EGW
PAGE
LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
Figure3. Block Diagram
Write
Write operations are initiatedwhen both W and E
arelowandG is high.TheM28C16A/17Asupports
bothEand W controlledwritecycles.The Address
is latchedbythefallingedge of E or W which ever
occurslast and the Data on therising edgeof Eor
W which ever occurs first.Once initiatedthe write
operationis internally timed until completion.
Page Write
Page write allows up to 32 bytes to be consecutively latched into the memory prior to initiating a
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Figure4. Status Bit Assignment
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load TimerStatus
programming cycle.All bytes must be located in a
single pageaddress, that is A5- A10 must be the
samefor all bytes. The page write can be initiated
duringany bytewrite operation.
Following the first byte write instruction the host
may sendanotheraddress and data up to amaximumof t
WHWH
afterthe risingedge ofE orW which
ever occurs first. If a transition of E or W is not
detected within t
WHWH
, the internal programming
cyclewill start.
Microcontroller Control Interface
The M28C16A/17A provides two write operation
status bits and one status pin that can be used to
minimize thesystemwritecycle.These signalsare
available on the I/O port bits DQ7 or DQ6 of the
memoryduring programming cycle only, or as the
RB signalon a separate pin.
Data Polling bit (DQ7). During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementaryvalue of the
previouslylatched bit. Once the write cycle is finished the true logic value appears on DQ7 in the
readcycle.
OPERATION(cont’d)
4/19
M28C16A, M28C17A
Symbol Parameter Test Condition Min Max Unit
C
IN
Input Capacitance VIN=0V 6 pF
C
OUT
Output Capacitance V
OUT
=0V 12 pF
Note:
1. Sampled only, not 100% tested.
Table5. Capacitance
(1)
(TA=25°C, f =1 MHz)
Symbol Parameter TestCondition Min Max Unit
I
LI
Input Leakage Current 0V ≤ VIN≤ V
CC
10 µA
I
LO
Output Leakage Current 0V ≤ VIN≤ V
CC
10 µA
I
CC
(1)
Supply Current (TTLand CMOS inputs) E = VIL,G=VIL, f = 5MHz 25 mA
I
CC1
(1)
Supply Current (Standby) TTL E = V
IH
1mA
I
CC2
(1)
Supply Current (Standby) CMOS E > VCC– 0.3V 50
µ
A
V
IL
Input Low Voltage –0.3 0.8 V
V
IH
Input High Voltage 2 VCC+ 0.5 V
V
OL
Output Low Voltage IOL= 2.1 mA 0.4 V
V
OH
Output High Voltage IOH= –400 µA 2.4 V
Note:
1. All I/O’sopen circuit.
Table6. Read ModeDC Characteristicsfor M28C16Aand M28C17A
(T
A
=–40 to 85°C, VCC= 4.5Vto5.5V)
Input Rise and Fall Times
≤
20ns
Input Pulse Voltages 0.4V to 2.4V
Input and Output TimingRef. Voltages 0.8V to 2.0V
Note thatOutput Hi-Z isdefined as the point wheredata is no longer driven.
Table4. AC MeasurementConditions
AI02101B
4.5V to 5.5V Operating Voltage
2.7V to 3.6V Operating Voltage
VCC– 0.3V
0V
0.5 V
CC
2.4V
0.4V
2.0V
0.8V
Figure5. AC TestingInput Output Waveforms
AI02114
OUT
CL= 30pF
CLincludes JIG capacitance
I
OL
DEVICE
UNDER
TEST
I
OH
V
CC
Figure6. AC TestingEquivalent LoadCircuit
5/19
M28C16A, M28C17A
Symbol Parameter Test Condition Min Max Unit
I
LI
Input Leakage Current 0V≤V
IN
≤
V
CC
10
µ
A
I
LO
Output Leakage Current 0V ≤ VIN≤ V
CC
10 µA
I
CC
(1)
Supply Current (TTLand CMOS inputs) E = VIL,G=VIL,f=5MHz 15 mA
I
CC2
(1)
Supply Current (Standby) CMOS E > VCC–0.3V 20 µA
V
IL
Input Low Voltage –0.3 0.6 V
V
IH
Input High Voltage 2 VCC+ 0.5 V
V
OL
Output Low Voltage IOL= 2.1 mA 0.2 V
CC
V
V
OH
Output High Voltage IOH= –400 µA 0.8 V
CC
V
Note: 1. All I/O’s open circuit.
Table8. Read ModeDC Characteristicsfor M28C16A-W
(T
A
=–40 to 85°C, VCC= 2.7Vto3.6V)
Symbol Parameter Min Max Unit
t
PUR
Time Delay to Read Operation 1
µ
s
t
PUW
Time Delay to Write Operation (once VCC≥ VWI)10ms
V
WI
Write InhibitThreshold 1.5 2.5 V
Note: 1. Sampled only,not 100% tested.
Table9. PowerUp Timingfor M28C16A-W
(1)
(TA= –40 to 85°C, VCC= 2.7V to 3.6V)
Symbol Parameter Min Max Unit
t
PUR
Time Delay to Read Operation 1 µs
t
PUW
Time Delay to Write Operation (once VCC≥ VWI)10ms
V
WI
Write InhibitThreshold 1.5 2.5 V
Note:
1. Sampled only, not 100% tested.
Table7. PowerUp Timingfor M28C16A andM28C17A
(1)
(T
A
=
–40 to 85°C, V
CC
= 4.5V to 5.5V)
6/19
M28C16A, M28C17A
Symbol Alt Parameter Test Condition
M28C16A / M28C17A
Unit
-15 -20
min max min max
t
AVQV
t
ACC
Address Validto
Output Valid
E=V
IL
,G=V
IL
150 200 ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G=V
IL
150 200 ns
t
GLQV
t
OE
Output Enable Low to
Output Valid
E=V
IL
70 80 ns
t
EHQZ
(1)
t
DF
Chip Enable High to
Output Hi-Z
G=V
IL
0 50 0 60 ns
t
GHQZ
(1)
t
DF
Output Enable High to
Output Hi-Z
E=V
IL
0 50 0 60 ns
t
AXQX
t
OH
Address Transitionto
Output Transition
E=V
IL
,G=V
IL
00ns
Note: 1. Output Hi-Zis defined as thepoint at which dataisno longer driven.
Table10. Read ModeAC Characteristicsfor M28C16Aand M28C17A
(T
A
=–40 to 85°C, VCC= 4.5Vto5.5V)
Symbol Alt Parameter Test Condition
M28C16A / M28C17A
Unit
-25 -30
min max min max
t
AVQV
t
ACC
Address Validto
Output Valid
E=V
IL
,G=V
IL
250 300 ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G=V
IL
250 300 ns
t
GLQV
t
OE
Output Enable Low to
Output Valid
E=V
IL
100 100 ns
t
EHQZ
(1)
t
DF
Chip Enable High to
Output Hi-Z
G=V
IL
0 70 0 80 ns
t
GHQZ
(1)
t
DF
Output Enable High to
Output Hi-Z
E=V
IL
0 70 0 80 ns
t
AXQX
t
OH
Address Transitionto
Output Transition
E=V
IL
,G=V
IL
00ns
Note: 1. Output Hi-Zis defined as thepoint at which dataisno longer driven.
Table11. Read Mode AC Characteristicsfor M28C16-W
(T
A
=–40 to 85°C, VCC= 2.7Vto3.6V)
7/19
M28C16A, M28C17A
AI01511B
VALID
tAVQV tAXQX
tGLQV tEHQZ
tGHQZ
DATA OUT
A0-A10
E
G
DQ0-DQ7
tELQV
Hi-Z
Figure7. Read Mode AC Waveforms
Toggle bit (DQ6).
The M28C16A/17A offers another way for determining when the internalwrite
cycleis completed.DuringtheinternalErase/Write
cycle,DQ6will toggle from ”0” to ”1” and ”1” to ”0”
(thefirst read valueis”0”) on subsequentattempts
to read any address in the memory. When the
internalcycleiscompletedthetogglingwillstopand
the device will be accessible for a new Read or
Writeoperation.
Page Load Timer Status bit (DQ5)
. In the Page
Writemode data may be latchedby E or W up to
t
WHWH
afterthe previousbyte. Up to 32bytes may
be input. The Data output (DQ5) indicates the
status of the internal Page LoadTimer. DQ5 may
be read by asserting Output Enable Low (t
PLTS
).
DQ5 Low indicates the timer is running, High
Note: WriteEnable (W) = High
8/19
M28C16A, M28C17A
Symbol Alt Parameter Test Condition Min Max Unit
t
AVWL
t
AS
Address Validto Write Enable Low E = VIL,G=V
IH
0ns
t
AVEL
t
AS
Address Validto Chip Enable Low G = VIH,W=V
IL
0ns
t
ELWL
t
CES
Chip Enable Low to Write Enable Low G = V
IH
0ns
t
GHWL
t
OES
Output Enable High to Write Enable
Low
E=V
IL
0ns
t
GHEL
t
OES
Output Enable High to Chip Enable Low W = V
IL
0ns
t
WLEL
t
WES
Write Enable Low to Chip Enable Low G = V
IH
0ns
t
WLAX
t
AH
Write Enable Low to AddressTransition 100 ns
t
ELAX
t
AH
Chip Enable Low to Address Transition 100 ns
t
WLDV
t
DV
Write Enable Low to Input Valid E = VIL,G=V
IH
1 µs
t
ELDV
t
DV
Chip Enable Low to Input Valid G = VIH,W=V
IL
1 µs
t
ELEH
t
WP
Chip Enable Low to Chip Enable High 100 ns
t
WHEH
t
CEH
Write Enable High to Chip Enable High 0 ns
t
WHGL
t
OEH
Write Enable High to Output Enable
Low
0ns
t
EHGL
t
OEH
Chip Enable High to OutputEnable Low 0 ns
t
EHWH
t
WEH
Chip Enable High to WriteEnable High 0 ns
t
WHDX
t
DH
Write Enable High to Input Transition 0 ns
t
EHDX
t
DH
Chip Enable High to Input Transition 0 ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low 200 ns
t
WLWH
tWP Write Enable Low to Write Enable High 100 ns
t
WHWH
t
BLC
Byte Load Repeat Cycle Time 0.2 30 µs
t
WHRH
t
WC
Write Cycle Time 5 ms
t
WHRL
t
DB
Write Enable High to Ready/Busy Low Note 1 100 ns
t
EHRL
t
DB
Chip Enable High to Ready/BusyLow Note 1 100 ns
t
DVWH
t
DS
Data Validbefore WriteEnable High 50 ns
t
DVEH
t
DS
Data Validbefore Chip EnableHigh 50 ns
Note
: 1.With a 3.3 kΩ external pull-upresistor.
Table12. Write Mode AC Characteristicsfor M28C16Aand M28C17A
(T
A
= –40 to 85°C, V
CC
=
4.5V to 5.5V)
9/19
M28C16A, M28C17A
Symbol Alt Parameter Test Condition Min Max Unit
t
AVWL
t
AS
Address Validto Write Enable Low E = VIL,G=V
IH
0ns
t
AVEL
t
AS
Address Validto Chip Enable Low G = VIH,W=V
IL
0ns
t
ELWL
t
CES
Chip Enable Low to Write Enable Low G = V
IH
0ns
t
GHWL
t
OES
Output Enable High to Write Enable
Low
E=V
IL
0ns
t
GHEL
t
OES
Output Enable High to Chip Enable Low W = V
IL
0ns
t
WLEL
t
WES
Write Enable Low to Chip Enable Low G = V
IH
0ns
t
WLAX
t
AH
Write Enable Low to AddressTransition 200 ns
t
ELAX
t
AH
Chip Enable Low to Address Transition 200 ns
t
WLDV
t
DV
Write Enable Low to Input Valid E = VIL,G=V
IH
1 µs
t
ELDV
t
DV
Chip Enable Low to Input Valid G = VIH,W=V
IL
1 µs
t
ELEH
t
WP
Chip Enable Low to Chip Enable High 200 ns
t
WHEH
t
CEH
Write Enable High to Chip Enable High 0 ns
t
WHGL
t
OEH
Write Enable High to Output Enable
Low
0ns
t
EHGL
t
OEH
Chip Enable High to OutputEnable Low 0 ns
t
EHWH
t
WEH
Chip Enable High to WriteEnable High 0 ns
t
WHDX
t
DH
Write Enable High to Input Transition 0 ns
t
EHDX
t
DH
Chip Enable High to Input Transition 0 ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low 200 ns
t
WLWH
tWP Write Enable Low to Write Enable High 200 ns
t
WHWH
t
BLC
Byte Load Repeat Cycle Time 0.4 50 µs
t
WHRH
t
WC
Write Cycle Time 5 ms
t
WHRL
t
DB
Write Enable High to Ready/Busy Low Note 1 250 ns
t
EHRL
t
DB
Chip Enable High to Ready/BusyLow Note 1 250 ns
t
DVWH
t
DS
Data Validbefore WriteEnable High 50 ns
t
DVEH
t
DS
Data Validbefore Chip EnableHigh 50 ns
Note
: 1.With a 3.3 kΩ external pull-upresistor.
Table13. Write Mode AC Characteristicsfor M28C16-W
(T
A
= –40 to 85°C, V
CC
=
2.7V to 3.6V)
10/19
M28C16A, M28C17A
AI01512
VALID
tAVWL
A0-A10
E
G
DQ0-DQ7
DATA IN
W
tWLAX
tELWL
tGHWL
tWLDV
tWHEH
tWHGLtWLWH
tWHWL
tWHDXtDVWH
RB
tWHRL
Figure8. WriteMode AC Waveforms- Write EnableControlled
AI01513
VALID
tAVEL
A0-A10
E
G
DQ0-DQ7
DATA IN
W
tELAX
tGHEL
tWLEL
tELDV
tEHGL
tEHDXtDVEH
RB
tEHRL
tELEH
tEHWH
Figure9. WriteMode AC Waveforms- ChipEnable Controlled
11/19
M28C16A, M28C17A
AI01514
A0-A10
E
G
DQ0-DQ7
W
tWHWH
Addr 0
DQ5
RB
Addr 1 Addr 2 Addr n
tWHWH
tWHRH
tWLWH
tWHWL
tPLTS
tWHRL
Byte 0 Byte 1 Byte 2 Byte n
Byte n
Figure10. PageWrite Mode AC Waveforms- WriteEnable Controlled
AI01516
A0-A10
E
G
DQ7
W
DQ7 DQ7DQ7 DQ7DQ7
READYLAST WRITE INTERNAL WRITE SEQUENCE
Address of thelast byte of thePage Write instruction
Figure11. Data PollingWaveformSequence
12/19
M28C16A, M28C17A
AI01517
A0-A10
E
G
DQ6
W
READYLAST WRITE
INTERNAL WRITESEQUENCE
(1)
TOGGLE
Figure12. ToggleBit Waveform Sequence
Note: 1. First Togglebit is forced to ’0’
13/19
M28C16A, M28C17A
Device Identifier
C16 RBavailable only
for the TSOP
package
C17 RBavailable
Speed
15
(1)
150 ns
20
(1)
200 ns
25
(2)
250ns
30
(2)
300ns
Operating Voltage
blank 4.5V to5.5V
5ms write
W 2.7V to 3.6V
5ms write
Package
BS PDIP28
MS SO28
300 mils
NS TSOP28
8 x 13.4mm
KA PLCC32
Option
T Tape & Reel
Packing
Temperature Range
6 –40 to 85°C
Example: M28C16 – 20 W NS 6 T
Notes: 1. Available forM28C16Aand M28C17Aonly.
2. Available for”W” Operating Voltage only.
Devicesare shippedfrom the factorywith the memory content set at all ”1’s” (FFh).
Fora listof availableoptions(Speed,Package,etc... )orforfurtherinformationonany aspectofthisdevice,
pleasecontactthe STMicroelectronics Sales Officenearest to you.
ORDERINGINFORMATION SCHEME
14/19
M28C16A, M28C17A
PDIP
A2A1A
L
B1 B e1
D
S
E1 E
N
1
C
α
eA
eB
D2
Symb
mm inches
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 36.83 37.34 1.450 1.470
D2 33.02 – – 1.300 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.08 0.070 0.082
α 0° 10° 0° 10°
N28 28
Drawing is not to scale.
PDIP28 - 28 pin PlasticDIP, 600 mils width
15/19
M28C16A, M28C17A
PLCC
D
Ne E1 E
1N
D1
Nd
CP
B
D2/E2
e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
Symb
mm inches
Typ Min Max Typ Min Max
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
Drawing is not to scale.
PLCC32 - 32 lead PlasticLeadedChip Carrier,rectangular
16/19
M28C16A, M28C17A
SO-b
E
N
CP
B
e
A2
D
C
LA1 α
H
A
1
Symb
mm inches
Typ Min Max Typ Min Max
A 2.46 2.64 0.097 0.104
A1 0.13 0.29 0.005 0.011
A2 2.29 2.39 0.090 0.094
B 0.35 0.48 0.014 0.019
C 0.23 0.32 0.009 0.013
D 17.81 18.06 0.701 0.711
E 7.42 7.59 0.292 0.299
e 1.27 – – 0.050 – –
H 10.16 10.41 0.400 0.410
L 0.61 1.02 0.024 0.040
α
0
°
8
°
0
°
8
°
N28 28
CP 0.10 0.004
Drawing is not to scale.
SO28 - 28 lead Plastic Small Outline, 300 mils body width
17/19
M28C16A, M28C17A
Symb
mm inches
Typ Min Max Typ Min Max
A 1.25 0.049
A1 0.20 0.008
A2 0.95 1.15 0.037 0.045
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 13.20 13.60 0.520 0.535
D1 11.70 11.90 0.461 0.469
E 7.90 8.10 0.311 0.319
e 0.55 - - 0.022 - -
L 0.50 0.70 0.020 0.028
α
0
°
5
°
0
°
5
°
N28 28
CP 0.10 0.004
Drawing is not to scale.
TSOP28- 28 lead Plastic Thin Small Outline,8 x 13.4mm
TSOP-c
D1
E
78
CP
B
e
A2
A
22
D
DIE
C
LA1 α
21
28
1
18/19
M28C16A, M28C17A
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ofuse of such informationnor for any infringement of patentsor otherrightsof third parties which mayresult from its use. No license is granted
by implicationor otherwiseunder any patent or patentrights ofSTMicroelectronics. Specifications mentioned in this publication are subjectto
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as criticalcomponents in lifesupport devices or systems without express writtenapproval of STMicroelectronics.
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STMicroelectronics GROUP OFCOMPANIES
Australia - Brazil - Canada- China - France- Germany - Italy - Japan - Korea - Malaysia - Malta- Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden- Switzerland -Taiwan - Thailand -United Kingdom - U.S.A.
19/19
M28C16A, M28C17A
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