4 Mbit (512Kb x 8) Low Voltage OTP EPROM
■ LOW VOLTAGE READ OPERATION:
3V to 3.6V
■ FAST ACCESS TIME: 120ns
■ LOW POWER CONSUMPTION:
– Active Current 15mA at 5MHz
– Standby Current 20µA
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMI N G TIMES:
– Typical 48sec. (PRESTO II Algorithm)
– Typical 27sec. (On-Board Programming)
■ PIN COMPATIBLE with the 4 Mbit,
Single Voltage Flash Memory
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: B4
M27V405
PLCC32 (K) TSOP32 (N)
8 x 20 mm
Figure 1. Logic Diagram
DESCRIPTION
The M27V405 is a low v oltage 4 Mbit EPROM offered in the OTP range (one time programmable).
It is ideally suited for microprocessor systems requiring large data or program storage and is organised as 524,288 by 8 bits.
The M27V405 operates in the read mode with a
supply voltage as low as 3V . Th e decrease in operating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
Table 1. Signal Names
A0-A18 Address Inputs
Q0-Q7 Data Outputs
E
G
V
PP
V
CC
V
SS
Chip Enable
Output Enable
Program Supply
Supply Voltage
Ground
CC
M27V405
V
SS
V
PP
8
AI01800
V
19
A0-A18 Q0-Q7
E
G
1/13May 1998
M27V405
Figure 2A. LCC Pin Connections
PP
CC
A18
32
Q3
V
Q4
V
Q5
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A16
A12
A15
1
9
M27V405
17
Q1
Q2
SS
V
A17
25
Q6
A14
A13
A8
A9
A11
G
A10
E
Q7
AI01801
Figure 2B. TSOP Pin Connections
A11 G
1
A9
A8
A13
A14
A17
V
PP
M27V405
V
A18
CC
8
(Normal)
9
A16
A15
A12
A7
A6
A5
A4 A3
16 17
32
25
24
AI01802
A10
E
Q7
Q6
Q5
Q4
Q3
V
SS
Q2
Q1
Q0
A0
A1
A2
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the ratin g " Operating Temperat ure Range", stresse s above th ose listed i n the Tabl e " A bsolute M aximum Rat i ngs" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indi cated in t he Opera t in g sections of this specif i cation i s not imp l i ed. Exposu re to Absolute Ma xi m um Rati ng condi tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality do c uments.
2. Min imum DC volta ge on In put or O utput is –0.5V with po ssible under shoot t o –2.0V f or a period less th an 20ns. Maximu m DC
voltage on Output is V
3. Depends on range.
Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC +2V for a period l ess than 20n s.
CC
(1)
(3)
–40 to 125 °C
2/13
Table 3. Operating Modes
Mode E G A9
Read
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Note: X = VIH or VIL, VID = 12V ± 0.5V.
V
IL
V
IL
V
Pulse V
IL
V
IH
V
IH
V
IH
V
IL
V
IL
V
IH
IH
V
IL
V
IH
XX
V
IL
X
X
X
X
X
V
ID
V
PP
V
or V
CC
SS
V
or V
CC
SS
V
PP
V
PP
V
PP
V
or V
CC
SS
V
CC
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
Device Code
V
IL
V
IH
00100000 20h
10110100 B4h
M27V405
Q0-Q7
Data Out
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
The M27V405 is pin compatible with the industry
standard 4 Mbit, sing le voltage Flash Mem ory. It
can be considered as a Flash Low C ost solution
for production quantities.
The M27V405 can also be operated as a standard
4 Mbit OTP EPROM (s imilar to M27C405) with a
5V power supply. The M27V405 is offered in
PLCC32 and TSOP32 (12 x 20 mm) packages.
DEVICE OPERATION
The modes of operations of the M27V405 are listed in the Operating Modes table. A singl e power
supply is required in the read mode. All inputs are
TTL levels except for V
and 12V on A9 for Elec-
pp
tronic Signature.
Read Mode
The M27V405 ha s two control functions, both of
which must be logically ac tive in order to obtain
data at the output s. Chip Enable (E
) is the power
control and should be used for device selection.
Output Enable (G
) is the output control and should
be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time
(t
) is equal to the delay from E to output
AVQV
(t
). Data is available at the output after a delay
ELQV
from the falling edge of G, assum ing that
GLQV
has been low and the addresses have been sta-
AVQV-tGLQV
.
of t
E
ble for at least t
Standby Mode
The M27V405 has a standby mode which reduces
the active current from 15mA to 20µA with low voltage operation V
≤ 3.6V , see Read Mod e DC
CC
Characteristics Table for details. The M 27V405 is
placed in the standby mode b y applying a CMOS
high signal to the E
input. When in the standby
mode, the outputs are in a h igh impedanc e state,
independent of the G
input.
3/13
M27V405
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
10ns
≤
20ns
≤
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: Sampled only, not 10 0% tested.
Input Capacitance
Output Capacitance
(1)
(TA = 25 °C, f = 1 MHz)
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
V
V
IN
OUT
= 0V
= 0V
6pF
12 pF
OUT
AI01823B
Two Line Outp ut C ontrol
Because OTP EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance tha t output bus contention
will not occur.
For the most efficient use of these two control
lines, E
ry device selecting function, while G
should be decoded and used as the prima-
should be
made a common connectio n to all devices in the
4/13
array and connected to the READ
line from the
system control bus. This ensures that all deselected memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS OTP EPROM s require careful decoupling
of the devices. The supply current, I
, has three
CC
segments that a re of intere st to the syste m designer: the standby current level, the active current level, and transient current peaks that are p roduced
M27V405
Table 7. Read Mode DC Characteristics
(1)
(TA = 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
Symbol Parameter Test Condition Min Max Unit
I
I
I
CC
I
CC1
I
CC2
I
V
V
IH
V
Input Leakage Current
LI
Output Leakage Curren t
LO
= VIL, G = VIL, I
Supply Current
E
f = 5MHz, V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
PP
Input Low Voltage –0.3 0.8 V
IL
(2)
Input High Voltage 2
Output Low Voltage
OL
> VCC – 0.2V, VCC
E
Output High Voltage TTL
V
OH
Output High Voltage CMOS
Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultaneously or af ter VPP.
2. Max imum DC voltage on Output i s V
Table 8A. Read Mode AC Characteristics
CC
+0.5 V.
(1)
0V
0V ≤ V
I
I
≤ V
V
≤
IN
CC
≤ V
OUT
CC
= 0mA,
OUT
3.6V
≤
CC
E
= V
IH
≤
V
= V
PP
CC
I
= 2.1mA
OL
= –400µA
OH
= –100µA V
OH
3.6V
±10 µA
±10 µA
15 mA
1mA
20 µA
10 µA
V
+ 1
CC
0.4 V
2.4 V
– 0.7V
CC
(TA = 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
M27V405
Symbol Alt Parameter Test Condition
V
V
Unit-120 -150
Min Max Min Max
CC
E
= VIL, G = V
G
= V
E
= V
G
= V
E
= V
= VIL, G = V
E
IL
IL
IL
IL
IL
0 50 0 50 ns
0 50 0 50 ns
00ns
IL
120 150 ns
120 150 ns
and VSS. This should be a high frequency capac itor of low inherent inductance and should be
placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be
used between V
and VSS for every eight devic-
CC
es. The bulk capacitor sho uld be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultaneously or af ter VPP.
2. Sam pl ed only, not 100% tested.
(2)
(2)
t
Address Valid to Output Valid
ACC
t
Chip Enable Low to Output Valid
CE
t
Output Enable Low to Output Valid
OE
t
Chip Enable High to Output Hi-Z
DF
t
Output Enable High to Output Hi-Z
DF
Address Transition to Output
t
OH
Transition
by the falling and rising edges of E. The magnitude
of the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0 .1µF ceram ic
capacitor be used on every device between V
60 80 ns
5/13
M27V405
Table 8B. Read Mode AC Characteristics
(1)
(TA = 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
M27V405
Symbol Alt Parameter Test Condition
Min Max Min Max
E
= VIL, G = V
G
= V
E
= V
G
= V
E
= V
= VIL, G = V
E
IL
IL
IL
IL
IL
0 50 0 70 ns
0 50 0 70 ns
00ns
IL
180 200 ns
180 200 ns
90 100 ns
(2)
(2)
t
Address Valid to Output Valid
ACC
t
Chip Enable Low to Output Valid
CE
t
Output Enable Low to Output Valid
OE
t
Chip Enable High to Output Hi-Z
DF
t
Output Enable High to Output Hi-Z
DF
Address Transition to Output
t
OH
Transition
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultaneously or af ter VPP.
2. Sampled only, not 100% tested
Figure 5. Read Mode AC Waveforms
Unit-180 -200
A0-A18
E
G
Q0-Q7
tAVQV
tELQV
VALID
tGLQV
VALID
tAXQX
tEHQZ
tGHQZ
Hi-Z
AI00724B
6/13
M27V405
Table 9. Programming Mode DC Characteristics
(1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
I
LI
I
CC
I
PP
V
V
V
OL
V
OH
V
Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultaneously or af ter VPP.
Input Leakage Current
Supply Current 50 mA
Program Current
Input Low Voltage –0.3 0.8 V
IL
Input High Voltage 2
IH
Output Low Voltage
Output High Voltage TTL
A9 Voltage 11.5 12.5 V
ID
Table 10. Programming Mode AC Characteristics
0 ≤ V
E
= V
I
= 2.1mA
OL
I
= –400µA
OH
(1)
IN
≤ V
IL
CC
±10
50 mA
V
+ 0.5
CC
0.4 V
2.4 V
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
t
t
t
t
t
t
Address Valid to Chip Enable Low 2 µs
AS
t
Input Valid to Chip Enable Low 2 µs
DS
VPP High to Chip Enable Low
VPS
VCC High to Chip Enable Low
VCS
Chip Enable Program Pulse Width 95 105 µs
PW
t
Chip Enable High to Input Transition 2 µs
DH
Input Transition to Output Enable Low 2 µs
OES
t
Output Enable Low to Output Valid 100 ns
OE
Output Enable High to Output Hi-Z 0 130 ns
DFP
Output Enable High to Address
t
AH
Transition
2µs
2µs
0ns
t
AVEL
t
QVEL
t
VPHEL
t
VCHEL
t
ELEH
t
EHQX
t
QXGL
t
GLQV
t
GHQZ
t
GHAX
Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultaneously or af ter VPP.
2. Sampled only, not 100% tested.
A
µ
V
Programming
The M27V405 has been designed to be fully compatible with the M27C405 and has the same electronic signature. As a result the M 27V405 c an be
programmed as the M27C405 on the same programming equipments applying 12.75V on V
PP
and 6.25V on VCC by the use of t he same PRESTO II algorithm. When delivered, all bits of the
M27V405 are in the ’1’ state.Data is introduced by
selectively programming ’0’s into the desired bit lo-
cations. Although only ’0’s will be programmed,
both ’1’s and ’0’s can be present in the data word.
The M27V405 is in the programming mode when
V
input is at 12.75V, G is at VIH and E is pulsed
PP
to V
. The data to be prog rammed is applied to 8
IL
bits in parallel to the data ou tput pins. The levels
required for the address and data inputs are TTL.
is specified to be 6.25V±0. 25V, but it can be
V
CC
set to lower values in case of On-Board Programming (see dedicated paragraph).
7/13
M27V405
Figure 6. Programming and Verify Mod es AC Wavefor ms
A0-A18
tAVPL
Q0-Q7
V
PP
V
CC
E
G
DATA IN DATA OUT
tQVEL
tVPHEL
tVCHEL
tELEH
PROGRAM VERIFY
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be program m ed wi th a guaranteed
margin, in a typical time of 52.5 seconds. Programming with PRESTO II consists of applyi ng a
sequence of 100ms program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pul se is applied
since the verify in MARGI N MODE provides the
necessary margin to each programmed cell.
Program Inhibit
Programming of multiple M27V405s in parallel
with different data is also easily accomplished. Except fo r E
, all like inputs including G of the parallel
M27V405 may be common. A TTL low level pulse
applied to a M27V405’s E
input, with VPP at
12.75V, will program that M27V405. A high level E
input inhibits the other M27V405s from bei ng programmed.
VALID
tEHQX
tGLQV
tQXGL
tGHQZ
tGHAX
AI00725
Program Verify
A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with G
at VIL , E at VIH, VPP at 12.75V and VCC at 6.25V.
On-B oard Programming
Programming the M27V405 may be performed directly in the application circuit, however this requires modification to the PRESTO II Algorithm
(see Figure 8). For in-circuit programming V
determined by the user and normally is compatible
with other components using the same supply voltage. It is recommended that the maximum value of
V
which remains compatible with the circuit is
CC
used.
Typically V
ing V
CC
=5.5V for program m ing sy stems us-
CC
=5V, and VCC=3.5V for low voltage 3V
systems is recommended. The valu e of V
not affect the programming, it gives a higher test
capability in VERIFY mode.
must be kept at 12.75 volts to maintain and
V
PP
enable the programming.
CC
is
CC
does
8/13
M27V405
Figure 7. Programming Flowchart
VCC = 6.25V, VPP = 12.75V
n = 0
E = 100µs Pulse
NO
NO
VERIFY
YES
NO
Last
Addr
YES
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
++ Addr
YES
++n
= 25
FAIL
AI00760B
Figure 8. On-Board Programming Flowchartt
VPP = 12.75V
SET MARGIN MODE
n = 0
E = 10µs Pulse
NO
NO
VERIFY
?
YES
E = 10µs Pulse
Last
NO
Addr
YES
CHECK ALL BYTES
VPP = V
CC
++ Addr
YES
++n
= 25
FAIL
Warning: compatibility with Flash Memory
Compatibility issues may arise when replacing the
compatible Single Supply 4 Mbit Flash Memory
(the M29F040) by the M27V405.
The V
"W" pin of the M29F040. The M27V 405 V
pin of the M 27V405 corresponds to the
PP
PP
pin
can withstand voltages up to 12.75V, while the "W"
pin of the M29F040 is a normal control signal input
and may be damaged if a high voltage is applied;
special precautions must be taken when programming in-circuit.
However if an already programmed M27V405 is
used, this can be directly put in place of the Flash
Memory as the V
ming mode, is set to V
Changes to PRESTO II
input, when not in program -
PP
or VSS.
CC
. The duration of the pro-
gramming pulse is red uced to 20µs, making the
programming time of the M27V405 comparable
with the counterpart Flash Memory.
AI01349
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an OTP EPROM
that will identify its manufacturer and type. This
mode is intended for use by programming equipment to automatically m atch the device t o b e programmed with its corresponding programming
algorithm. This mod e is functional in the 25°C ±
5°C ambient temperature range that is required
when programming the M27V 405. To activate t he
ES mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the M27V405
with V
PP=VCC
=5V. Two identifier bytes may then
be sequenced from the device outputs by toggling
address line A0 from V
lines must be held at V
ture mode. Byte 0 (A0=V
facturer code and byte 1 (A0=V
to VIH. All other address
IL
during Electronic Signa-
IL
) represents the manu-
IL
) the device
IH
identifier code. For the STMicroelectronics
M27V405, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q0 to Q7.
9/13
M27V405
Table 11. Ordering Information Scheme
Example: M27V405 -120 K 1 TR
Device Type
Speed
-120 = 120 ns
-150 = 150 ns
-180 = 180 ns
-200 = 200 ns
Package
K = PLCC32
N = TSOP32: 8 x 20mm
Temperature Range
1 = –0 to 70 °C
4 = –20 to 70 °C
5 = –20 to 85 °C
6 = –40 to 85 °C
Option
TR = Tape & Reel Packing
For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this device, please contact the ST Sales Office nearest to you.
10/13
M27V405
Table 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Packag e Mec han ical Data
Symb
A 2.54 3.56 0.100 0.1 40
A1 1.52 2.41 0.060 0.0 95
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.0 21
B1 0.66 0.81 0.026 0.0 32
D 12.32 12.57 0.485 0.4 95
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14 .10 0.547 0.555
E2 12.45 13 .46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
Typ Min Max Typ Min Max
mm inches
Figure 9. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Ou tline
D
D1
1 N
Ne E1 E
F
D2/E2
A2
B
0.51 (.020)
1.14 (.045)
Nd
R
PLCC
Drawing is not to scale.
CP
A1
B1
e
A
11/13
M27V405
Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.15 0.002 0.007
A2 0.95 1.05 0.037 0.041
B 0.15 0.27 0.006 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 7.90 8.10 0.311 0.319
e 0.50 – – 0.020 – –
L 0.50 0.70 0.020 0.028
α
N32 32
CP 0.10 0.004
mm inches
0° 5° 0° 5°
Figure 10. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline
A2
1 N
e
E
B
N/2
D1
D
DIE
A
CP
C
TSOP-a
Drawing is not to scale.
LA1 α
12/13
M27V405
Information furnished is believed to be accurate an d rel i able. However, STMicroelectro ni cs assumes no responsibility for the con sequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent ri ghts of STM i croelectr onics. Specifications menti oned in thi s publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approv al of STMicroel ectronics.
The ST log o i s registered trademark of STMicroelectronics
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13/13
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