SGS Thomson Microelectronics M27V405 Datasheet

4 Mbit (512Kb x 8) Low Voltage OTP EPROM

■ LOW VOLTAGE READ OPERATION:

3V to 3.6V

■ FAST ACCESS TIME: 120ns

■ LOW POWER CONSUMPTION:

– Active Current 15mA at 5MHz
– Standby Current 20µA

■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■ PROGRAMMI N G TIMES:

– Typical 48sec. (PRESTO II Algorithm)
– Typical 27sec. (On-Board Programming)

■ PIN COMPATIBLE with the 4 Mbit,

Single Voltage Flash Memory

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Device Code: B4

M27V405

PLCC32 (K) TSOP32 (N)

8 x 20 mm

Figure 1. Logic Diagram

DESCRIPTION

The M27V405 is a low v oltage 4 Mbit EPROM of­fered in the OTP range (one time programmable).
It is ideally suited for microprocessor systems re­quiring large data or program storage and is orga­nised as 524,288 by 8 bits.

The M27V405 operates in the read mode with a
supply voltage as low as 3V . Th e decrease in op­erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.

Table 1. Signal Names

A0-A18 Address Inputs
Q0-Q7 Data Outputs
E
G
V

PP

V

CC

V

SS

Chip Enable
Output Enable
Program Supply
Supply Voltage
Ground

CC

M27V405

V

SS

V

PP

8

AI01800

V

19

A0-A18 Q0-Q7

E

G

1/13May 1998

M27V405

Figure 2A. LCC Pin Connections

PP

CC

A18

32

Q3

V

Q4

V

Q5

A7
A6
A5
A4
A3
A2
A1
A0

Q0

A16

A12

A15

1

9

M27V405

17

Q1

Q2

SS

V

A17

25

Q6

A14
A13
A8
A9
A11
G
A10
E
Q7

AI01801

Figure 2B. TSOP Pin Connections

A11 G

1
A9
A8

A13
A14
A17

V

PP

M27V405

V

A18

CC

8

(Normal)

9

A16
A15
A12

A7
A6
A5
A4 A3

16 17

32

25
24

AI01802

A10
E
Q7
Q6
Q5
Q4
Q3
V

SS

Q2
Q1
Q0
A0
A1
A2

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the ratin g " Operating Temperat ure Range", stresse s above th ose listed i n the Tabl e " A bsolute M aximum Rat i ngs" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indi cated in t he Opera t in g sections of this specif i cation i s not imp l i ed. Exposu re to Absolute Ma xi m um Rati ng condi ­tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qua­lity do c uments.

2. Min imum DC volta ge on In put or O utput is –0.5V with po ssible under shoot t o –2.0V f or a period less th an 20ns. Maximu m DC

voltage on Output is V

3. Depends on range.

Ambient Operating Temperature

Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC +2V for a period l ess than 20n s.

CC

(1)

(3)

–40 to 125 °C

2/13

Table 3. Operating Modes

Mode E G A9

Read
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature

Note: X = VIH or VIL, VID = 12V ± 0.5V.

V

IL

V

IL

V

Pulse V

IL

V

IH

V

IH

V

IH

V

IL

V

IL

V

IH

IH

V

IL

V

IH

XX

V

IL

X
X
X
X
X

V

ID

V

PP

V

or V

CC

SS

V

or V

CC

SS

V

PP

V

PP

V

PP

V

or V

CC

SS

V

CC

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code
Device Code

V

IL

V

IH

00100000 20h
10110100 B4h

M27V405

Q0-Q7

Data Out

Hi-Z

Data In

Data Out

Hi-Z
Hi-Z

Codes

The M27V405 is pin compatible with the industry
standard 4 Mbit, sing le voltage Flash Mem ory. It
can be considered as a Flash Low C ost solution
for production quantities.

The M27V405 can also be operated as a standard
4 Mbit OTP EPROM (s imilar to M27C405) with a
5V power supply. The M27V405 is offered in
PLCC32 and TSOP32 (12 x 20 mm) packages.

DEVICE OPERATION

The modes of operations of the M27V405 are list­ed in the Operating Modes table. A singl e power
supply is required in the read mode. All inputs are
TTL levels except for V

and 12V on A9 for Elec-

pp

tronic Signature.

Read Mode

The M27V405 ha s two control functions, both of
which must be logically ac tive in order to obtain
data at the output s. Chip Enable (E

) is the power

control and should be used for device selection.
Output Enable (G

) is the output control and should
be used to gate data to the output pins, indepen­dent of device selection. Assuming that the ad­dresses are stable, the address access time
(t

) is equal to the delay from E to output

AVQV

(t

). Data is available at the output after a delay

ELQV

from the falling edge of G, assum ing that

GLQV

has been low and the addresses have been sta-

AVQV-tGLQV

.

of t
E
ble for at least t

Standby Mode

The M27V405 has a standby mode which reduces

the active current from 15mA to 20µA with low volt­age operation V

≤ 3.6V , see Read Mod e DC

CC

Characteristics Table for details. The M 27V405 is
placed in the standby mode b y applying a CMOS
high signal to the E

input. When in the standby
mode, the outputs are in a h igh impedanc e state,
independent of the G

input.

3/13

M27V405

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

10ns

≤

20ns

≤

Figure 3. AC Testing Input Output Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: Sampled only, not 10 0% tested.

Input Capacitance
Output Capacitance

(1)

(TA = 25 °C, f = 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE
UNDER

TEST

CL

CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance

V

V

IN

OUT

= 0V

= 0V

6pF

12 pF

OUT

AI01823B

Two Line Outp ut C ontrol

Because OTP EPROMs are usually used in larger
memory arrays, this product features a 2 line con­trol function which accommodates the use of mul­tiple memory connection. The two line control
function allows:

a. the lowest possible memory power dissipation,
b. complete assurance tha t output bus contention

will not occur.

For the most efficient use of these two control
lines, E
ry device selecting function, while G

should be decoded and used as the prima-

should be

made a common connectio n to all devices in the

4/13

array and connected to the READ

line from the
system control bus. This ensures that all deselect­ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.

System Considerations

The power switching characteristics of Advanced
CMOS OTP EPROM s require careful decoupling
of the devices. The supply current, I

, has three

CC

segments that a re of intere st to the syste m design­er: the standby current level, the active current lev­el, and transient current peaks that are p roduced