SGS Thomson Microelectronics M27V256 Datasheet

M27V256

256 Kbit (32Kb x 8) Low Voltage UV EPROM and OTP EPROM

■ LOW VOLTAGE READ OPERATION:

3V to 3.6V

■ FAST ACCESS TIME: 90ns

■ LOW POWER CONSUMPTION:

CC

28

V

PP

1

8 x 13.4mm

8

– Active Current 10mA at 5MHz – Standby Current 10µA

■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■ PROGRAMMING TIME: 100µs/byte (typical)

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 8Dh

DESCRIPTION

The M27V256 is a low voltage 256 Kbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems and is organized as 32,768 by 8 bits.

The M27V256 operates in the read mode with a supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges.

The FDIP28W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chiptoultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

28

1

FDIP28W (F) PDIP28 (B)

PLCC32 (K) TSOP28 (N)

Figure 1. Logic Diagram

V

15

A0-A14 Q0-Q7

Table 1. Signal Names

A0-A14 Address Inputs Q0-Q7 Data Outputs E Chip Enable G Output Enable V

PP

V

CC

V

SS

Program Supply Supply Voltage Ground

E

G

M27V256

V

SS

AI01908

1/15May 1998

M27V256

Figure 2A. DIP Pin Connections

V

PP

A12

A7 A6 A5 A4 A3 A2 A1 A0

Q0

Q2 SS

1 2 3 4 5 6 7 8 9 10 11 12 13 14

M27V256

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AI01909

V

CC

A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5Q1 Q4 Q3V

Figure 2B. LCC Pin Connections

PP

CC

A13

DU

32

DU

V

Q3

A14

Q4

25

Q5

A8 A9 A11 NC G A10 E Q7 Q6

AI01910

V

A7

A12

A6 A5 A4 A3 A2

9 A1 A0

NC

Q0

Q1

Warning: NC = Not Connected, DU = Dont’t Use.

1

M27V256

17

Q2

SS

V

Figure 2C. TSOP Pin Connections

G

A11

A13 A14

V

A12

A9 A8

CC

PP

A7 A6 A5 A4 A3

22

28

M27V256

1

78

21

15 14

AI01911

A10 E Q7 Q6 Q5 Q4 Q3 V

SS

Q2 Q1 Q0 A0 A1 A2

For applications where the content is programmed only one time and erasure is not required, the M27V256 is offered in PDIP28, PLCC32 and TSOP28 (8 x 13.4 mm) packages.

DEVICE OPERATION

The modes of operation of the M27V256are listed in the Operating Modes. A single power supply is required in the read mode. All inputs are TTL levels except for VPPand 12V on A9 for Electronic Signature.

Read Mode

The M27V256 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (t

) is equal to the delay from E to output

AVQV

(t

). Data is available at the output after delay

ELQV

of t

from the falling edge of G, assuming that

GLQV

E has been low and the addresses have been stable for at least t

AVQV-tGLQV

.

2/15

M27V256

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device.These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program andother relevant quality documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is V

3. Depends on range.

Ambient Operating Temperature Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC+2V for a period less than 20ns.

CC

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E G A9

Read Output Disable V Program

V Verify V Program Inhibit Standby Electronic Signature

Note: X = VIHor VIL,VID= 12V ± 0.5V.

V

IL

Pulse V

IL

IH

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

V

IH

X XVCCHi-Z X XVPPData Out X

XX

V

IL

V

ID

V

PP

V

CC

V

PP

V

PP

V

CC

V

CC

Data Out

Q0-Q7

Data In

Hi-Z Hi-Z

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code Device Code

V

IL

V

IH

Standby Mode

The M27V256 hasastandbymodewhich reduces the supply current from 10mA to 10µA with low voltage operationVCC≤ 3.6V, seeRead Mode DC

00100000 20h 10001101 8Dh

placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.

Characteristics table for details. The M27V256 is

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M27V256

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: Sampled only, not 100% tested.

Input Capacitance Output Capacitance V

(1)

(TA=25°C, f = 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE UNDER

TEST

C

L

CL= 30pF for High Speed CL= 100pF for Standard CLincludes JIG capacitance

V

=0V

IN

=0V 12 pF

OUT

6pF

OUT

AI01823B

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memory power dissipation, b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control lines, E shouldbe decoded and used as theprimary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the

4/15

system control bus. This ensures that all deselected memory devices are intheir lowpower standby mode and hat the output pins are only active when data is desired from a particular memory device.

System Considerations

The power switching characteristics of Advance CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of this transient current peaks is dependent on the capacitive and inductive loading of the device at the output.

M27V256

Table 7. Read Mode DC Characteristics

(1)

(TA = 0 to 70°C or –40 to 85°C; VCC= 3.3V ± 10%;VPP=VCC)

Symbol Parameter Test Condition Min Max Unit

I

CC

I

CC1

I

CC2

I V

V

IH

V

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Table 8A. Read Mode AC Characteristics

Input Leakage Current

LI

Output Leakage Current

LO

Supply Current

E=V

IL

f = 5MHz, V

0V ≤ V

,G=VIL,I

Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current

PP

Input Low Voltage –0.3 0.8 V

IL

(2)

Input High Voltage 2 Output Low Voltage

OL

Output High Voltage TTL

OH

Output High Voltage CMOS

2. Maximum DC voltage on Output is V

CC

+0.5V.

(1)

E>V

CC

I I

OH

≤ V

IN

CC

≤ V

OUT

E=V

CC

IH

CC

OUT

≤ 3.6V

= 0mA,

–0.2V,VCC≤ 3.6V

V

PP=VCC

I

= 2.1mA

OL

= –400µA = –100µA

2.4 V

Vcc – 0.7V V

±10 µA ±10 µA

10 mA

1mA 10 µA 10 µA

V

+1

CC

0.4 V

(TA= 0 to 70 °C or –40 to 85°;VCC= 3.3V ± 10%; VPP=VCC)

M27V256

Symbol Alt Parameter Test Condition

-90

(3)

-100

Min Max Min Max

Unit

V

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

AXQX

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

3. Speed obtained with High Speed AC measurement conditions.

The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic

capacitor be used on every device between V and VSS. This should be a high frequency capacitor of low inherent inductance and should be

(2)

t

Address Valid to Output Valid E = VIL,G=V

ACC

t

Chip Enable Low to Output Valid

CE

t

Output Enable Low to Output Valid

OE

t

Chip Enable High to Output Hi-Z G = V

DF

t

Output Enable High to Output Hi-Z

DF

Address Transition to Output

t

OH

Transition

CC

90 100 ns 90 100 ns 40 45 ns

025030ns 025030ns

00ns

G=V E=V

E=V

,G=V

IL

placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCCand VSSfor every eight devices. The bulk capacitor should be located near the power supplyconnection point. The purposeof the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

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