M27V201
2 Mbit (256Kb x 8) Low Voltage UV EPROM and OTP EPROM
■ LOW VOLTAGE READ OPERATION:
3V to 3.6V
■ FAST ACCESS TIME: 120ns
■ LOW POWER CONSUMPTION:
CC
32
V
1
8 x 20 mm
PP
8
Q0-Q7
– Active Current15mA at 5MHz
– Standby Current 20µA
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/byte (typical)
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 61h
DESCRIPTION
The M27V201 is a low voltage 2 Mbit EPROM offered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiringlarge data or
program storage and is organised as 262,144 by 8
bits.
The M27V201 operates in the read mode with a
supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP32W (window ceramic frit-seal package)
has a transparent lid which allow the user to expose the chiptoultraviolet light to erasethebitpattern.
Table 1. Signal Names
32
1
FDIP32W (F) PDIP32 (B)
PLCC32 (K) TSOP32 (N)
Figure 1. Logic Diagram
V
18
A0-A17
A0-A17 Address Inputs
Q0-Q7 Data Outputs
E Chip Enable
G Output Enable
P Program
V
PP
V
CC
V
SS
Program Supply
Supply Voltage
Ground
P
E
G
M27V201
V
SS
AI00693B
1/15May 1998
M27V201
Figure 2A. DIP Pin Connections
V
PP
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q2
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
M27V201
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AI01901
V
CC
PA16
A17
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
Figure 2B. LCC Pin Connections
CC
VPPV
32
Q3
Q4
P
Q5
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A16
A12
A15
1
9
Q1
Q2
M27V201
17
SS
V
A17
25
Q6
A14
A13
A8
A9
A11
G
A10
E
Q7
AI00694
Figure 2C. TSOP Pin Connections
A11 G
A9
A8
A13
A14
A17
V
CC
V
PP
A16
A15
A12
A7
A6
A5
A4 A3
1
P
M27V201
8
(Normal)
9
16 17
32
25
24
AI01154B
A10
E
Q7
Q6
Q5
Q4
Q3
V
SS
Q2
Q1
Q0
A0
A1
A2
A new pattern can then be written to the device by
following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27V201 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
DEVICE OPERATION
The operating modes of the M27V201 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for VPPand 12V on A9for Electronic
Signature.
Read Mode
The M27V201 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time
(t
) is equal to the delay from E to output
AVQV
(t
). Data is availableat the outputafter a delay
ELQV
of t
from the falling edge of G, assuming that
GLQV
E has been low and the addresses have been stable for at least t
AVQV-tGLQV
.
2/15
M27V201
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SUREProgram andother relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC+2V for a period less than 20ns.
CC
(3)
–40 to 125 °C
Table 3. Operating Modes
Mode E G P A9
Read
Output Disable V
Program
Verify V
Program Inhibit
Standby
Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
V
IL
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
IH
V
IL
XX
XXV
VILPulse
V
IH
X
XVPPData Out
XXX
XXX
V
IL
V
IH
V
ID
V
PP
V
or V
CC
SS
or V
CC
SS
V
PP
V
PP
V
or V
CC
SS
V
CC
Q0-Q7
Data Out
Hi-Z
Data In
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
Device Code
V
IL
V
IH
Standby Mode
The M27V201 hasa standby mode which reduces
the active currentfrom 15mA to 20µA with lowvolt-
age operation VCC≤ 3.6V, see Read Mode DC
00100000 20h
01100001 61h
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
Characteristics table for details.The M27V201 is
3/15
M27V201
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: Sampled only, not 100% tested.
Input Capacitance
Output Capacitance V
(1)
(TA=25°C, f = 1 MHz)
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
C
L
CL= 30pF for High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
V
=0V
IN
=0V 12 pF
OUT
6pF
OUT
AI01823B
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should bedecoded and used as theprimary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system controlbus. This ensures that all deselect-
4/15
ed memory devices are intheir low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
M27V201
Table 7. Read Mode DC Characteristics
(1)
(TA = 0 to 70°C or –40 to 85°C; VCC= 3.3V ± 10%;VPP=VCC)
Symbol Parameter TestCondition Min Max Unit
I
I
I
CC
I
CC1
I
CC2
I
V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Table 8A. Read Mode AC Characteristics
Input Leakage Current
LI
Output Leakage Current
LO
Supply Current
E=V
IL
f = 5MHz, V
0V ≤ V
0V ≤ V
,G=VIL,I
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
PP
Input Low Voltage –0.3 0.8 V
IL
(2)
Input High Voltage 2
Output Low Voltage
OL
Output High Voltage TTL
OH
Output High Voltage CMOS
2. Maximum DC voltage on Output is V
CC
+0.5V.
(1)
E>V
CC
I
I
OH
OH
≤ V
IN
CC
≤ V
OUT
CC
= 0mA,
OUT
≤ 3.6V
CC
E=V
IH
–0.2V,VCC≤ 3.6V
V
PP=VCC
I
= 2.1mA
OL
= –400µA
= –100µA
2.4 V
Vcc –0.7V V
±10 µA
±10 µA
15 mA
1mA
20 µA
10 µA
V
+1
CC
0.4 V
(TA= 0 to 70 °C or –40 to 85°;VCC= 3.3V ± 10%; VPP=VCC)
M27V201
Symbol Alt Parameter Test Condition
-120 -150
Min Max Min Max
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
(2)
(2)
t
Address Valid to Output Valid
ACC
t
Chip Enable Low to Output Valid
CE
t
Output Enable Low to Output Valid
OE
t
Chip Enable High to Output Hi-Z
DF
t
Output Enable High to Output Hi-Z
DF
Address Transition to Output
t
OH
Transition
E=V
G=V
E=V
G=V
E=V
E=V
,G=V
IL
,G=V
IL
IL
IL
IL
IL
IL
IL
120 150 ns
120 150 ns
50 60 ns
040050ns
040050ns
00ns
Unit
V
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between V
CC
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be
used between VCCand VSSfor every eight devices. The bulk capacitor should be located near the
power supply connection point.Thepurpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
M27V201
Table 8B. Read Mode AC Characteristics
(1)
(TA= 0 to 70°C or –40 to 85 °C; VCC= 3.3V ± 10%;VPP= Vcc)
M27V201
Symbol Alt Parameter Test Condition
-180 -200
Min Max Min Max
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
(2)
(2)
t
ACC
t
t
t
t
t
Address Valid to Output Valid
Chip EnableLow to Output Valid
CE
Output Enable Low to Output Valid E = V
OE
Chip EnableHigh to Output Hi-Z
DF
Output Enable High to Output Hi-Z
DF
Address Transition to Output
OH
Transition
E=V
G=V
G=V
E=V
E=V
,G=V
IL
IL
IL
,G=V
IL
IL
IL
180 200 ns
180 200 ns
80 90 ns
IL
0 50 0 70 ns
0 50 0 70 ns
00ns
IL
Figure 5. Read Mode AC Waveforms
A0-A17
tAVQV
VALID
tAXQX
VALID
Unit
E
tGLQV
G
tELQV
Q0-Q7
Programming
The M27V201 has been designed to be fully compatible withthe M27C2001and hasthe same electronic signature. As a result the M27V201 can be
programmed as the M27C2001 on the same programming equipments by applying 12.75V on V
PP
and 6.25V on VCCby the use of the same PRESTO II algorithm. When delivered (and after each
erasure for UV EPROM), all bits of the M27V201
are in the ’1’state.Data is introduced by selectively
programming ’0’s into the desired bit locations. Al-
tEHQZ
tGHQZ
Hi-Z
AI00719B
though only ’0’s will be programmed, both ’1’s and
’0’scan be present in the data word. The only way
to change a ’0’to a ’1’is by die exposition to ultraviolet light (UV EPROM). The M27V201 is in the
programming mode when VPPinput is at 12.75V,
EisatVILand P is pulsed to VIL. The data to be
programmed is applied to 8 bits in parallel to the
data output pins. The levels required for the address and data inputs are TTL. VCCis specified to
be 6.25V ±0.25V.
6/15
M27V201
Table 9. Programming Mode AC Characteristics
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
I
LI
I
CC
I
PP
V
IL
V
IH
V
OL
V
OH
V
ID
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics
Input Leakage Current
V
IL
≤ VIN≤ V
IH
±10 µA
Supply Current 50 mA
Program Current
E=V
IL
50 mA
Input Low Voltage –0.3 0.8 V
V
Input High Voltage 2
CC
+ 0.5
Output Low Voltage IOL= 2.1mA 0.4 V
I
Output High Voltage TTL
= –400µA
OH
2.4 V
A9 Voltage 11.5 12.5 V
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V
Symbol Alt Parameter Test Condition Min Max Unit
t
AVPL
t
QVPL
t
VPHPL
t
VCHPL
t
ELPL
t
PLPH
t
PHQX
t
QXGL
t
GLQV
(2)
t
GHQZ
t
GHAX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
t
t
t
VPS
t
VCS
t
CES
t
t
t
OES
t
t
DFP
t
Address Validto Program Low 2 µs
AS
Input Valid to Program Low 2 µs
DS
VPPHigh to Program Low
VCCHigh to Program Low
2 µs
2 µs
Chip Enable Low to Program Low 2 µs
Program Pulse Width 95 105 µs
PW
Program High to Input Transition 2 µs
DH
Input Transition to Output Enable Low 2 µs
Output Enable Low to Output Valid 100 ns
OE
Output Enable High to Output Hi-Z 0 130 ns
Output Enable High to Address
AH
Transition
0ns
V
7/15
M27V201
Figure 6. Programming and Verify Modes AC Waveforms
A0-A17
tAVPL
Q0-Q7
tQVPL
V
PP
tVPHPL
V
CC
tVCHPL
E
tELPL
P
tPLPH
G
Figure 7. Programming Flowchart
VCC= 6.25V, VPP= 12.75V
n=0
P = 100µs Pulse
NO
NO
VERIFY
YES
Last
NO
Addr
YES
CHECK ALL BYTES
1st: VCC=6V
2nd: VCC= 4.2V
++ Addr
YES
++n
=25
FAIL
VALID
DATA IN DATA OUT
tPHQX
tGLQV
tQXGL
PROGRAM VERIFY
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Programming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE at VCCmuch
higher than 3.6Vprovides thenecessary marginto
each programmed cell.
Program Inhibit
Programming of multiple M27V201s in parallel
with different data is also easily accomplished. Except for E,all like inputs including G of the parallel
M27V201 may be common.A TTL low level pulse
applied to a M27V201’s P input, with E low and
VPPat 12.75V, will program that M27V201. A high
level E input inhibits the other M27V201s from being programmed.
Program Verify
A verify (read) should be performed on the pro-
AI00715C
grammed bits to determine that they were correctly programmed. The verify is accomplished with E
and G at VIL, P at VIH,VPPat 12.75V and VCCat
6.25V.
tGHQZ
tGHAX
AI00720
8/15
M27V201
On-Board Programming
The M27V201 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically matchthe device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C ambient temperaturerange that is required when programming theM27V201. To activatethe ES mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27V201 with
VPP=VCC=5V. Two identifier bytes may then be
sequenced from the deviceoutputs by toggling address line A0 from VILto VIH. All other address
lines must be held at VILduring Electronic Signature mode. Byte 0 (A0=VIL) represents the manufacturer code and byte 1 (A0=VIH) the device
identifier code. For the STMicroelectronics
M27V201, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q0 to Q7.
Note that the M27V201 and M27C2001 have the
same identifier bytes.
ERASUREOPERATION(applies to UV EPROM)
The erasure characteristics of the M27V201 are
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Data
shows that constant exposure to room level fluorescent lighting could erase a typical M27V201 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27V201 is to be exposed to these
types of lighting conditions for extended periods of
time, itis suggested that opaque labelsbe put over
the M27V201 window to prevent unintentional erasure. The recommended erasure procedure for
the M27V201 is exposure to short wave ultraviolet
light which has wavelength of 2537 Å. The integrated dose (i.e. UV intensity xexposure time) for
erasure should be a minimum of 15 W-sec/cm2.
The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with
12000 µW/cm2power rating. The M27V201
should beplaced within 2.5 cm(1 inch) of the lamp
tubes during the erasure. Somelamps have a filter
on their tubes which should be removed before
erasure.
9/15
M27V201
Table 11. Ordering Information Scheme
Example: M27V201 -120 K 1 TR
Device Type
Speed
-120 = 120 ns
-150 = 150 ns
-180 = 180 ns
-200 = 200 ns
Package
F = FDIP32W
B = PDIP32
K = PLCC32
N = TSOP32: 8 x 20mm
Temperature Range
1 = –0 to 70 °C
6=–40to85°C
Options
TR = Tape& Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
10/15
M27V201
Table 12. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
Symb
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 41.73 42.04 1.643 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 0.125
S 1.52 2.49 0.060 0.098
∅ 7.11 – – 0.280 – –
α 4° 11° 4° 11°
N32 32
Typ Min Max Typ Min Max
mm inches
Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window,Package Outline
A2
B1 B e
A3A1A
L
α
C
eA
D2
eB
D
S
N
∅
1
Drawing is not to scale.
E1 E
FDIPW-a
11/15
M27V201
Table 13. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 41.78 42.04 1.645 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 15.24 – – 0.600 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.03 0.070 0.080
α 0° 10° 0° 10°
mm inches
N32 32
Figure 9. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline
A2A1A
L
B1 B e1
D2
α
C
eA
eB
D
S
N
E1 E
1
PDIP
Drawing is not to scale.
12/15
M27V201
Table 14. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data
Symb
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
Typ Min Max Typ Min Max
mm inches
Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline
D
D1
1N
Ne E1 E
F
D2/E2
A2
B
0.51 (.020)
1.14 (.045)
PLCC
Drawing is not to scale.
Nd
R
CP
A
A1
B1
e
13/15
M27V201
Table 15. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.15 0.002 0.007
A2 0.95 1.05 0.037 0.041
B 0.15 0.27 0.006 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 7.90 8.10 0.311 0.319
e 0.50 – – 0.020 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N32 32
CP 0.10 0.004
mm inches
Figure 11. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline
A2
1N
e
E
B
N/2
D1
D
DIE
A
CP
C
TSOP-a
Drawing is not to scale.
LA1 α
14/15
M27V201
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