SGS Thomson Microelectronics M27C512-90XN6TR, M27C512-90XN6, M27C512-90XN3TR, M27C512-90XN3, M27C512-90XN1TR Datasheet

512 Kbit (64Kb x8) UV EPROM and OTP EPROM

■ 5V ± 10% SUPPLY VOLTAGE in READ

OPERATION

■ ACCESS TIME: 45ns

■ LOW POWER “CMOS” CONSUMPTION:

– Active Current 30mA
– Standby Current 100µA

■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■ PROGRAMMING TIMES of AROUND 6sec.

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Device Code: 3Dh

DESCRIPTION

The M27C512 is a 512 Kbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for applica­tions where fast turn-around and pattern experi­mentation are important requirements and is
organized as 65,536 by 8 bits.

The FDIP28W (window ceramic frit-seal package)
has transparent lid which allows the user to ex­pose the chipto ultraviolet light to erase thebitpat­tern. A new pattern can then be written to the
device by following the programming procedure.

For applications wherethe content is programmed
only one time and erasure is not required, the
M27C512 is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.

28

1

FDIP28W (F) PDIP28 (B)

PLCC32 (C) TSOP28 (N)

28

Figure 1. Logic Diagram

V

CC

16

A0-A15

M27C512

1

8 x 13.4 mm

8

Q0-Q7

GV

PP

E

M27C512

V

SS

AI00761B

1/18April 2001

M27C512

Figure 2A. DIP Connections

A15 V

1

A12

2

A7

3

A6

4

A5

5

A4

6

A3

7
8
9
10
11
12
13
14

M27C512

A2
A1
A0

Q0

Q2
SS

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI00762

CC

A14
A13
A8
A9
A11
GV
A10
E
Q7
Q6
Q5Q1
Q4
Q3V

PP

Figure 2B. LCC Connections

A15

A6
A5
A4
A3
A2
A1
A0

NC

Q0

A7

9

Q1

DU

A12

1

M27C512

17

Q2

SS

DU

V

V

32

Q3

CC

A14

Q4

A13

25

Q5

A8
A9
A11
NC
GV
A10
E
Q7
Q6

AI00763

PP

Figure 2C. TSOP Connections

GV

A11

A13
A14

V

A15
A12

PP

A9
A8

CC

A7
A6
A5
A4
A3

22

28

M27C512

1

78

AI00764B

21

15
14

A10
E
Q7
Q6
Q5
Q4
Q3
V

SS

Q2
Q1
Q0
A0
A1
A2

Table 1. Signal Names

A0-A15 Address Inputs
Q0-Q7 Data Outputs
E Chip Enable
GV
V
V
NC
DU

PP

CC

SS

Output Enable / Program Supply
Supply Voltage
Ground
Not Connected Internally
Don’t Use

2/18

M27C512

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi­tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and otherrelevant qual­ity documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V

3. Depends on range.

Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC+2V for a period less than 20ns.

CC

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E

Read
Output Disable V
Program

V
Program Inhibit V
Standby
Electronic Signature

Note: X = VIHor VIL,VID= 12V ± 0.5V.

V

IL

IL

Pulse V

IL

IH

V

IH

V

IL

GV

V

PP

V

IL

V

IH

PP

PP

A9 Q7-Q0

X Data Out
X Hi-Z
XDataIn
X Hi-Z

X X Hi-Z

V

IL

V

ID

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code
Device Code

V

IL

V

IH

00100000 20h
00111101 3Dh

3/18

M27C512

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. Testing Input Output Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% tested.

Input Capacitance
Output Capacitance

(1)

(TA=25°C, f = 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE
UNDER

TEST

C

L

CL= 30pF for High Speed
CL= 100pF for Standard
CLincludes JIG capacitance

V

V

IN

OUT

=0V

=0V

6pF

12 pF

OUT

AI01823B

DEVICE OPERATION

The modes of operations of the M27C512 are list­ed in the Operating Modes table. A single power
supply is required in the read mode. All inputs are
TTL levels except for GVPPand 12V on A9 for
Electronic Signature.

Read Mode

The M27C512 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable(G) is the output control and should
be used to gate data to the output pins, indepen­dent of device selection. Assuming that the ad-

4/18

dresses are stable, the address access time
(t

) is equal to the delay from E to output

AVQV

(t

). Data is availableat the output after a delay

ELQV

of t

from the falling edge of G, assuming that

GLQV

E has been low and the addresses have been sta­ble for at least t

AVQV-tGLQV

.

Standby Mode

The M27C512 has a standby mode which reduces
the active current from 30mA to 100µA The
M27C512 is placed in the standby mode by apply­ing aCMOS highsignal to the Einput. When in the
standby mode, the outputs are in a high imped­ance state, independent of the GVPPinput.

M27C512

Table 7. Read Mode DC Characteristics

(1)

(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC=5V±5% or 5V ± 10%; VPP=VCC)

Symbol Parameter Test Condition Min Max Unit

I

I

I

CC

I

CC1

I

CC2

I
V

V

IH

V

V

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Table 8A. Read Mode AC Characteristics

Input Leakage Current 0V ≤ VIN≤ V

LI

Output Leakage Current 0V ≤ V

LO

Supply Current

Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current

PP

Input Low Voltage –0.3 0.8 V

IL

(2)

Input High Voltage 2
Output Low Voltage

OL

Output High Voltage TTL

OH

Output High Voltage CMOS

2. Maximum DC voltage on Output is V

CC

+0.5V.

(1)

E=V

= 0mA, f = 5MHz

I

OUT

E=V

E>V

V

PP=VCC

I

OL

I

OH

I

= –100µAV

OH

≤ V

OUT

,G=VIL,

IL

IH

– 0.2V

CC

= 2.1mA

= –1mA

CC

CC

3.6 V
– 0.7V

CC

±10 µA
±10 µA

30 mA

1mA

100 µA

10 µA

V

+1

CC

0.4 V

(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC=5V±5% or 5V ± 10%; VPP=VCC)

M27C512

Symbol Alt Parameter Test Condition

-45

(3)

Min Max Min Max Min Max Min Max

t

AVQVtACC

t

ELQV

t

GLQV

(2)

t

EHQZ

(2)

t

GHQZ

t

AXQX

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

3. Speed obtained with High Speed AC measurement conditions.

Address Valid to
Output Valid

Chip Enable Low to

t

CE

Output Valid
Output Enable Low

t

OE

to Output Valid
Chip Enable High to

t

DF

Output Hi-Z
Output Enable High

t

DF

to Output Hi-Z
Address Transition to

t

OH

Output Transition

E=V

E=V

,G=V

IL

G=V

E=V

G=V

E=V

,G=V

IL

IL

IL

IL

IL

IL

IL

45 60 70 80 ns

45 60 70 80 ns

25 30 35 40 ns

0 25 0 25 0 30 0 30 ns

0 25 0 25 0 30 0 30 ns

0000ns

-60 -70 -80

V

V

Unit

5/18

M27C512

Table 8B. Read Mode AC Characteristics

(1)

(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC=5V±5% or 5V ± 10%; VPP=VCC)

M27C512

Symbol Alt Parameter Test Condition

-90

-10 -12 -15/-20/-25

Min Max Min Max Min Max Min Max

t

AVQVtACC

t

ELQV

t

GLQV

(2)

t

EHQZ

(2)

t

GHQZ

t

AXQX

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

Address Valid to
Output Valid

Chip Enable Low to

t

CE

Output Valid
Output Enable Low

t

OE

to Output Valid
Chip Enable High to

t

DF

Output Hi-Z
Output Enable High

t

DF

to Output Hi-Z
Address Transition to

t

OH

Output Transition

E=V

E=V

,G=V

IL

G=V

E=V

G=V

E=V

,G=V

IL

IL

IL

IL

IL

IL

IL

90 100 120 150 ns

90 100 120 150 ns

40 40 50 60 ns

0 30 0 30 0 40 0 50 ns

0 30 0 30 0 40 0 50 ns

0000ns

Figure 5. Read Mode AC Waveforms

Unit

A0-A15

E

G

Q0-Q7

tAVQV

tELQV

VALID

tGLQV

VALID

tAXQX

tEHQZ

tGHQZ

Hi-Z

AI00735B

6/18

M27C512

Table 9. Programming Mode DC Characteristics

(1)

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)

Symbol Parameter Test Condition Min Max Unit

I

LI

I

CC

I

PP

V

IL

V

IH

V

OL

V

OH

V

ID

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Input Leakage Current
Supply Current 50 mA
Program Current
Input Low Voltage –0.3 0.8 V
Input High Voltage 2 VCC+ 0.5 V
Output Low Voltage
Output High Voltage TTL IOH= –1mA 3.6 V
A9 Voltage 11.5 12.5 V

Two Line Output Control

Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con­trol function which accommodates the use of mul­tiple memory connection. The two line control
function allows:

a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control
lines, E should be decoded and used as the prima­ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system controlbus. This ensures that all deselect­ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.

V

≤ VIN≤ V

IL

E=V

I

= 2.1mA

OL

IH

IL

±10 µA

50 mA

0.4 V

System Considerations

The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg­ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges ofE. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.The associated transient voltage peaks
can be suppressed by complying with the two line
output controlandby properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram­ic capacitorbe used on every device betweenV
and VSS. This should be a high frequency capaci­tor of low inherent inductance and should be
placed as close to the device as possible. In addi­tion, a 4.7µF bulk electrolytic capacitor should be
used between VCCand VSSfor every eight devic­es. The bulk capacitor should be located near the
power supplyconnection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.

CC

7/18

M27C512

Table 10. MARGIN MODE AC Characteristics

(1)

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)

Symbol Alt Parameter Test Condition Min Max Unit

t

A9HVPH

t

VPHEL

t

A10HEH

t

A10LEH

t

EXA10X

t

EXVPX

t

VPXA9X

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after V

t
t

t

AS10VA10

t

AS10VA10

t

AH10

t
t

VA9High to VPPHigh

AS9

VPPHigh to Chip Enable Low

VPS

Chip Enable Transition to V
Chip Enable Transition to VPPTransition

VPH

VPPTransition to VA9Transition 2 µs

AH9

High to Chip Enable High (Set)
Low to Chip Enable High (Reset)

Transition 1 µs

A10

2 µs
2 µs
1 µs
1 µs

2 µs

PP.

Figure 6. MARGIN MODE AC Waveforms

V

CC

A8

A9

GV

PP

E

A10 Set

A10 Reset

Note: A8 High level = 5V; A9 High level = 12V.

tA9HVPH tVPXA9X

tVPHEL

tEXVPX

tA10HEH

tA10LEH

tEXA10X

AI00736B

8/18

M27C512

Table 11. Programming Mode AC Characteristics

(1)

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)

Symbol Alt Parameter Test Condition Min Max Unit

t

AVEL

t

QVEL

t

VCHEL

t

VPHEL

t

VPLVPH

t

ELEH

t

EHQX

t

EHVPX

t

VPLEL

t

ELQV

(2)

t

EHQZ

t

EHAX

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

t
t

t

VCS

t

OES

t

PRT

t

t

t

OEH

t
t

t

DFP

t

Address Valid to Chip Enable Low 2 µs

AS

Input Valid to Chip Enable Low 2 µs

DS

VCCHigh to Chip Enable Low
VPPHigh to Chip Enable Low

2 µs

2 µs
VPPRise Time 50 ns
Chip Enable Program Pulse Width (Initial) 95 105 µs

PW

Chip Enable High to Input Transition 2 µs

DH

Chip Enable High to VPPTransition
VPPLow to Chip Enable Low

VR

Chip Enable Low to Output Valid 1 µs

DV

2 µs

2 µs

Chip Enable High to Output Hi-Z 0 130 ns
Chip Enable High to Address Transition 0 ns

AH

Programming

When delivered (and after each erasure for UV
EPROM), all bits of the M27C512 are in the ’1’
state. Data is introduced by selectively program­ming ’0’s into the desired bit locations. Although
only ’0’s will be programmed, both ’1’s and ’0’s can
be present in the data word. The only way to
change a ’0’to a’1’is by die exposure to ultraviolet
light (UV EPROM). The M27C512 is in the pro­gramming mode when VPPinput is at 12.75V and

E is pulsed to VIL. The data to be programmed is
applied to 8 bits in parallel tothe data output pins.
The levels required for the address and data in­puts are TTL. VCCis specified to be 6.25V ±

0.25V. The M27C512 can use PRESTO IIB Pro­gramming Algorithm that drastically reduces the
programming time (typically less than 6 seconds).
Nevertheless to achieve compatibility with all pro­gramming equipments, PRESTO Programming
Algorithm can be used as well.

9/18

M27C512

Figure 7. Programming and Verify Modes AC Waveforms

A0-A15

tAVEL

Q0-Q7

tQVEL

V

CC

tVCHEL

GV

PP

tVPHEL

E

Figure 8. Programming Flowchart

VCC= 6.25V, VPP= 12.75V

SET MARGIN MODE

n=0

E = 100µs Pulse

NO

NO

VERIFY

YES

Last

NO

Addr

YES

RESET MARGINMODE

CHECK ALL BYTES

1st: VCC=6V

2nd: VCC= 4.2V

++ Addr

YES

++n

=25

FAIL

DATA IN

AI00738B

tELEH

PROGRAM

VALID

tEHAX

DATA OUT

tEHQX

tELQV

tEHVPX

tVPLEL

VERIFY

tEHQZ

AI00737

PRESTO IIB Programming Algorithm

PRESTO IIB Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 6.5 seconds. This can
be achieved with STMicroelectronics M27C512
due to several design innovations described in the
M27C512 datasheet to improve programming effi­ciency and to provide adequate margin for reliabil­ity. Before starting the programming the internal
MARGIN MODE circuit is set in order to guarantee
that each cell is programmed with enough margin.
Then a sequence of 100µs program pulses are ap­plied to each byte until a correct verify occurs. No
overprogram pulses are applied since the verify in
MARGIN MODE provides the necessary margin.

Program Inhibit

Programming of multiple M27C512s in parallel
with different data is also easily accomplished. Ex­cept for E, all like inputs including GVPPof thepar­allel M27C512 may be common. A TTL low level
pulse applied to a M27C512’s E input, with VPPat

12.75V, will program that M27C512. A high level E
input inhibits the other M27C512s from being pro­grammed.

Program Verify

A verify (read) should be performed on the pro­grammed bits to determine that they were correct­ly programmed. The verify is accomplished with G
at VIL. Data should be verified with t

ELQV

after the

falling edge of E.

10/18

M27C512

Electronic Signature

The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am­bient temperaturerange that is required when pro­gramming the M27C512. To activate the ES
mode, the programming equipment must force

11.5V to 12.5V on address line A9 of the
M27C512. Two identifier bytes may then be se­quenced from the device outputs by toggling ad­dress line A0 from VILto VIH. All other address
lines must be held at VILduring Electronic Signa­ture mode. Byte 0 (A0 = VIL) represents the man­ufacturer code and byte 1 (A0 = VIH) the device
identifier code. For the STMicroelectronics
M27C512, these two identifier bytes are given in
Table 4and can be read-out on outputs Q7 to Q0.

ERASURE OPERATION(appliesfor UV EPROM)

The erasure characteristics of the M27C512 is
such that erasure begins when the cells are ex­posed to light with wavelengths shorter than ap­proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range.

Research shows that constant exposure to room
level fluorescent lighting could erase a typical
M27C512 in about 3 years, while it would take ap­proximately 1 week to cause erasure when ex­posed to direct sunlight. If the M27C512 is to be
exposed to these types of lighting conditions for
extended periods of time, it is suggested that
opaque labelsbe put over the M27C512 window to
prevent unintentional erasure. The recommended
erasureprocedure for the M27C512 is exposureto
short wave ultraviolet light which has wavelength
2537 Å. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of 15 W-sec/cm2. The erasure time with this dos­age is approximately 15 to 20 minutes using an ul­traviolet lamp with 12000 µW/cm2power rating.
The M27C512 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.

11/18

M27C512

Table 12. Ordering Information Scheme

Example: M27C512 -70 X C 1 TR

Device Type

M27

Supply Voltage

C=5V

Device Function

512 = 512 Kbit (64Kb x8)

Speed

(1)

=45ns

-45

-60 = 60 ns

-70 = 70 ns

-80 = 80 ns

-90 = 90 ns

-10 = 100 ns

-12 = 120 ns

-15 = 150 ns

-20 = 200 ns

-25 = 250 ns

Tolerance

V

CC

blank = ± 10%
X=±5%

Package

F = FDIP28W
B = PDIP28
C = PLCC32
N = TSOP28: 8 x 13.4 mm

Temperature Range

1=0to70°C
3 = –40 to 125 °C
6=–40to85°C

Options

X = Additional Burn-in
TR = Tape& Reel Packing

Note: 1. High Speed, see AC Characteristics section for further information.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de­vice, please contact the STMicroelectronics Sales Office nearest to you.

12/18

Table 13. Revision History

Date Revision Details

November 1998 First Issue
09/25/00 AN620 Reference removed
04/02/01 FDIP28W mechanical dimensions changed (Table 14)

M27C512

13/18

M27C512

Table 14. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data

Symbol

A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177

B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –

C 0.23 0.30 0.009 0.012
D 36.50 37.34 1.437 1.470

D2 33.02 – – 1.300 – –

E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526

e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710

L 3.18 4.10 0.125 0.161

S 1.52 2.49 0.060 0.098

∅ 7.11 – – 0.280 – –

α 4° 11° 4° 11°

N28 28

Typ Min Max Typ Min Max

millimeters inches

Figure 9. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline

A2

B1 B e

A3A1A

L

α

C

eA

D2

eB

D

S

N

∅

1

Drawing is not to scale.

E1 E

FDIPW-a

14/18

Table 15. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data

millimeters inches

Symbol

Typ Min Max Typ Min Max

A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160

B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –

C 0.20 0.30 0.008 0.012
D 36.83 37.34 1.450 1.470

D2 33.02 – – 1.300 – –

E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545

e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135
S 1.78 2.08 0.070 0.082
α 0° 10° 0° 10°

M27C512

N28 28

Figure 10. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline

A2A1A

L

B1 B e1

D2

α

C

eA

eB

D

S

N

E1 E

1

PDIP

Drawing is not to scale.

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M27C512

Table 16. PLCC32 - 32lead Plastic Leaded Chip Carrier, Package Mechanical Data

Symbol

A 2.54 3.56 0.100 0.140

A1 1.52 2.41 0.060 0.095
A2 0.38 0.015

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

D 12.32 12.57 0.485 0.495

D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430

e 1.27 0.050

E 14.86 15.11 0.585 0.595

E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530

F 0.00 0.25 0.000 0.010
R 0.89 0.035
N32 32

Nd 7 7
Ne 9 9

CP 0.10 0.004

Typ Min Max Typ Min Max

millimeters inches

Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline

D

D1

1N

Ne E1 E

F

D2/E2

0.51 (.020)

1.14 (.045)

Nd

R

PLCC

Drawing is not to scale.

A1

A2

B1

e

B

A

CP

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Table 17. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.25 0.049
A1 0.20 0.008
A2 0.95 1.15 0.037 0.045

B 0.17 0.27 0.007 0.011

C 0.10 0.21 0.004 0.008
D 13.20 13.60 0.520 0.535

D1 11.70 11.90 0.461 0.469

E 7.90 8.10 0.311 0.319

e 0.55 – – 0.022 – –

L 0.50 0.70 0.020 0.028

α 0° 5° 0° 5°

N28 28

CP 0.10 0.004

millimeters inches

Figure 12. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Outline

A2

22

21

e

28

1

E

B

78

D1

D

DIE

A

CP

C

TSOP-c

Drawing is not to scale

LA1 α

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