SGS Thomson Microelectronics M27C4001-90XN6X, M27C4001-90XN6TR, M27C4001-90XN1X, M27C4001-90XN1TR, M27C4001-90XL6X Datasheet
...
4 Mbit (512Kb x 8) UV EPROM and OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ ACCESS TIME: 35ns
■ LOW POWERCONSUMPTION:
– Active Current 30mA at 5MHz
– Standby Current 100µA
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 41h
DESCRIPTION
The M27C4001 is a 4 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for microprocessor systems requiring large programs and
is organised as 524,288 by 8 bits.
The FDIP32W (window ceramic frit-seal package)
and LCCC32W (leadless chip carrier package)
have a transparent lid which allow the user to expose the chipto ultraviolet lighttoerase the bitpattern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C4001 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
M27C4001
32
1
FDIP32W (F)
LCCC32W (L)
PLCC32 (C)
Figure 1. Logic Diagram
V
19
A0-A18 Q0-Q7
CC
32
V
PP
1
PDIP32 (B)
TSOP32 (N)
8 x 20 mm
8
E
G
M27C4001
V
SS
AI00721B
1/17November 2000
M27C4001
Figure 2A. DIP Connections
V
1
PP
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
A2
A1
A0
Q0
Q2
SS
M27C4001
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AI00722
V
CC
A18A16
A17
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
Figure 2B. LCC Connections
A16
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A12
9
Q1
VPPV
A15
1
32
M27C4001
17
Q2
Q3
SS
V
Q4
CC
A18
Q5
A17
25
Q6
A14
A13
A8
A9
A11
G
A10
E
Q7
AI00723
Figure 2C. TSOP Connections
A11 G
A9
A8
A13
A14
A17
A18
V
CC
V
PP
A16
A15
A12
A7
A6
A5
A4 A3
1
M27C4001
8
(Normal)
9
16 17
AI01155B
32
25
24
A10
E
Q7
Q6
Q5
Q4
Q3
V
SS
Q2
Q1
Q0
A0
A1
A2
Table 1. Signal Names
A0-A18 Address Inputs
Q0-Q7 Data Outputs
E Chip Enable
G Output Enable
V
PP
V
CC
V
SS
Program Supply
Supply Voltage
Ground
2/17
M27C4001
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure toAbsolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Outputis V
3. Depends on range.
Table 3. Operating Modes
Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC+2V for a period less than20ns.
CC
(1)
Mode E G A9
Read
Output Disable V
Program
Verify V
Program Inhibit
Standby
Electronic Signature
Note: 1. X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
V
Pulse V
IL
IH
V
IH
V
IH
V
IL
(3)
V
IL
V
IH
IH
V
IL
V
IH
X
XV
X
XVPPData Out
X
XX
V
IL
V
ID
–40 to 125 °C
V
pp
V
or V
CC
SS
or V
CC
SS
V
PP
V
PP
V
or V
CC
SS
V
CC
Q7 - Q0
Data Out
Hi-Z
Data In
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
Electronic Signature
V
IL
V
IH
00100000 20h
01000001 41h
3/17
M27C4001
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4 to2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8 and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: 1. Sampled only, not 100% tested.
(1)
(TA=25°C, f =1 MHz)
Input Capacitance
Output Capacitance
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
DEVICE
UNDER
TEST
CL= 30pF for High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
V
=0V
IN
V
=0V
OUT
1N914
3.3kΩ
C
L
6pF
12 pF
OUT
AI01823B
DEVICE OPERATION
The operating modes of the M27C4001 are listed
in the Operating Modes table. A single powersupply is required in the read mode. All inputs areTTL
levels except for VPPand 12Von A9 for Electronic
Signature.
Read Mode
The M27C4001 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, independent of device selection. Assuming that the ad-
4/17
dresses are stable, the address access time
(t
) is equal to the delay from E to output
AVQV
(t
). Datais available at the output after a delay
ELQV
of t
from the falling edge of G, assuming that
GLQV
E has been low and the addresses have been stable for at least t
AVQV-tGLQV
.
Standby Mode
The M27C4001 hasa standbymode whichreduces the supply current from 30mA to 100µA. The
M27C4001 is placed in the standby mode by applying a CMOS high signal to the E input.When in
the standby mode, the outputs are in a high impedance state, independent of the G input.
M27C4001
Table 7. Read Mode DC Characteristics
(1)
(TA= 0 to 70 °C or –40 to 85 °C; VCC=5V±5% or 5V ± 10%; VPP=VCC)
Symbol Parameter Test Condition Min Max Unit
I
I
LO
I
CC
I
CC1
I
CC2
I
PP
V
V
IH
V
V
OH
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Maximum DC voltage on Output is V
Table 8A. Read Mode AC Characteristics
Input Leakage Current
LI
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage –0.3 0.8 V
IL
(2)
Input High Voltage 2
Output Low Voltage
OL
Output High Voltage TTL
Output High Voltage CMOS
+0.5V.
CC
(1)
0V ≤ V
0V ≤ V
OUT
E=V
IL
= 0mA, f = 5MHz
I
OUT
E=V
E>V
CC
V
PP=VCC
I
= 2.1mA
OL
I
= –400µA
OH
= –100µAV
I
OH
≤ V
IN
CC
≤ V
CC
,G=VIL,
IH
– 0.2V
±10 µA
±10 µA
30 mA
1mA
100 µA
10 µA
V
+1
CC
0.4 V
2.4 V
– 0.7V
CC
(TA= 0 to 70 °C or –40 to 85 °C; VCC=5V±5% or 5V ± 10%; VPP=VCC)
M27C4001
Symbol Alt Parameter Test Condition
-35
(3)
Min Max Min Max Min Max
t
AVQV
t
ELQV
t
GLQV
(2)
t
EHQZ
(2)
t
GHQZ
t
AXQX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after V
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Address Valid to
t
ACC
Output Valid
Chip Enable Low to
t
CE
Output Valid
Output Enable Low to
t
OE
Output Valid
Chip Enable High to
t
DF
Output Hi-Z
Output Enable High to
t
DF
Output Hi-Z
Address Transition to
t
OH
Output Transition
E=V
E=V
,G=V
IL
G=V
E=V
G=V
E=V
,G=V
IL
IL
IL
IL
IL
IL
IL
35 45 55 ns
35 45 55 ns
20 25 30 ns
030030030ns
030030030ns
000ns
-45
PP
(3)
-55
(3)
V
V
Unit
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decoded and used as theprimary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselected memory devices are intheir low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
5/17
M27C4001
Table 8B. Read Mode AC Characteristics
(1)
(TA= 0 to 70 °C or –40 to 85 °C; VCC=5V±5% or 5V ± 10%; VPP=VCC)
M27C4001
Symbol Alt Parameter Test Condition
Min Max Min Max Min Max
t
AVQV
t
ELQV
t
GLQV
(2)
t
EHQZ
(2)
t
GHQZ
t
AXQX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
Address Valid to
t
ACC
Output Valid
Chip Enable Low to
t
CE
Output Valid
Output Enable Low to
t
OE
Output Valid
Chip Enable High to
t
DF
Output Hi-Z
Output Enable High to
t
DF
Output Hi-Z
Address Transition to
t
OH
Output Transition
E=V
E=V
,G=V
IL
G=V
E=V
G=V
E=V
,G=V
IL
IL
IL
IL
IL
IL
IL
70 80 100 ns
70 80 100 ns
35 40 50 ns
0 30 0 30 0 30 ns
0 30 0 30 0 30 ns
000ns
Figure 5. Read Mode AC Waveforms
Unit-70 -80/-90 -10/-12/-15
A0-A18
E
G
Q0-Q7
VALID
tAVQV
tGLQV
tELQV
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs requirecareful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitudeof
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can besuppressed bycomplying with the two line
VALID
tAXQX
tEHQZ
tGHQZ
Hi-Z
AI00724B
outputcontrol and by properly selected decoupling
capacitors.It is recommended that a 0.1µF ceram-
ic capacitorbe used on every device between V
CC
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
placed as close to the device aspossible. In addition, a 4.7µF bulk electrolytic capacitor should be
used between VCCand VSSfor every eight devices. The bulk capacitor should be located near the
power supply connection point. The purposeof the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
6/17
M27C4001
Table 9. Programming Mode DC Characteristics
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
I
I
CC
I
PP
V
V
V
V
OH
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Input Leakage Current
LI
Supply Current 50 mA
Program Current
Input Low Voltage –0.3 0.8 V
IL
Input High Voltage 2 VCC+ 0.5 V
IH
Output Low Voltage
OL
Output High Voltage TTL IOH= –400µA 2.4 V
A9 Voltage 11.5 12.5 V
ID
Table 10. Programming Mode AC Characteristics
0 ≤ V
I
OL
(1)
≤ V
IN
E=V
= 2.1mA
CC
IL
±10 µA
50 mA
0.4 V
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
t
AVEL
t
QVEL
t
VPHEL
t
VCHEL
t
ELEH
t
EHQX
t
QXGL
t
GLQV
t
GHQZ
t
GHAX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
t
t
t
t
t
t
t
t
Address Validto Chip Enable Low 2 µs
AS
t
Input Valid to Chip Enable Low 2 µs
DS
VPPHigh to Chip Enable Low
VPS
VCCHigh to Chip Enable Low
VCS
Chip Enable Program Pulse Width 95 105 µs
PW
Chip Enable High toInput
DH
Transition
Input Transition to Output Enable
OES
Low
Output Enable Low to Output Valid 100 ns
OE
Output Enable High to Output Hi-Z 0 130 ns
DFP
Output Enable High to Address
t
AH
Transition
2 µs
2 µs
2 µs
2 µs
0ns
Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M27C4001 are in the ’1’
state. Data is introduced by selectively programming ’0’s into the desired bit locations. Although
only ’0’swill be programmed, both ’1’s and ’0’s can
be present in the data word. The only way to
change a ’0’to a’1’is by die exposure to ultraviolet
light (UV EPROM). The M27C4001 is in the programming mode when VPPinput is at12.75V, G is
at VIHand E is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data
output pins. The levels required for the address
and data inputs are TTL. VCCis specified to be
6.25V ± 0.25V.
7/17
M27C4001
Figure 6. Programming and Verify Modes AC Waveforms
A0-A18
tAVPL
Q0-Q7
tQVEL
V
PP
tVPHEL
V
CC
tVCHEL
E
tELEH
G
Figure 7. Programming Flowchart
VCC= 6.25V, VPP= 12.75V
n=0
E = 100µs Pulse
NO
NO
VERIFY
YES
Last
NO
Addr
YES
CHECK ALL BYTES
1st: VCC=6V
2nd: VCC= 4.2V
++ Addr
YES
++n
=25
FAIL
VALID
DATA IN DATA OUT
tEHQX
tGLQV
tQXGL
PROGRAM VERIFY
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 52.5 seconds. Programming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7).During
programming and verify operation, a MARGIN
MODE circuit is automatically activatedin order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides the
necessary margin to each programmed cell.
Program Inhibit
Programming of multiple M27C4001s in parallel
with different data is also easily accomplished.Except for E, all likeinputs including G of theparallel
M27C4001 may be common. A TTL low level
pulse applied to a M27C4001’s E input, with V
at 12.75V, will program that M27C4001. A high
level E input inhibits the other M27C4001s from
being programmed.
Program Verify
AI00760B
A verify (read) should be performed on the programmed bits to determine that theywere correctly programmed. The verify is accomplished with G
at VIL, E at VIH,VPPat 12.75V and VCCat 6.25V.
tGHQZ
tGHAX
AI00725
PP
8/17
M27C4001
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code froman EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically matchthe deviceto be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C ambient temperaturerange that is required when programming the M27C4001. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
M27C4001 with VPP=VCC= 5V. Two identifier
bytes maythen be sequenced from the device outputs bytoggling address line A0from VILtoVIH. All
other address lines must be held at VILduring
Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1
(A0 = VIH) the device identifier code. For the
STMicroelectronics M27C4001,these two identifier bytes are given in Table 4 and can be read-out
on outputs Q7 to Q0.
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristics of the M27C4001 are
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Data
shows that constant exposure to room level fluorescent lighting could erase atypical M27C4001 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C4001 is to be exposed to
these types of lighting conditions for extended periods of time, it is suggested that opaquelabels be
put over the M27C4001 window to prevent unintentional erasure. The recommended erasure procedure for the M27C4001 is exposure to short
wave ultraviolet light which has wavelength of
2537 Å. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of 15 W-sec/cm2. The erasure time with this dosage is approximately 15to 20 minutes using an ultraviolet lamp with 12000 µW/cm2power rating.
The M27C4001 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
9/17
M27C4001
Table 11. Ordering Information Scheme
Example: M27C4001 -45 X C 1 TR
Device Type
M27
SupplyVoltage
C=5V
Device Function
4001 = 4 Mbit (512Kb x 8)
Speed
(1)
=35ns
-35
(1)
-45
=45ns
(1)
-55
=55ns
-70 = 70 ns
-80 = 80 ns
-90 = 90 ns
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
Tolerance
V
CC
blank = ± 10%
X=±5%
Package
F = FDIP32W
L = LCCC32W
B = PDIP32
C = PLCC32
N = TSOP32: 8 x 20 mm
Temperature Range
1=0to70°C
6=–40to85°C
Options
X = Additional Burn-in
TR = Tape & Reel Packing
Note: 1. High Speed, seeAC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contactthe STMicroelectronics Sales Office nearest to you.
10/17
Table 12. Revision History
Date Revision Details
July 1998 First Issue
09/25/00 AN620 Reference removed
11/29/00 PLCC codification changed (Table 11)
M27C4001
11/17
M27C4001
Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
Symbol
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 41.73 42.04 1.643 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 0.125
S 1.52 2.49 0.060 0.098
Ø 7.11 – – 0.280 – –
α 4° 11° 4° 11°
N32 32
Typ Min Max Typ Min Max
millimeters inches
Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Outline
A2
B1 B e
A3A1A
L
α
C
eA
D2
eB
D
S
N
∅
1
Drawing is not to scale.
E1 E
FDIPW-a
12/17
M27C4001
Table 14. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 41.78 42.04 1.645 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 15.24 – – 0.600 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.03 0.070 0.080
α 0° 10° 0° 10°
N32 32
millimeters inches
Figure 9. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline
A2A1A
L
B1 B e1
D2
α
eA
eB
D
S
N
E1 E
1
Drawing is not to scale.
C
PDIP
13/17
M27C4001
Table 15. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 2.80 0.110
B 0.51 0.71 0.020 0.028
D 11.53 11.63 0.442 0.458
E 13.72 14.22 0.540 0.560
e 1.27 – – 0.050 – –
e1 0.39 – 0.015 –
e2 7.62 – – 0.300 – –
e3 10.16 – – 0.400 – –
h 1.02 – – 0.040 – –
j 0.51 – – 0.020 – –
L 1.14 1.40 0.045 0.055
L1 1.96 2.36 0.077 0.093
K 10.50 10.80 0.413 0.425
K1 8.03 8.23 0.316 0.324
N32 32
millimeters inches
Figure 10. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, Package Outline
e2
D
EK
e3
e
N
1
e1
K1
A
LCCCW-a
Drawing is not to scale.
o
jx45
L1
B
Lhx45
o
14/17
M27C4001
Table 16. PLCC32 - 32lead Plastic Leaded Chip Carrier, Package Mechanical Data
Symbol
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 0.38 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
e 1.27 0.050
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
F 0.00 0.25 0.000 0.010
R 0.89 0.035
N32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
Typ Min Max Typ Min Max
millimeters inches
Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline
D
D1
1N
Ne E1 E
F
D2/E2
0.51 (.020)
1.14 (.045)
Nd
R
PLCC
Drawing is not to scale.
A1
A2
B1
e
B
A
CP
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M27C4001
Table 17. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.17 0.002 0.006
A2 0.95 1.05 0.037 0.041
B 0.15 0.27 0.006 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 7.90 8.10 0.311 0.319
e 0.50 – – 0.020 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N32 32
CP 0.10 0.004
millimeters inches
Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1N
e
E
B
N/2
D1
D
DIE
A
CP
C
TSOP-a
Drawing is not to scale.
LA1 α
16/17
M27C4001
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