1 Mbit Low Voltage Paged Flash Memory
With 20 MHz Serial SPI Bus Interface
■ 1 Mbit PAGED Flash Memory
■ 128 BYTE PAGE PROGRAM IN 3 ms TYPICAL
■ 256 Kbit SECTOR ERASE IN 1 s TYPICAL
■ BULK ERASE IN 2 s TYPICAL
■ SINGLE 2.7 V to 3.6 V SUPPLY VOLTAGE
■ SPI BUS COMPATIBLE SERIAL INTERFACE
■ 20 MHz CLOCK RATE AVAILABLE
■ SUPPORTS POSITIVE CLOCK SPI MODES
■ DEEP POWER DOWN MODE (1 µA TYPICAL)
■ ELECTRONIC SIGNATURE
■ 10,000 ERASE/PROG CYCLES PER SECTOR
■ 20 YEARS DATA RETENTI ON
■ –40 TO 85°C TEMPERATURE RANGE
DESCRIPTION
The M25P10 is an 1 Mbit Paged Flash M emory
fabricated with STMicroelectronics High
Endurance CMOS technology. The memory is
accessed by a simple SPI bus compatible serial
interface. The bus sign als are a s erial clock input
(C), a serial data input (D) and a serial data output
(Q).
The device connected to the bus is selected when
the chip select input (S
in during the low to high transition of clock C, data
) goes low. Data is clocked
8
SO8 (MN)
150 mil width
8
SO8 (MW)
200 mil width
Figure 1. Logic Diagram
V
CC
M25P10
PRELIMINARY DATA
1
1
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S
W
Write Protect
Hold
HOLD
V
CC
V
SS
June 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Chip Select
Supply Voltage
Ground
W
HOLD
D
C
S
M25P10
V
SS
Q
AI03744
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M25P10
Figure 2. SO Connections
M25P10
1
SV
2
3
W
SS
4
8
7
6
5
AI03745
CC
HOLDQ
C
DV
is clocked out duri ng the high to low transition of
clock C
SIGNALS DESCRIPTION
Seria l O utput ( Q )
The output pin is used to transfer data serially out
of the memory. Data is shifted out on the falling
edge of the serial clock.
Serial Inpu t ( D )
The input pin is used to transfer data serially into
the device. It receives instructions, addresses,
and the data to be program med. Input is latched
on the rising edge of the serial clock.
Serial Clock (C)
The serial clock provides the timing of the serial
interface. Instructions, addresses, or data present
at the input pin are latched o n the rising edge of
the clock input, while data on the Q pin changes
after the falling edge of the clock input.
Chip Select (S
When S
is high, the memory is deselected and the
)
Q output pin is at high impedance a nd, unless an
internal Read, Program, Erase or Write Status
Register operation is underway, the device will be
in the Standby Power mode (this is not the Deep
Power Down mode). S
low enables the memory,
placing it in the active power mode. It should be
noted that after power-on, a high to low t ransition
is required prior to the start of any operation.
on S
Hold (HOLD
)
The HOLD pin is used to pause serial
communications with a SPI memory without
resetting the serial sequence. To take the Hold
condition into account, the product must be
selected. The HOLD condition is validated by a 0
state on the Hold pin synchronized with the 0 state
on the Clock, as shown in Figure 4. The DeHOLD
condition is validated by a 1 state on the Hold pin
synchronized with the 0 state on the Clock. During
the Hold condition D, Q, and C are at a high
impedance state.
When the memory is under HOLD condition, it is
possible to deselect the device. Then, the protocol
is reset. The memory remains on HOLD as long as
the Hold pin is Low. To restart communication with
the device, it is necessary t o both DeHOLD (H =
1) and to SELECT the memory.
Write Protect (W
)
This pin is for hardware write protection of the
Status Register (SR); except WIP and WEL bits.
When bit 7 (SRWD) of the status register is 0 (the
initial delivery state); it is possible to write the S R
once the WEL (Write Enable Latch) has been set
with the WREN instruction and whatever is the
status of pin W
(high or low).
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Note: 1. Exc ept for the ratin g “Ambie nt Operati ng Temperat ure Range”, stresses abov e those liste d in this table may cause perman ent
2/21
damage to the dev ice. T hese are stress r atings only, a nd ope ration of the dev ice at t hese or any o ther co ndition s above those
indicated in the Operating se ctions of this s pecification is no t implied. Expos ure to Absolute M aximum Rating co nditions for
extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL -STD-883C, 3015.7 (1 00 pF, 1500 Ω)
Ambient Operating Temperature –40 to 85 °C
Storage Temperature –65 to 150 °C
Lead Temperature during Soldering SO8: 40 seconds 215 °C
Input and Output Voltage Range (with respect to Ground) –0.3 to 5.0 V
Supply Voltage Range –0.6 to 5.0 V
Electrostatic Discharge Voltage (Human Body model)
1
2
2000 V
Figure 3. Microcontroller and Memor y Devices on the SPI Bus
M25P10
SPI Interface with
(CPOL, CPHA) =
('0', '0') or ('1', '1')
Master
(ST6, ST7, ST9,
ST10, Others)
CS3 CS2 CS1
SDO
SDI
SCK
CQD
M25P10
S
Once bit 7 (SRWD) of the status register has been
set to 1, the possibility to rewrite the SR depends
on the logical level present at pin W
pin is high, it will be possible to rewrite the
–If W
:
status register after having set t he WEL (Write
Enable Latch).
–If W
pin is low, any attempt to modify the status
register will be ignored by the device even if the
WEL was set. As a consequ ence: all the data
bytes in the memory area software protected
(SPM) by the BPi bits of the st atus register are
also hardware protected against data
modification and can be seen as a R ead Only
memory area. This mode is called the Hardware
Protected Mode (HPM).
CQD
M25P10
S
CQD
M25P10
S
AI03746
It is possible to enter the Hardware Protected
Mode (HPM) by setting SRWD bit after pulling
down the W
pin or by pulling down the W pin after
setting SRWD bit.
The only way to abort the Hardware Protected
Mode once entered is to pull high the W
pin is permanently tied to high level, the
If W
pin.
Hardware Protected Mode will never be activated
and the memory will only allow the user to
software protect a part of the memory with the BPi
bits of the status register.
All protection features of the device are
summarized in Table 3.
Figure 4. Hold Condition Activation
CLOCK
HOLD PIN
MEMORY
STATUS
ACTIVE
HOLD ACTIVE HOLD ACTIVE
AI02029B
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M25P10
Figure 5. M25P10-Compatible SPI Modes
CPOL
CPHA
0
1
0
1
C
C
D or Q
MSB LSB
Clock Polarity (CPOL) and Clock Phase
(CPHA) with SPI Bus
As shown in Figure 5, th e M25 P10 can be driven
by a microcontroller with its SPI peripheral running
in either of the two following modes: (CPOL,
CPHA) = (’0’, ’0’) or (CPOL, CPHA) = (’1’, ’1’). For
these two modes, input data is latched in by the
low to high transition of clock C, and output data is
available from the high to low transition of Clock
(C).The difference between (CPOL, CPHA) = (0,
0) and (CPOL, CPHA) = (1, 1) is the clock polarity
when in stand-by: C remains at ’0’ for (CPOL,
CPHA) = (0, 0) and C remains at ’1’ for (CPOL,
CPHA) = (1, 1) when there is no data transfer.
MEMORY ORGANIZATION
The memory is organized in 131,072 words of 8
bits each. The device features 1,024 pages of 128
bytes each. Each page can be individually
programmed (bits are programmed from ‘1’ to ’0’
state).
AI01438
The device is also organized in 4 sectors of
262,144 bits (32,768 x 8 bits) each.The device is
Sector or Bulk Erasable but not Page Erasable
(bits are erased from ’0’ to ’1’ state).
OPERATIONS
All instructions, addresses and data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after
the chip select (S
) goes low. Prior to any
Table 4. Memory Organization
Sector Address Range
3 18000h 1FFFFh
2 10000h 17FFFh
1 08000h 0FFFFh
0 00000h 07FFFh
Table 3. Protection Features
W SRWD Status Register (SR)
X 0 Writeable after setting WEL
1 1 Writeable after setting WEL
0 1 Hardware protected
Note: 1. SPM: Software Pr otected Mode.
2. HPM: Hardware Protected Mode.
3. BPi: Bits BP0 and BP1 of the Status Register.
4. WEL: Wri te Enable Latch of the Sta tus Register.
5. W
: Write Protect Input Pin.
6. SRWD: Status Register Wri te Disable Bits of the St at us Register.
7. The device is Bulk Er asable if, and only if, (BP0, BP1) = (0, 0), (see Bulk Er ase paragraph).
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Data Bytes (Software
Protected Area by BPi bits)
Software protected by the BPi
bits of the Status Register
Software protected by the BPi
bits of the Status Register
Hardware protected by the
BPi bits of the Status Register
and the W
pin
Mode
SPM
SPM
HPM
Data Bytes (Unprotected
Area)
Paged Programmable and
Sector Erasable
Paged Programmable and
Sector Erasable
Paged Programmable and
Sector Erasable
Figure 6. Block Diagram
M25P10
HOLD
W
S
C
D
Q
Control Logic
I/O Shift Register
Address Register
and Counter
Y Decoder
High Voltage
Generator
Data
Register
128 Bytes
Status
1FFFFh1FF80h
An + 7FhAn
Size of the
Read only
Memory
area
X Decoder
Table 5. Protected Area Sizes
BP1 BP0 Software Protected Area
0 0 none
0 1 Upper quarter = Sector 3
1 0 Upper half = Sectors 2 & 3
1 1 Whole memory= Sectors 0, 1, 2 & 3
007Fh0000h
AI03747
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M25P10
Table 6. Instruction Set
Instruc
tion
WREN Set Write Enable Latch 0000 0110
WRDI Reset Write Enable Latch 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read Data from Memory Array 0000 0011
PP
SE
BE
DP Enter Deep Power-down mode 1011 1001
RES
Program up to 128 Data bytes
to Memory Array
Sector Erase (set to FFh) one
sector of Memory Array
Bulk Erase (set to FFh) whole
of Memory Array
Release from Deep Powerdown mode, and Read
Electronic Signature
Description
Instruction
Format
0000 0010
1101 1000
1100 0111
1010 1011
operation, a one-byte instruction code must be
sent to the chip. This c od e is entered via the dat a
input (D), and latched on the rising edge of the
clock input (C). To enter an instruction code, the
device must have bee n previously selected (S
=
low). Table 6 shows the available instruction set.
At Power-up and Power-down, the device must
not be selected (that is the S
voltage applied on the V
voltage reaches the correct V
(min) at Power-up and VSS at Power-down (a
V
CC
simple pull-up resistor on S
input must follow the
pin) until the supply
CC
values which are
CC
insures safe and
proper power up and down phases).
Read Data Byte(s) (READ)
The device is first selected by putting S
low. Th e
Read instruction byte is followed by a three bytes
address (A23-A0), each bit being latched-in during
the rising edge of the clock (C). Then the data
stored in the memory at the selected byte address
is shifted out on the Q output pin, each bit being
shifted out during the falling edge of the clock (C).
The first byte a ddressed can be any byt e within a
page. The address is automatically incremented to
the next higher address after each byte of dat a is
shifted out. The whole memory can theref ore be
read with a single Read instruction. When the
highest address is reached, the add ress counter
rolls over to 000000h allowing the read cycle to be
continued indefinitely.
The Read operation is terminated by deselecting
the chip. The chip can be deselec ted at any time
during data output. Any read attempt during an
Erase, Program or Write Status Register cycle will
be rejected and will deselect the chip without
having any effects on the ongoing operation.
The timing sequence is shown in Figure 11.
Page Program (PP)
Prior to any Page Program attempt, a write enable
instruction (WREN) must have been previously
sent (the S
properly transmitted and the S
input driven low, WREN instruction
input driven high).
After the WREN instruction decoding, the memory
sets the Write Enable Latc h (WEL) which allows
the execution of any further Page Program
instruction. The Page Program instruction is
entered by driving the Chip select input (S
) low,
followed by the instruction byte, 3 address bytes
and at least 1 data byte on Data In input (D). If the
least significant address bits differ from [A6A0]=000.0000, all transmi tted data ex ceeding the
addressed page boundary will roll over and will be
programmed from address [A6-A0]=000.0000 of
this same page. The Chip Select input (S
) must be
driven low for the entire duration of the sequence.
Figure 7. WREN: Set Write Enable Latch Sequence
S
21 34567
0
C
INSTRUCTION
D
HIGH IMPEDANCE
Q
6/21
AI02281B
Figure 8. WRDI: Reset Write Enable Latch Sequence
S
21 34567
0
C
INSTRUCTION
D
HIGH IMPEDANCE
Q
M25P10
AI03750
If more than 128 bytes are sent to the device,
previously latched data are discarded and the last
128 data bytes are guaranteed to be programmed
correctly within the s ame page. If less than 128
Data bytes are sent to device; they are correctly
programmed at the requested addresses without
having any effects on the other bytes of the same
Page.
The device must be deselected just after the
eighth bit of the last data byte has been latched in.
If not, the Page Program instruction is not
executed. As soon as the device is deselected, the
self-timed Page Program cycle (t
) is initiated.
PP
While the Page Program cycle is in progress, the
status register may be read to check the WIP bit
value. WIP is high during the self-timed Page
Program cycle and is low when it is completed.
When the cycle is completed, the write enable
latch (WEL) is reset.
A Page Program instruction applied to a Page
which is software protected by the BPi bits (see
Table 4 and Table 5) is not initiated.
Figure 9. RDSR: Read Status Register Sequence
The timing sequence is shown in Figure 12.
Write Enable (WREN) and Write Disable (WRDI)
The Write Enable Latch must be set prior to every
Page Program (PP), Sector Erase (SE), Bulk
Erase (BE) and Write Status Register (WRSR)
operation. The WREN instruction, whose timing
sequence is sho wn in Figure 7, w ill set the latch
and the WRDI instruction, whose timing sequence
is shown in Figure 8, will reset the latch.
The Write Enable Latch is reset under the
following conditions:
– Power on
– WRDI instruction completion
– WRSR in s t ru ctio n completio n
– Page Program instruction completion
– Sector Erase instruction completion
– Bulk Erase instruction completion.
After completion of either WREN or WRDI
instruction, the chip enters a wait state and waits
for a deselect.
S
21 3456789101112131415
0
C
INSTRUCTION
D
Q
HIGH IMPEDANCE
STATUS REG. OUT
7 6543210
MSB
STATUS REG. OUT
7 6543210
MSB MSB
7
AI02031
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