SGS Thomson Microelectronics M24C04-DW6T, M24C04-BN6, M24C04, M24C02-W, M24C02-RMN6T Datasheet

1/20May 2000

M24C16, M24C08

M24C04, M24C02, M24C01

16/8/4/2/1 Kbit Serial I²C Bus EEPROM

■ Two Wire I

2

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 3.6V for M24Cxx-R

■ Hardware Write Control

■ BYTE and PAGE WRITE (up to 16 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim ed P ro g ra m ming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ 1 Million Erase/Write Cycles (minimum)

■ 40 Year Data Retention (minimum)

DESCRIPTION

These I

2

C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 2048/1024/512/256/128 x 8 bit
(M24C16, M24C08, M24C04, M24C02, M24C01),
and operate with a power supply down to 2.5 V (for
the -W version of each device), and down to 1.8 V
(for the -R version of each device).

The M24C16, M24C08, M24C04, M24C02,
M24C01 are available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small
Outline packages. The M24C16-R is also
available in a chip-scale (SBGA) package.

Figure 1. Logic Diagram

AI02033

3

E0-E2 SDA

V

CC

M24Cxx

WC

SCL

V

SS

Table 1. Signal Names

E0, E1, E2 Chip Enable Inputs
SDA Serial Data/Address Input/

Output
SCL Serial Clock
WC Write Control
V

CC

Supply Voltage
V

SS

Ground

PSDIP8 (BN)

0.25 mm frame

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

8

1

8

1

8

1

SBGA

SBGA5 (EA)

75 mil width

M24C16, M24C08, M24C04, M24C02, M24C01

2/20

Figure 2A. DIP Connections

Note: 1. NC = Not Connected

Figure 2B. SO Connections

Note: 1. NC = Not Connected

Figure 2C. Standard-TSSOP Connections

Note: 1. NC = Not Connected

SDAV

SS

SCL

WC

V

CC

/ E2

AI02034D

M24Cxx

1
2
3
4

8
7
6
5

/ E2/ E2/ E2NC

/ E1

/ E1/ E1/ NCNC

/ E0

/ E0/ NC/ NCNC

/1Kb

/2Kb/4Kb/8Kb16Kb

1

AI02035D

2
3
4

8
7
6
5

SDAV

SS

SCL

WC

V

CC

/ E2

M24Cxx

/ E2/ E2/ E2NC

/ E1

/ E1/ E1/ NCNC

/ E0

/ E0/ NC/ NCNC

/1Kb

/2Kb/4Kb/8Kb16Kb

1

AI02036D

2
3
4

8
7
6
5

SDAV

SS

SCL

WC

V

CC

/ E2

M24Cxx

/ E2/ E2/ E2NC

/ E1

/ E1/ E1/ NCNC

/ E0

/ E0/ NC/ NCNC

/1Kb

/2Kb/4Kb/8Kb16Kb

Figure 2D. SBGA Connections (top view, marking side, with balls on the underside)

AI02796E

SCL V

SS

SDA

WC V

CC

M24C16

Ball "1"

3/20

M24C16, M24C08, M24C04, M24C 02, M24C01

These memory devices are compatible with the
I

2

C memory standard. This is a two wire serial
interface that uses a bi-directional data bus and
serial clock. The memory carries a built-in 4-bit
unique Device Type Identifier code (1010) in
accordance with the I

2

C bus definition.

The memory behaves as a slave device in the I

2

C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, gene rated by the
bus master. The START condition is followed by a
Device Select Code and RW

bit (as described in

Table 3), terminated by an acknowledge bit.

When writing data to the memory, the memory
inserts an acknowledge bit during the 9

th

bit time,

following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data b yte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.

Power On Reset: V

CC

Lock-Out Write Protect

In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until the V

CC

voltage has reached

the POR threshold value, and all operations are

Figure 3. Maximum R

L

Value versus Bus Capacitance (C

BUS

) for an I2C Bus

AI01665

V

CC

C

BUS

SDA

R

L

MASTER

R

L

SCL

C

BUS

100

0

4

8

12

16

20

C

BUS

(pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc = 100kHz

Table 2. Absolute Maximum Ratings

1

Note: 1. Exc ept for the r ating “Oper ating Tempe rature Range”, stresses above th ose listed in the Table “Absolute M aximum Rati ngs” may

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this s pecificatio n is not implied. Ex posure to A bsolute Maximum Rating cond i ­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL -STD-883C , 3015.7 (100 pF, 1500 Ω)

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature -40 to 125 °C

T

STG

Storage
Temperature

-65 to 150 °C

T

LEAD

Lead Temperature
during Soldering

PSDIP8: 10 sec

SO8: 40 sec

TSSOP8: 40 sec

SBGA5: t.b.c.

260
215
215

t.b.c.

°C

V

IO

Input or Output range -0.6 to 6.5 V

V

CC

Supply Voltage -0.3 to 6.5 V

V

ESD

Electrostatic Discharge Voltage (Human Body model2)

4000

V

M24C16, M24C08, M24C04, M24C02, M24C01

4/20

disabled – the device will not respond to any
command. In the same way, when V

CC

drops from
the operating voltage, below the POR threshold
value, all operations are disabled an d the device
will not respond to any command. A stable and
valid V

CC

must be applied before applying any

logic signal.

SIGNAL DESCRIPTION
Serial Clock (SCL)

The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a
slower clock, the master must have an open drain
output, and a pull-up resistor must be c onnected
from the SCL line to V

CC

. (Figure 3 indicates how
the value of the pull-up resistor can be calculated).
In most applications, though, this method of
synchronization is not employed, and so the pull­up resistor is not necessary, provided that the

master has a push-pull (rather than open drain)
output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to
transfer data in or out of the memory. It is an open
drain output that may be wire-OR’ed with other
open drain or open collector signals on the bus. A
pull up resistor must be connected f rom the SDA
bus to V

CC

. (Figure 3 indicates how t he value of

the pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code (but
see the description of memory addressing, on
page 6, for more details). These inputs may be
driven dynamically or tied to V

CC

or VSS to
establish the device select code (but note that the
V

IL

and VIH levels for the inputs are CMOS

compatible, not TTL compatible).

Figure 4. I

2

C Bus Protocol

SCL

SDA

SCL

SDA

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

1 23 789

MSB

ACK

START

CONDITION

SCL

1 23 789

MSB ACK

STOP

CONDITION

5/20

M24C16, M24C08, M24C04, M24C 02, M24C01

Write Control (WC)

The hardware Write Control pin (WC

) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC

=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
unconnected, the WC

input is internally read as

V

IL

, and write operations are allowed.

When WC

=1, Device Select and Address bytes
are acknowledged, Data bytes are not
acknowledged.

Please see the Application Note

AN404

for a more

detailed description of the Write Control feature.

DEVICE OPERATION

The memory device supports the I

2

C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note

AN1001

. Any device that sends data on to the bus
is defined to be a transm itter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is k nown as the master,
and the other as the slave. A data transfer can only
be initiated by the mas ter, which wi ll also provide
the serial clock for synchronization. The memory

device is always a slave device in all
communication.

Start Condition

START is identified by a high t o low transition of
the SDA line while the clock, SCL, is stab le in t he
high state. A START condition must precede any
data transfer command. The memory device
continuously monitors (except during a
programming cycle) the SDA and SCL lines for a
START condition, and will not respond unless one
is given.

Stop Condition

STOP is identified by a low to high transition of the
SDA line wh ile th e clock S CL is sta ble in the h igh
state. A STOP condition terminates
communication between the m emory device and
the bus master. A STOP condition at the end of a
Read command, after (and only after) a NoAck,
forces the memory device into its standby state. A
STOP condition at the end of a Write com mand
triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
bus after sending eight bits of data. During the 9

th

Table 3. Device Select Code

1

Note: 1. The most significant bit, b7, is sent first.

2. E0, E1 and E2 are comp ared against the respective ext ernal pins on the memory device.

3. A10, A9 and A8 repres ent high significant bits of the address.

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0
M24C01 Select Code 1010E2E1E0RW
M24C02 Select Code 1010E2E1E0RW
M24C04 Select Code 1010E2E1A8RW
M24C08 Select Code 1010E2A9A8RW
M24C16 Select Code 1010A10A9A8RW

Table 4. Operating Modes

Note: 1. X = V

IH

or V

IL

.

Mode RW bit

WC

1

Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW

= ‘1’

Random Address Read

0X

1

START, Device Select, RW

= ‘0’, Address

1 X reSTART, Device Select, RW

= ‘1’

Sequential Read 1 X

≥

1 Similar to Current or Random Address Read

Byte Write 0 V

IL

1 START, Device Select, RW = ‘0’

Page Write 0 V

IL

≤

16 START, Device Select, RW

= ‘0’

M24C16, M24C08, M24C04, M24C02, M24C01

6/20

Figure 5. Wri te Mo de S e qu e nces with WC=1 (data wri te inhibi ted)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR DATA IN

WC

START

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

WC

DATA IN 3

AI02803B

PAGE WRITE
(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK ACK NO ACK

R/W

ACK ACK NO ACK NO ACK

R/W

NO ACK NO ACK

clock pulse period, the receiver pulls the SDA bus
low to acknowledge the receipt of the eight data
bits.

Data Input

During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high
transition, and the data must change

only

when

the SCL line is low .

Memory Addressing

To start communication betwee n the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type

Identifier, and a 3-bit Chip Enable “Address” (E2,
E1, E0 ) .

To address the memory array, the 4-bit Device
Type Identifier is 1010b.

Up to eight memory devices can be connected on
a single I

2

C bus. Each one is given a uniq ue 3-bit
code on its Chip Enable inputs. W hen the Device
Select Code is received, the memory only
responds if the Chip Enable Code (shown in Table

3) is the same as the pattern applied to its Chip
Enable pins.

Those devices with larger memory capacities (the
M24C16, M24C08 and M24C04) need more
address bits. E0 is not available for use on devices
that need to use address line A8; E1 is not
available for devices that need to use address line
A9, and E2 is not available for devices that need to
use address line A10 (see Figure 2A to Figure 2D
and Table 3 for details). Using the E0, E1 and E2
inputs pins, up to eight M24C02 (or M24C01), four
M24C04, two M24C08 or one M24C16 device can
be connected to one I

2

C bus. In each case, and in

the hybrid cases, this gives a total memory

7/20

M24C16, M24C08, M24C04, M24C 02, M24C01

Figure 6. Wri te Mo de S e qu e nces with WC=0 (data wri te enab led)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR DATA IN

WC

START

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

WC

DATA IN 3

AI02804

PAGE WRITE
(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK

R/W

ACK ACK

ACK ACK ACK ACK

R/W

ACKACK

capacity of 16 Kbits, 2 KBytes (except where
M24C01 devices are used).

The 8

th

bit is th e RW bit. This is set to ‘1’ for read

and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding
memory gives an acknowledgment on the SDA
bus during the 9

th

bit time. If the memory does not
match the Device Sel ect Code, it deselects itself
from the bus, and goes into stand-by mode.

There are two modes both for read and write.
These are summarized in Table 4 and described
later. A communication between the m aster and
the slave is ended with a STOP condition.

Write Operations

Following a START con dition the ma ster sends a
Device Select Code with the RW

bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for an address byte. The memory
responds to the address byte with an acknowledge
bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC

=1 (during a period o f time from the START
condition until the end of the address byte) will not
modify the memory contents, and the
accompanying data bytes will

not

be

acknowledged (as shown in Figure 5).

Byte Write

In the Byte Write mode, after the Device Select
Code and the address, the master sends one data
byte. If the addressed location is write protected by
the WC

pin, the memory replies with a NoAck, and

the location is not modified. If, instead, the WC

pin
has been held at 0, as shown in Figure 6, the
memory replies with an Ack. The master
terminates the transfer by generating a STOP
condition.

Page Write

The Page Write mode allows u p to 16 by tes to be
written in a single write cycle, provided that they

M24C16, M24C08, M24C04, M24C02, M24C01

8/20

A STOP condition at any other time does not
trigger the internal write cycle.

During the internal write cycle, the SDA input is
disabled internally, and the device does not
respond to any requests.

Minimizing System Delays by Polling On ACK

During the internal write cycle, the memory
disconnects itself from the bus, and copies the
data from its internal latches to the memory cells.
The ma ximum w rite tim e (t

w

) is shown in Table 6B,
but the typical time is shorter. To make use of this,
an Ack polling sequence can be used by the
master.

are all located in the same ’row’ in the memory:
that is the most significant memory add ress bits
are the same. If more bytes are sent than will fit up
to the end of the row, a condition known as ‘roll­over’ occurs. Data starts to become overwritten, or
otherwise altered.

The master sends from one up to 16 bytes of data,
each of which is acknow ledged by the memory if
the WC

pin is low. If the WC pin is high, the
contents of the addressed memory location are
not modified, and each dat a byte is followed by a
NoAck. After each byte i s tran sferred, the i nte rnal
byte address counter (the 4 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.

When the master generates a STOP condition
immediately after the Ack bi t (in t he “10

th

bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.

Figure 7. Wri te Cy cle Pol l in g Fl owchart using A C K

WRITE Cycle

in Progress

AI01847

Next

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

NO

YESNO

ReSTART

STOP

Proceed

WRITE Operation

Proceed
Random Address
READ Operation

Send

Byte Address

First byte of instruction
with RW = 0 already
decoded by M24xxx

9/20

M24C16, M24C08, M24C04, M24C 02, M24C01

Read Operations

Read operations are performed independently of
the state of the WC

pin.

Random Address Read

A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then,

without

sending a STOP condition, the
master sends another START condition, and
repeats the Device Select Code, with the RW

bit

set to ‘1’. The memory acknowledges this, and
outputs the contents of the addressed byte. The
master must

not

acknowledge the byte output, and

terminates the transfer with a STOP condition.

The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the m aster issues a START condition

followed by a Device Select Code (the first byte
of the new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no Ack will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an Ack, indicating that the memory is ready
to receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).

Figure 8. Read Mode Sequences

Note: 1. The seven most sign i fi cant bits of the Device Sele ct Code of a Rando m Read (in the 1st and 3rd bytes) must be identical .

START

DEV SEL * BYTE ADDR

START

DEV SEL DATA OUT 1

AI01942

DATA OUT N

STOP

START

CURRENT
ADDRESS
READ

DEV SEL DATA OUT

RANDOM
ADDRESS
READ

STOP

START

DEV SEL * DATA OUT

SEQUENTIAL
CURRENT
READ

STOP

DATA OUT N

START

DEV SEL * BYTE ADDR

SEQUENTIAL
RANDOM
READ

START

DEV SEL * DATA OUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

M24C16, M24C08, M24C04, M24C02, M24C01

10/20

Table 5A. DC Characteristics

(T

A

= 0 to 70 °C, or –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V)

(T

A

= 0 to 70 °C, or –40 to 85 °C; VCC = 1.8 to 3.6 V)

Note: 1. This is preliminary data.

Symbol Parameter Test Condition Min. Max. Unit

I

LI

Input Leakage Current
(SCL, SDA)

0V ≤ V

IN

≤ V

CC

± 2 µA

I

LO

Output Leakage Current 0 V ≤ V

OUT

≤ V

CC,

SDA in Hi-Z ± 2 µA

I

CC

Supply Current

V

CC

=5V, fc=400kHz (rise/fall time < 30ns)

2mA

-W series:

V

CC

=2.5V, fc=400kHz (rise/fall time < 30ns)

1mA

-R series:

V

CC

=1.8V, fc=400kHz (rise/fall time < 30ns)

0.8

1

mA

I

CC1

Supply Current
(Stand-by)

V

IN

= VSS or V

CC

, V

CC

= 5 V 1 µA

-W series: V

IN

= VSS or V

CC

, V

CC

= 2.5 V 0.5 µA

-R series: V

IN

= VSS or V

CC

, V

CC

= 1.8 V

0.1

1

µA

V

IL

Input Low Voltage
(E0, E1, E2, SCL, SDA)

– 0.3 0.3 V

CC

V

V

IH

Input High Voltage
(E0, E1, E2, SCL, SDA)

0.7V

CC

VCC+1 V

V

IL

Input Low Voltage (WC) – 0.3 0.5 V

V

IH

Input High Voltage (WC)

0.7V

CC

VCC+1

V

V

OL

Output Low
Voltage

I

OL

= 3 mA, VCC = 5 V

0.4 V

-W series: I

OL

= 2.1 mA, VCC = 2.5 V 0.4 V

-R series:

I

OL

= 0.7 mA, VCC = 1.8 V

0.2

1

V

Current Address Read

The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read m ode, following a START
condition, the master sends a Device Select Code
with the RW

bit set to ‘1’. The memory
acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The master
terminates the transfer with a STOP condition, as
shown in Figure 8,

without

acknowledging the byte

output.

Sequenti a l Rea d

This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master

does

acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must

not

acknowledge the last

byte output, and

must

generate a STOP condition.

The output data comes from consecutive
addresses, with the internal address counter
automatically incremen ted af t er ea ch byt e out put.

After the last memory address, the address
counter ‘rolls-over’ and the memory continues to
output data from memory address 00h.

Acknowledge in Read Mode

In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9

th

bit time. If the master does n ot pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.

11/20

M24C16, M24C08, M24C04, M24C 02, M24C01

Table 5B. DC Characteristics

1

(TA = –40 to 125 °C; VCC = 4.5 to 5.5 V)

Note: 1. This is preliminary data.

Table 6A. AC Characteristics

Note: 1. For a r eS T ART condition, or follow i ng a write cycle.

2. Samp l ed only, not 100 % t ested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. This i s prelim i nary dat a.

Symbol Parameter Test Condition Min. Max. Unit

I

LI

Input Leakage Current (SCL, SDA)

0V ≤ V

IN

≤ V

CC

± 2 µA

I

LO

Output Leakage Current 0 V ≤ V

OUT

≤ V

CC,

SDA in Hi-Z ± 2 µA

I

CC

Supply Current

V

CC

=5V, fc=400kHz (rise/fall

time < 30ns)

3mA

I

CC1

Supply Current (Stand-by) V

IN

= VSS or V

CC

, V

CC

= 5 V 5 µA

V

IL

Input Low Voltage (E0, E1, E2, SCL, SDA) – 0.3 0.3 V

CC

V

V

IH

Input High Voltage (E0, E1, E2, SCL, SDA)

0.7V

CC

VCC+1

V

V

IL

Input Low Voltage (WC) – 0.3 0.5 V

V

IH

Input High Voltage (WC)

0.7V

CC

VCC+1

V

V

OL

Output Low Voltage IOL = 3 mA, VCC = 5 V 0.4 V

Symbol Alt. Parameter

M24C16, M24C08, M24C04, M24C02, M24C01

Unit

V

CC

=4.5 to 5.5 V

T

A

=0 to 70°C or

–40 to 85°C

V

CC

=2.5 to 5.5 V

T

A

=0 to 70°C or

–40 to 85°C

V

CC

=1.8 to 3.6 V

T

A

=0 to 70°C or

–40 to 85°C

4

Min Max Min Max Min Max

t

CH1CH2

t

R

Clock Rise Time 300 300 300 ns

t

CL1CL2

t

F

Clock Fall Time 300 300 300 ns

t

DH1DH2

2

t

R

SDA Rise Time 20 300 20 300 20 300 ns

t

DL1DL2

2

t

F

SDA Fall Time 20 300 20 300 20 300 ns

t

CHDX

1

t

SU:STA

Clock High to Input Transition 600 600 600 ns

t

CHCL

t

HIGH

Clock Pulse Width High 600 600 600 ns

t

DLCLtHD:STA

Input Low to Clock Low (START) 600 600 600 ns

t

CLDXtHD:DAT

Clock Low to Input Transition 0 0 0 µs

t

CLCH

t

LOW

Clock Pulse Width Low 1.3 1.3 1.3 µs

t

DXCXtSU:DAT

Input Transition to Clock
Transition

100 100 100 ns

t

CHDHtSU:STO

Clock High to Input High (STOP) 600 600 600 ns

t

DHDL

t

BUF

Input High to Input Low (Bus
Free)

1.3 1.3 1.3 µs

t

CLQV

3

t

AA

Clock Low to Data Out Valid 200 900 200 900 200 900 ns

t

CLQX

t

DH

Data Out Hold Time After Clock
Low

200 200 200 ns

f

C

f

SCL

Clock Frequency 400 400 400 kHz

t

W

t

WR

Write Time 5 10 10 ms

M24C16, M24C08, M24C04, M24C02, M24C01

12/20

Table 6B. AC Characteristics

4

Note: 1. For a r eS T ART condition, or follow i ng a write cycle.

2. Samp l ed only, not 100 % t ested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. This i s prelim i nary dat a.

Symbol Alt. Parameter

M24C16, M24C08, M24C04, M24C02, M24C01

Unit

V

CC

=4.5 to 5.5 V; TA=–40 to 125°C

Min Max

t

CH1CH2

t

R

Clock Rise Time 300 ns

t

CL1CL2

t

F

Clock Fall Time 300 ns

t

DH1DH2

2

t

R

SDA Rise Time 20 300 ns

t

DL1DL2

2

t

F

SDA Fall Time 20 300 ns

t

CHDX

1

t

SU:STA

Clock High to Input Transition 600 ns

t

CHCL

t

HIGH

Clock Pulse Width High 600 ns

t

DLCLtHD:STA

Input Low to Clock Low (START) 600 ns

t

CLDXtHD:DAT

Clock Low to Input Transition 0 µs

t

CLCH

t

LOW

Clock Pulse Width Low 1.3 µs

t

DXCXtSU:DAT

Input Transition to Clock Transition 100 ns

t

CHDHtSU:STO

Clock High to Input High (STOP) 600 ns

t

DHDL

t

BUF

Input High to Input Low (Bus Free) 1.3 µs

t

CLQV

3

t

AA

Clock Low to Data Out Valid 200 900 ns

t

CLQX

t

DH

Data Out Hold Time After Clock Low 200 ns

f

C

f

SCL

Clock Frequency 400 kHz

t

W

t

WR

Write Time 10 ms

Table 7. AC Measurement Conditions

Input Rise and Fall Times

≤

50 ns

Input Pulse Voltages

0.2V

CC

to 0.8V

CC

Input and Output Timing
Reference Voltages

0.3V

CC

to 0.7V

CC

Figure 9. AC Testing Input Output Waveforms

AI00825

0.8V

CC

0.2V

CC

0.7V

CC

0.3V

CC

Table 8. Input Parameters1 (TA = 25 °C, f = 400 kHz)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min. Max. Unit

C

IN

Input Capacitance (SDA) 8 pF

C

IN

Input Capacitance (other pins) 6 pF

Z

WCL

WC Input Impedance VIN < 0.5 V 5 70 k

Ω

Z

WCH

WC Input Impedance VIN > 0.7V

CC

500 k

Ω

t

NS

Pulse width ignored
(Input Filter on SCL and SDA)

Single glitch 100 ns

13/20

M24C16, M24C08, M24C04, M24C 02, M24C01

Figure 10. AC Waveforms

SCL

SDA IN

SCL

SDA OUT

SCL

SDA IN

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLCH

tDXCX

tCLDX

SDA

INPUT

SDA

CHANGE

tCHDH

tDHDL

STOP &

BUS FREE

DATA VALID

tCLQV tCLQX

DATA OUTPUT

tCHDH

STOP

CONDITION

tCHDX

START

CONDITION

WRITE CYCLE

tW

AI00795B

M24C16, M24C08, M24C04, M24C02, M24C01

14/20

Table 9. Ordering Information Scheme

Note: 1. Temperature range 1 available only on reque st .

2. SBGA5 packa ge available on l y f or the “M24C16 -R EA 6 T”

Example: M2 4C08 –WDW1T

Memory Capacity Option

16 16 Kbit (2048 x 8) T Tape and Reel Packing
08 8 Kbit (1024 x 8)
04 4 Kbit (512 x 8) Temperature Range

02 2 Kbit (256 x 8)

1

1

0 °C to 70 °C

01 1 Kbit (128 x 8) 6 –40 °C to 85 °C

3 –40 °C to 125 °C

Operating Voltage Package

blank 4.5 V to 5.5 V BN PSDIP8 (0.25 mm frame)
W 2.5 V to 5.5 V MN SO8 (150 mil width)

R

1.8 V to 3.6 V

DW

TSSOP8 (169 mil width)

EA

SBGA5

2

ORDERING INFORMATION

Devices are shipped from the factory with the

memory content set at all ‘1’s (FFh).
The notation used for the device number is as

shown in Table 9. For a list of avai lable options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.

15/20

M24C16, M24C08, M24C04, M24C 02, M24C01

Figure 11. PSDIP8 (BN)

Note: 1. Drawing is not to scale.

PSDIP-a

A2

A1AL

e1

D

E1 E

N

1

C

eA
eB

B1

B

Table 10. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 3.90 5.90 0.154 0.232

A1 0 .49 – 0.019 –

A2 3 .30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022

B1 1 .15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.0 14
D 9.20 9.90 0.362 0.3 90
E 7.62 – – 0.300 – –

E1 6 .00 6.70 0.236 0.264

e1 2.54 – – 0.100 – –
eA 7 .80 – 0.307 –
eB 10.00 0.394

L 3.00 3.80 0.118 0.1 50
N8 8

M24C16, M24C08, M24C04, M24C02, M24C01

16/20

Table 11. SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1 .75 0.053 0.069

A1 0 .10 0.25 0.004 0.010

B 0.33 0 .51 0.013 0.020
C 0.19 0.25 0.007 0.0 10
D 4.80 5.00 0.189 0.1 97
E 3.80 4 .00 0.150 0.157
e 1 .27 – – 0. 050 – –

H 5.80 6.20 0.228 0.2 44
h 0.25 0.50 0.010 0.0 20
L 0.40 0.90 0.016 0.0 35

α

0° 8° 0° 8°

N8 8

CP 0.10 0.004

Figure 12. SO8 narrow (MN)

Note: 1. Drawing is not to scale.

SO-a

E

N

CP

B

e

A

D

C

LA1 α

1

H

h x 45˚

17/20

M24C16, M24C08, M24C04, M24C 02, M24C01

Table 12. TSSOP8 - 8 lead Thin Shrink Small Outline

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.10 0.043
A1 0.05 0.15 0.002 0.006
A2 0.85 0.95 0.033 0.037

B 0.19 0.30 0.007 0.012

C 0.09 0.20 0.004 0.008

D 2.90 3.10 0.114 0.122

E 6.25 6.50 0.246 0.256
E1 4.30 4.50 0.169 0.177

e 0.65 – – 0.026 – –

L 0.50 0.70 0.020 0.028

α

0° 8° 0° 8°

N8 8

CP 0.08 0.003

Figure 13. TSSOP8 (DW)

Note: 1. Drawing is not to scale.

TSSOP

1

N

CP

N/2

DIE

C

L

A1

EE1

D

A2A

α

eB

M24C16, M24C08, M24C04, M24C02, M24C01

18/20

Figure 14. SBGA5 (EA) – Underside view (ball side)

Note: 1. Drawing is not to scale.

E1

A

SBGA-00

A1

D

D1

E1 E

e

BALL "1"

Table 13. SBGA5 - 5 ball Shell Ball Grid Array

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 0.430 0.380 0.480 0.017 0.015 0.019
A1 0.180 0.150 0.210 0.007 0.006 0.008

D 1.900 1. 870 1.930 0.075 0.074 0.076
D1 1.190 1.160 1.220 0.047 0.046 0.048

E 1.750 1.720 1.780 0.069 0.068 0.070
E1 1.070 1.040 1.100 0.042 0.041 0.043

e 0.800 0. 770 0.830 0.031 0.030 0.033

ball diameter 0.350 0.320 0.380 0.014 0.013 0.015

N5 5

19/20

M24C16, M24C08, M24C04, M24C 02, M24C01

Table 14. Revision History

Date Description of Revision

10-Dec-1999

TSSOP8 Turned-Die package removed (p 2 and order information)
Lead temperature added for TSSOP8 in table 2

18-Apr-2000 Labelling change to Fig-2D, correction of values for ‘E’ and main caption for Tab-13

05-May-2000 Extra labelling to Fig-2D

M24C16, M24C08, M24C04, M24C02, M24C01

20/20

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