Datasheet LNBP21PD-TR, LNBP21PD, LNBP21D2-TR, LNBP21D2 Datasheet (SGS Thomson Microelectronics)

LNBP21

LNBP SUPPLY AND CONTROL IC WITH

STEP-UP CONVERTER AND I

■ COMPLETE INTERFACE BETWEEN LNB

AND I2CTM BUS

■ BUILT-IN DC/DC CONTROLLER FOR

SINGLE 12V SUPPLY OPERATION

■ ACCURATE BUILT-IN 22KHz TONE

OSCILLATOR

■ SUITS WIDELY ACCEPTED STANDARDS

■ FAST OSCILLATOR START-UPFACILITATES

DiSEqCTM ENCODING

■ BUILT-IN 22KHz TONE DETECTOR

SUPPORTS BI-DIRECTIONAL DiSEqCTM

■ LOOP-THROUGH FUNCTION FOR SLAVE

OPERATION

■ LNB SHORT CIRCUIT PROTECTION AND

DIAGNOSTIC

■ CABLE LENGTH DIGITAL COMPENSATION

■ INTERNAL OVER TEMPERATURE

PROTECTION

■ ESD RATING4KV ON POWER

INPUT-OUTPUT PINS

2

C INTERFACE

SO-20PowerSO-20

DESCRIPTION

Intended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBP21 is a
monolithic voltage regulator and interface IC,
assembled in SO-20 and PowerSO-20,
specifically designed t o provide the power and the
13/18V, 22KHz tone signalling to the LNB

SCHEMATIC DIAGRAM

Gate

Sense

Vup

Vcc

Byp

SDA
SCL

ADDR

DSQIN

Preregul.+

U.V.lockout

+P.ON res.

I²C
interf.

Step-up

Controller

LNBP21

Feedback

Enable
I Select
V Select

Linear Post-reg

+Modulator

+Protections

22KHz
Oscill.

Diagnostics

Tone

Detector

LT1

LT2

OUT

EXTM

DETIN

DSQOUT

1/20October 2002

LNBP21

downconverter i n the antenna or to the multiswitch
box. In this application field, it offers a complete
solution with extremely low component count, low
power dissipation together with simple design and

2

I

CTM standard interfac-ing.
This IC has a built in DC/DC step-up controller
that, from a s ingle supply source ranging from 8 to
15V, generates the voltages that let the linear
post-regulator to work at a minimum dis sipat ed
power. An UnderVoltage Lockout circuit will
disable the whole circuit when the supplied V

CC

drops below a fixedthreshold(6.7V typically).The
internal 22KHz tone generator is factory t rim med
in accordance to the standards, and can be
controlled either by the I
dedicated pin (DSQIN) that allows immediate
DiSEqC

TM

data encoding (*). All t he functions of

this IC are controlled via I

2CTM

2CTM

interface or by a

bus by writing 6
bits on the System Register (SR, 8 bits) . The
same register can be read back, and two bits will
report the diagnostic status. When the IC is put in
Stand-by (EN bit LOW), the power blocks are
disabled and the loop-through switch between
LT1 and LT2 pins is clos ed, thus leaving all LNB
powering and control functions to the Master
Receiver (**). When the regulator blocks are
active (EN bit HIGH), the output can be logic
controlled to be 13 or 18 V (typ.) by mean of t he
VSEL bit (Voltage SELect) for remote controlling
of non-DiSEqC LNBs. Additionally, it is possible
to increment by 1V (typ.) the selected voltage
value to compen sate for the excess voltage drop
along the coaxial cable ( LLC bit HIGH). In order to
minimise the power dissipation, the out put voltage
of the internal step-up converter is adjusted to
allow the linear regulator to work at m inimum
dropout. Another bit of the SR is addressed to the
remote control of non-DiSEqC LNBs: the TEN
(Tone ENable) bit. When it is set to HIGH, a
continuous 22K Hz to ne is gene rated regardless
of the DSQIN pin logic status. The TEN bit must
besetLOWwhentheDSQINpinisusedfor
DiSEqC
DiSEqC
22KHz tone detector. Its input pin (DETIN) must
be AC coupled to the DiSEqC

TM

encoding. The f ully bi-directional

TM

interfacing is c ompleted by the built -in

TM

bus, and the
extractedPWKdataareavailableonthe
DSQOUT pin (*).
In order to improve design flexibility and to allow
implementation of newcoming LNB remote control
standards, an analogic modulation input pin is
available (EXTM). An appropria te DC blocking

(*): External components are needed to comply to bi-directional DiSEqCTMbus hardware require-ments. Full compliance of the whole appli­cation toDiSEqCTMspecifications is not implied by the use of this IC.
(**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must
be externally limited.

capaci-tor must be used to couple the modulating
signal sour ce to the EX TM pin. When external
modulation is not used, the relevant pin can be left
open.
The cu rrent limitation block has two thresho lds
that can be selected by the I

bitoftheSR;the

SEL

lower threshold is between 400 and 550m A
(I

=HIGH), while the higher threshold is

SEL

between 500 and 650mA (I

SEL

=LOW).
The current protection block is SOA type. This
limits the short circuit current (Isc) typically at
200mA with I
I

=LOW when the output port is connected to

SEL

=HIGH and at 300mA with

SEL

ground.
It is possible to set the Short Circuit Current
protection either statically (simple current clamp)
or dy-namically by the PCL bit of the SR; when
the PCL (Pulsed Current Limiting) bit is set to
LOW, the overcurrent protection c ircuit w ork s
dynamically: as soon as an overload is detected,
the output is shut-down for a time t

, typically

off

900ms. S imultaneously the OLF bit of the System
Register is set to HIGH. After this time has
elapsed, the output is resumed for a time t
10t

(typ.). At the end of ton, if the overload is still

off

on

=1/

detected, the protection circuit will cycle again
through Toff and T on. At the end of a full Ton in
which no overload is detected, norm al operation is
resumed and the OLF bit is reset to LOW. Typica l
Ton+Toff time is 990ms and it is determined by an
internal timer. This dynamic operation can greatly
reduce the power dissipation in short circuit
condition, still ensuring excellent power-on start
up in most conditions (**) .
However, there c ould be some cases in whi ch an
highly capacitive load on the output may cause a
difficult start-up when the dynamic protection is
chosen. T his can be solved by initiating any power
start-up in static mode (PCL=HIGH) and then
switching t o the dynam ic mode (PCL=LOW) after
a chosen amount of time. When in static mode,
the OLF bit goes HIGH when the current clamp
limit is reached and returns LOW when the
overload condition is cleared.
This IC is also protect ed against overheating:
when the junction temperature exceeds 150°C
(typ.), the step-up converter and the linear
regulator are shut off, the loop-trough switch is
opened, and the OTF bit of the SR is set to HIGH.
Normal operation is resumed and the OTF bit is
reset to LOW when the junction is cooled down to
140°C (typ.).

2/20

ORDERING CODES

LNBP21

TYPE

SO-20
(Tube)

SO-20

(Tape & Reel)

PowerSO-20

(Tube)

PowerSO-20

(Tape & Reel)

LNBP21 LNBP21D2 LNBP21D2-TR LNBP21PD LNBP21PD-TR

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V
V

V

LT1,VLT2

I

V

V

V

DETIN

V

I

V

I

GATE

V

SENSE

V

ADDRESS

T
T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.

DC Input Voltage

CC

DC Input Voltage

UP

DC Input Voltage
Output Current

O

DC Output Pin Voltage

O

Logic Input Voltage (SDA, SCL, DSQIN)

I

Detector Input Signal Amplitude
Logic High Output Voltage (DSQOUT)

OH

Bypass Switch ON Current

LT

Bypass Switch OFF Voltage

LT

Gate Current
Current Sense Voltage
Address Pin Voltage
Storage Temperature Range

stg

Operating Junction Temperature Range

op

16 V
25 V
20 V

Internally Limited mA

-0.3 to 22 V

-0.3 to 7 V
2

V

PP

7V

900 mA
±20 V

±400 mA

-0.3 to 1 V

-0.3 to 7 V

-40 to +150 °C

-40 to +125 °C

THERMAL DATA

Symbol Parameter SO-20 PowerSO-20 Unit

R

thj-case

Thermal Resistance Junction-case

15 2 °C/W

PIN CO NFIGUARATION (top view)

SO-20

PowerSO-20

3/20

LNBP21

TABLE A: PIN CONFIGURATIONS

PIN NUMBER

SYMBOL NAME FUNCTION

V

Supply Input 8V to 15V supply. A 220µF bypass capacitor to

CC

GND with a 470nF (ceramic) in parallel is
recommended

GATE Exrernal Switch Gate External MOS switch Gate connection of the

step-up converter

SENSE Current Sense Input Current Sense comparator input. Connected to

current sensing resistor

V

Step-up Voltage Input of the linear post-regulator.Thevoltage on this

up

pin is monitored by internal step-ut controller to
keep a minimum dropout across the linear pass
transistor

OUT Output Port Output of the linear post regulator modulator to the

LNB. See truth table for voltage selections.

SDA Serial Data

SCL Serial Clock

Bidirectional data from/to I
Clock from I

2

Cbus.

2

C bus.

DSQIN DiSEqC Input When the TEN bit of the System Register is LOW,

this pin will accept the DiSEqC code from the main
µcontroller. The LNBP21 will use this code to
modulate the internally generated 22kHz carrier.Set
to GND thi pin if not used.

DETIN Detector In 22kHz Tone Detector Input. Must be AC coupled to

the DiSEcQ bus.

DSQOUT DiSEqC Output Open collector output of the tone Detector to the

main µcontroller for DiSEcQ data decoding. It is
LOW when tone is detected.

EXTM Extrernal Modulator External Modulation Input. Need DC decoupling to

the AC source. If not used, can be left open.

GND Ground Circuit Ground. It is internally connected to the die

frame for heat dissipation.

BYP Bypass Capacitor Needed for internal preregulator filtering 8 8

LT1 Loop Through Switch In standby mode the power switch between LT1

and LT2 is closed. Max allowed current is 900mA.
this pin can be left open if loopthrough function is
not needed.

LT2 Loop Through Switch Same as above 2 3

ADDR Address Setting

2

C bus addresses available by setting the

Four I
Address Pin level voltage

vs PACKAGE

SO-20 PowerSO-20

19 18

17 17

14 16

20 19

12

11 12
12 13
13 14

99

10 15

45

5,6,15,16 1,10,11,20

34

77

4/20

TYPICAL AP PLICATION CIRCUIT

C2
220µF

C3
470nF

Ceramic

IC1

Vup

D1 1N4001

LT1

Master ST B

C7
10nF

LNBP21

IC2

(Note 3)

STS4DNFS30L

Gate

LNBP21

L1=22µH

Vin

12V

(*) Set to GND if not used
(**) filter to be used according to EUTELSAT reccomendation to implement the DiSEqC
not implemented (see DiSEqC implementation note)
(***) IC2 isa ST Fettky, STS4DNFS30L,thatincludes both the schottkydiode andtheN-Channel Mos-Fet, needed fortheDC/DC converter,
in a So-8 package. It can be replaced by a schottky diode (STPS2L3A or similar) and a N-Channel Mos-Fet (STN4NF03L or similar)

R

sc

0.1

ΩΩΩΩ

(Note 4)

C1
220µF

C4
470nF

Ceramic

Sense

Vcc

DSQIN(Note 1)
SCL
SDA

GND

LT2

Vo

DETIN
(Note 1)

Byp

EXTM

ADDRESS

DSQOUT

270µH

C6
10nF

C5
470nF

D2
BAT43

see Note 2

0<Vaddr<V

15 ohm

C8
10nF

TM

2.x, not needed if bidirectional DiSEqCTM2.x is

to LNB

Byp

I2C BUS INTERFACE

Data transmission from main µP to the LNBP21
and viceversa takes place through t he 2 wires I2C
bus interface, consisting of the two lines SDA and
SCL (pull-up resistors to positive supply voltage
must be externally connected).

DATA VALIDITY
As shown in fig. 1, the data on the SDA line must

be stable during the high period of the clock. The
HIGH and LOW state of the da ta line can only
change when the c lock s ignal on the SCL line is
LOW.

ACKNOWLEDGE
The mas ter (µP) puts a resistive HIGH level on the

SDA l ine during the acknowledge clock pulse (see
fig. 3). The peripheral (LNBP21) that
acknowledges has to pull-down (LOW) the SDA
line during the acknowled ge clock pulse, so that
the SDA line is stable LOW during this clock pulse.
The peripheral which has been addressed has to
generate an ac k nowledge after the reception of
each byte, other-wise the SDA line remains at the
HIGH l ev el during the ninth clock pulse time. In
this case the master transm it ter can generate t he
STOP information in order to abort the transfer.

START A ND S TOP CONDITIONS
As shown in fig.2 a start condition is a H IG H to

LOW transition of the SDA line while SCL is HIGH.

The LNBP21 won't gen-erate the acknowledge if
the Vcc s upply is below the Undervoltage Lockout
threshold (6.7V typ.).

The stop condition is a LOW to HIGH transition of
the SDA line while SCL is HIGH. A STOP
condi-tions must be sent before each START
condition.

TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the

LNBP21, th e µP can use a simpler transmission:

BYTE FORMAT
Every byte transferred to the SDA line must

contain 8 bits. Each byte must be followed by an
ac-knowledge bit. The MSB is transferred first.

simply it waits one clock without checking the
slave acknowledging, and sends the new data.

This approach of cou rse is less protected from
misworking and decreases the noise immuni ty.

5/20

LNBP21

Figure1 : DATA V ALIDITY ON THE I2CBUS

2

Figure2 : TIMING DIAGRAM ON I

CBUS

Figure3 : ACKNOWLEDGE ON I

6/20

2

CBUS

LNBP1 S O FTWARE DESCRIPTION

LNBP21

INTERFACE P ROTOCO L
The interface protocol comprises:

- A s tart condition (S)

CHIP ADDRESS DATA

MSB LSB MSB LSB

S0001000R/WACK ACKP

ACK= Acknowledge
S= Start
P= Stop
R/W= Read/Write

- A chip address byte = hex 10 / 11 (the LSB bit
determines read(=1)/write(=0) transmission)

- A sequence of data (1 byte + acknowledge)

- A stop condition (P)

SYSTEM REGISTER (SR, 1 BYTE)

MSB LSB
R, W R, W R, W R, W R, W R, W R R

PCL ISEL TEN LLC VSEL EN OTF OLF

R,W= read and write bit
R= Read-only bit
All bits resetto 0 at Power-On

TRANSMITTED DATA (I2CBUSWRITEMODE)
When the R/W bit in the chip address is set to 0,

the main µP can write on the System Register
(SR) of the LNBP21 via I

2

C bus. Only 6 bits out of

the 8 available c an be written by the µP, since the
re-maining 2 are left to the diagnostic flags, and
are read-only.

PCL ISEL TEN LLC VSEL EN OTF OLF Function

=13V, VUP=16V Loopthrough switch open

001XX
011XX
101XX

111XX
0 1 X X 22KHz tone is controlled by DSQIN pin
1 1 X X 22KHz tone is ON, DSQIN pin disabled

01XX

11XX
0 1 X X Pulsed (dynamic) current limiting is selected
1 1 X X Static current limiting is selected

X X X X X 0 X X Power blocks disabled, Loopthrough switch closed

X= don't care.
Values are typical unless otherwise specified

RECEIVED DATA (I2C bus READ MODE)
The LNBP21 can provide to the Master a copy of

the S YSTEM RE GI STER information via I2C bus
in read mode. The read mode is Mas ter activated
by sending the chip address with R/W bit set to 1.
At the following master generated clocks bits, the

V

OUT

V

=18V, VUP=21V Loopthrough switch open

OUT

=14V, VUP=17V Loopthrough switch open

V

OUT

=19V, VUP=22V Loopthrough switch open

V

OUT

I

OUT(min)

I

OUT(min)

=500mA, I
=400mA, I

OUT(max)
OUT(max)

=650mA ISC=300mA
=550mA ISC=300mA

LNBP21 issues a byte on the SDA data bus line
(MSB transmitted first).
At the ninth clock bit the MCU master can :

- acknowledge the reception, starting in this way
the transmission of another byte from the
LNBP21;

7/20

LNBP21

- no acknowledge, stopping the read mode
communication.

While the whole register is read back by the µP,
only the two read-only bits OLF and OTF convey
di-agnostic informations about the LNBP21.

PCL ISEL TEN LLC VSEL EN OTF OLF Function

<140°C, normal operation

0

These bits are read exactly the same as

they were left after last write operation

Values are typical unless otherwise specified

1

POWER-ON I2C INTERFACE RESET
TheI2CinterfacebuiltintheLNBP21is

automatically reset at power-on. As long as the
Vcc stays be-low the UnderVoltage Lock out
threshold (6.7V typ.), the interface will not respond
to any I2C com-mand and the System Register
(SR) is initialised to all zeroes, thus keeping the
power blocks disabled. Once the Vcc rises above

7.3V, the I2C interface bec omes operative and the
SR can be configured by the main µP. T his is due
to About 500mV of hysteresis provided in the UVL
threshold to avoid false retriggering of the
Power-On reset circuit.

T

J

T

>150°C, power block disabled, Loothrough switch open

J

0
1

I

OUT<IOMAX

I

OUT>IOMAX

, normal operation
, overload protection triggered

PWK data i n accordance to the DiSEqC pro-tocol.
Full compliance of the sy stem to the s pec ificati on
is thus not implied by the bare use of the LNBP21.

The system designer should also take in
consideration the bus hardware requirements,
that include the source im pedance of the Master
Transmitter measured at 22KHz. To limit the
attenuation at car-rier frequency, this impedance
has to be 15ohm at 22KHz, dropping to zero ohm
at DC to allow the power flow towards the
peripherals. This c an be simply accomplished by
the LR termination put on the OUT pin of the
LNBP, as shown in the Typical Application Circuit
on page 5.

DiSEqCTM IMPLEMENTATION
The LNBP21 helps the system designer to

implement the bi-directional (2. x ) DiSEqC protocol
by al-lowing an easy PWK modulation/
demodulation of the 22 KHz carrier. The PWK dat a
are exchanged between the LNBP21 and the
main µP using logic levels that are compatible with

Unidirectional (1.x) DiSEqC and non-DiSEqC
systems normally don't need this termination, and
the OUT pin c an be directly connected to the LNB
supply port of the Tuner. T here is also no need of
Tone Decoding, thus, it is recommended to
connect t he DETIN and DSQOUT pins t o ground
to avoid EMI.

both 3. 3 and 5V mi-crocon trollers. This data
exchange is made through two dedicated pins,
DSQIN and DSQOUT, in or-der to maintain the
timing relationships between the PWK data and
the PWK modul ation as accurate as possible.
These two pins should be directly connected to
two I/O pins of the µP, thus leaving to the resident
firmware the task of encoding and decoding t he

ADDRESS PIN
Connecting this pin to GND the Chip I 2C interface

address is 0 001000, but, it is pos s ible to choice
among 4 different addresses simply setting this
pin at 4 fixed voltage levels (see table on page

10).

ELECTRICALCHARACTERISTICSFORLN BP SERIES(T
PCL=0, DSQIN=0, V

2

for I

C access to the system register)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Supply Voltage IO= 500 mA TEN=VSEL=LLC=1 8 15 V

V

IN

V

8/20

LT1 Input Voltage 20 V

LT1

Supply Current IO= 0mA TEN=VSEL=LLC=1 EN=1 20 40 mA

I

IN

V

Output Voltage IO= 500 mA VSEL=1 LLC=0 17.3 18 18.7 V

O

=12V, I

IN

=50mA, unless otherwise specified. See software description sec tion

OUT

= 0to85°C,EN=1,LLC=0,TEN=0, ISEL=0,

J

EN=0 2.55mA

LLC=1 19 V

LNBP21

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

Output Voltage IO= 500 mA VSEL=0 LLC=0 12.5 13 13.5 V

O

LLC=1 14 V

f

A

D

G
V

Z

f

DETIN

V

Z

T

∆T

∆V

∆V

I

t

TONE

I

Line Regulation V

O

=15 to 18V VSEL=0 5 40 mV

IN1

VSEL=1 5 60 mV

Load Regulation VSEL=0 or 1 I

O

Output Current Limiting ISEL=1 400 550 mA

MAX

= 50 to 500mA 200 mV

OUT

ISEL=0 500 650 mA

I

Output Short Circuit Current ISEL=1 200 mA

SC

ISEL=0 300 mA

Dynamic Overload

OFF

protection OFF Time

t

Dynamic Overload

ON

protection ON Time

PCL=0 Output Shorted 900 ms

PCL=0 Output Shorted t

/10 ms

OFF

Tone Frequency TEN=1 20 22 24 KHz
Tone Amplitude TEN=1 0.55 0.72 0.9 Vpp

TONE

Tone Duty Cycle TEN=1 40 50 60 %

TONE

Tone Rise and Fall Time TEN=1 5 10 15 µs

t

r,tf

External Modulation Gain ∆V

EXTM

External Modulation Input

EXTM

Voltage
External Modulation

EXTM

Impedance
Loopthrough Switch Voltage

V

LT

Drop (lt1 to LT2)

f

DC/DC Converter Switch

SW

Frequency
Tone Detector Frequency

OUT

/∆V

, f = 10Hz to 40KHz 6

EXTM

AC Coupling 400 mVpp

f = 10Hz to 50KHz 260 Ω

EN=0, ILT=300mA, VMI=12 or 19V 0.35 0.6 V

220 kHz

0.4Vpp sinewave 18 24 kHz

Capture Range
Tone Detector Input

DETIN

Amplitude
Tone Detector Input

DETIN

Impedance

V

Overload Flag Pin Logic

OL

LOW
Overload Flag Pin OFF

I

OZ

State Leakage Current
DSQIN Input Pin Logic

V

IL

LOW

V

DSQIN Input Pin Logic

IH

HIGH

I

DSQIN Pins Input Current VIH=5V 15 µA

IH

Output Backward Current EN=0 V

OBK

Temperature Shutdown

SHDN

Threshold
Temperature Shutdown

SHDN

Hysteresis

fIN=22kHz sinewave 0.2 1.5 Vpp

150 kΩ

Tone present IOL=2mA 0.3 0.5 V

Tone absent VOH=6V 10 µA

2V

= 18V -4 -10 mA

OBK

150 °C

15 °C

0.8 V

9/20

LNBP21

GATE AND SE NSE ELECTRICAL CHARACTERISTICS (TJ= 0 to 85°C, VIN=12V)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

R

DSON-L

R

DSON-H

V

SENSE

2

C ELECTRICAL C HARACTERISTICS (TJ=0to85°C,VIN=12V)

I

Gate LOW R
Gate LOW R

DSON
DSON

Current Limit Sense Voltage 200 mV

Symbol Parameter Test Conditions Min. Typ. Max. Unit

LOW Level Input Voltage SDA, SCL 0.8 V

V

IL

HIGH Level Input Voltage SDA, SCL 2 V

V

IH

Input Current SDA, SCL, VIN= 0.4 to 4.5v -10 10 µA

I

IH

DSQIN Input Pin Logic

V

IL

LOW

f

Maximum Clock Frequency SCL 500 KHz

MAX

I

=-100mA 4.5 Ω

GATE

I

=100mA 4.5 Ω

GATE

SDA (open drain), IOL= 6mA 0.6 V

ADDRESS PIN CHARACTERISTICS (T

= 0 to 85°C, VIN=12V)

J

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

ADDR-1

V

ADDR-2

V

ADDR-3

V

ADDR-4

"0001000" Addr Pin Voltage 0 0.7 V
"0001001" Addr Pin Voltage 1.3 1.7 V
"0001010" Addr Pin Voltage 2.3 2.7 V
"0001011" Addr Pin Voltage 3.3 5 V

TEST CIRCUIT

1N4001

ILT

V

A

Scope Probe

VEXTM, VDETIN

MI,VOBK

Load

VOH/I

OL

Vin

From I2C
Master

Pulse Gen.

STPS2L30A

L1=22µH

IIN

A

{

SDA
SCL

STN4NF03L

Rsc

0.1

ΩΩΩΩ

470nF

470nF

220µF

220µF 470nF

Vup

Gate

Sense

Vcc

SDA
SCL

DSQIN

BYP

ADDRESS

LNBP21

LT1

LT2

OUT

EXTM

DETIN

DSQOUT

10nF

V

LT

V

,IOBK

IO

10nF

A

VOUT

20µF

10nF

V

A

OL

V

IOZ /IOL

V

10/20

LNBP21

TYPICAL CHARACTERISTICS (unless otherwise specified T
Figure 4 : Output Voltage vs Temperature

Figure 5 : Output Voltage vs Temperature

Figure 7 : Line Regulation vs Temperature

Figure 8 : Load Regulation vs Temperature

=25°C)

j

Figure 6 : Line Regulation vs Temperature

Figure 9 : Load Regulation vs Temperature

11/20

LNBP21

Figure 10 : Supply Current vs Temperature

Figure 11 : Supply Current vs Temperature

Figure 13 : Dynamic Overload Protection OFF

Time vs Temperature

Figure 14 : Output Current Limiting vs

Temperature

Figure 12 : Dynamic Overload Protection ON

Time vs Temperature

12/20

Figure 15 : Output Current Limiting vs

Temperature

LNBP21

Figure 16 : Tone Frequency vs Temperature

Figure 17 : Tone Amplitude vs Temperature

Figure 19 : Tone Rise Time vs T emperature

Figure 20 : Tone Fall Time vs Temperature

Figure 18 : Tone Duty Cicle vs Tem perat ure

Figure 21 : Loopthrought Switch Drop Voltage vs

Temperature

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Figure 22 : Loopthrought Switch Drop Voltage vs

Temperature

Figure 23 : Loopthrought Switch Drop Voltage vs

Loopthrought Current

Figure 25 : DSQOUT Pin Logic Low vs

Temperature

Figure 26 : Undervoltage Lockout Threshold vs

Temperature

Figure 24 : Loopthrought Switch Drop Voltage vs

Loopthrought Current

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Figure 27 : Output Backward Current vs

Temperature

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V

12V,I

TEN=1

V

12V,I

TEN=0

V

12V,I

TEN=0

V

12V,I

TEN=0

Figure 28 : DC/DC Conv ert er Efficiency vs

Temperature

Figure 29 : Current Lim it Sense vs Tem perature

Figure 31 : DSQIN Tone Enable Transient

Response

=

CC

=50mA,EN=1,

O

Figure 32 : DSQIN Tone Enable Transient

Response

Figure 30 : 22kHz Tone

=

CC

=50mA,EN=

O

=

CC

=50mA,EN=1,

O

Figure 33 : DSQIN Tone Disable Transient

Response

=

CC

=50mA,EN=1,

O

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LNBP21

V

12V,I

VSEL=f

1

V

12V,I

VSEL=f

1

Figure 34 : Output Voltage Transient Response

from 13V to 18V

=

CC

=50mA,

O

rom0to1,EN=

TERMAL DESIGN NOTES

During normal operation, this device dissipates
some power. At maximum rated output current
(500mA), the voltage drop on the linear regulator
lead t o a total dissipated power that is of about

1.7W. The heat generated requires a suitable
heatsink to keep the junction temperature below
the overtemperature protection threshold.
Assuming a 40°C temperature in side the
Set-Top-Box case, the total Rthj-amb has to be
less than 50°C/W.

While this can be easily achieved using a
through-hole power package that can be attached
to a small heatsink or to the metallic frame of the
receiver, a surface mount power package must
rely on PCB solutions whose thermal efficiency is
often limited. The simplest solution is to use a
large, con-tinuous copper area of the G ND layer to
dissipate the heat coming from the IC body.

The SO-20 package of this IC has 4 GND pins that
are not just intended for electrical GND
connec-tion, but also to provide a low thermal
resistance path between the silicon chip and the
PCB heatsink. Given an Rthj-c equal to 15°C/W,
a maximum of 35°C/W are left to the PCB
heatsink. This figure is achieved if a minimum of
25cm2 copper area i s placed just below the IC

Figure 35 : Output Voltage Transient Response

from 13V to 18V

=

CC

=50mA,

O

rom1to0,EN=

body. This area can be the inner GND layer of a
multi-layer PCB, or, in a dual layer P CB , an
unbroken GND area even on the opposite side
where the IC is placed. In both cases, the thermal
path between the IC GND pins and the dissipating
copper area must exhibit a low th ermal resistance.

In figure 4 , it is shown a sugges te d layout for the
SO-20 package with a dual lay er PCB, where the
IC Ground pins and the square dissipating area
are thermally connected through 32 vias holes,
filled by solder. This arrangement, when
L=50mm, achieves an Rthc-a of about 25°C/W.

Different layouts are possible, too. Basic
principles, however, suggest to keep the IC and its
ground pins approx imately in the middle of the
dissipating area; to provide as many vias as
possible;tode-signadissipatingareahavinga
shape as square as possible and not interrupted
by other copper traces.

Due to presence of an expo sed pad co nnec t ed to
GND below the IC body, the PowerSO-20
package has a Rthj-c much lower than the SO-20,
only 2°C/W. As a result, muc h lower copper area
must be provided to di ssip ate the same power and
minimum of 12cm2 coppe r area i s enough, see
figure 5.

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Figure 36 : SO-20 SUGGESTED PCB HEATSINK LAYOUT

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Figure 37 : PowerSO-20 SUGGESTED PCB HEATSINK LAYOUT

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SO-20 MECHANICAL DATA

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 2.65 0.104
a1 0.1 0.2 0.004 0.008
a2 2.45 0.096

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.012

C 0.5 0.020
c1 45˚ (typ.)

D 12.60 13.00 0.496 0.512

E 10. 00 10.65 0.393 0.419

e 1.27 0.050

e3 11.43 0.450

F 7.40 7.60 0.291 0.300

L 0.50 1.27 0.020 0.050
M 0.75 0.029
S ˚ (max.)

mm. inch

8

18/20

PO13L

PowerSO-20 MECHANICAL DATA

LNBP21

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

A 3.60 0.1417

a1 0.10 0.30 0.0039 0.0118
a2 3.30 0.1299
a3 0 0.10 0 0.0039

b 0.40 0.53 0.0157 0.0209
c 0.23 0.32 0.0090 0.0013

D (1) 15.80

16.00

0.6220 0.630
E 13.90 14.50 0.5472 0.5710
e 1.27 0.0500

e3 11.43 0.4500

E1 (1) 10.90 11.10 0.4291 0.4370

E2 2.90 0.1141

G 0 0.10 0.0000 0.0039

h 1.10 0.0433
L 0.80 1.10 0.0314 0.0433
N0˚10˚

1
S0˚ 8˚0˚ 8˚
T 10.0 0.3937

(1) “D and E1” do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.006”)

E2

h x45˚

NN

a2

b

DETAIL A

110

e3

D

T

e

1120

A

E1

DETAIL B

PSO20MEC

R

a3

Gage Plane

lead

E

DETAIL B

0.35

S

a1

L

c

DETAIL A

slug

-C-

SEATING PLANE

GC

(COPLANARITY)

0056635

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LNBP21

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