2Axis - 2g/6g LINEAR ACCELEROMETER
■ 3V TO 5.25V SINGLE SUPPLY OPERATION
■ THE SENSITIVITY IS ADJUSTED WITH A
TOTAL ACCURACY OF ±10%
■ THE OUTPUT VOLTAGE, OFFSET,
SENSITIVITY AND TEST VOLTAGE ARE
RATIOMETRIC TO THE SUPPLY VOLTAGE
■ DEVICE SENSITI VITY IS ON-CHI P FACTORY
TRIMMED
■ EMBEDDED SELF TEST
■ HIGH SHOCK SURVIVABILITY
DESCRIPTION
The LIS2L02AQ is a dual-axis linear accelerometer
that includes a sensing element and an IC interface
able to take the information from the sensing el ement
and to provide an analog signal to the exter nal wor ld.
The sensing element, capable to detect the acceleration, is manufactured using a dedicated process
called THELMA (Thick Epi-Poly Layer for Microactuators and Accelerometers) developed by ST to produce inertial sensors and actuators in silicon.
The IC interface instead is manufactured using a
CMOS process that allow s high l evel o f integration to
design a dedicated circuit which is trimmed to better
match the sensing element characteristics.
The LIS2L02AQ has a user selectable full scale of
2g, 6g and it is capable of measuring accelerations
LIS2L02AQ
INERTIAL SENSOR:
PRODUCT PREVIEW
QFN-44
ORDERING NUMBER: LIS2L02AQ
over a maximum bandwidth of 4.0 K Hz for both the X
and Y axis. The device bandwidth m ay be r educed by
using external capacitances. A self-test capability allows the user to check the functioning of the system.
The LIS2L02AQ is available in plastic SMD package
and it is specified over a temperature range extending from -40°C to +85°C.
The LIS2L02AQ belongs to a family of products suitable for a variety of applications:
– Antitheft systems
– Inertial navigation
– Virtual reality input devices
– Vibration Monitoring, recording and com pen-
sation
– Appliance control
– Robotics
BLOCK DIAGRAM
S1X
S1Y
rot
S2Y
S2X
VOLTAGE & CURRENT
REFERENCE
December 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
MUX
TRIMMING CIRCUIT
TEST INTERFACE
AMPLIFIE R
DEMUX
CLOCK
&
PHASE GENERATOR
S/HCHARGE
S/H
&
Routx
Routy
Voutx
Vouty
1/6
LIS2L02AQ
PIN DESCRIPTION
N° Pin Function
1 to 3 NC Internally not connected
4 GND 0V supply
5 Vdd Power supply
6 Vouty Output Voltage
7 ST Self Test (Logic 0: normal mode; Logic 1: Self-test)
8 Voutx Output Voltage
9-13 NC Internally not connected
14 PD Power Down (Logic 0: normal mode; Logic 1: Power-Down mode)
15 NC Internally not connected
16 FS Full Scale selection (Logic 0: 2g Full-scale; Logic 1: 6g Full-scale)
17-18 Reserved Leave unconnected
19 NC Internally not connected
20 Reserved Leave unconnected
21 NC Internally not connected
22-23 Reserved Leave unconnected
24-25 NC Internally not connected
26 Reserved Connect to Vdd or GND
27 Reserved Leave unconnected or connect to Vdd
28 Reserved Leave unconnected or connect to GND
29-44 NC Internally not connected
PIN CONNECTION
(Top view)
1
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
NCNCNCNCNCNCNCNCNCNCNC
Y
NC
NC
NC
GND
X
Vdd
Vouty
ST
Voutx
NC
NC
NC
NC
NCPDNC
LIS2L02AQ
FS
Reserved
Reserved
NC
Reserved
Reserved
Reserved
NC
NC
NC
NC
NC
Reserved
Reserved
Reserved
NC
NC
Reserved
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LIS2L02AQ
ELECTRICAL CHARACTERISTCS
(Temperature range -40°C to +85°C)
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
V
Supply voltage 3 5.25 V
dd
Supply current 1.0 mA
I
dd
Zero-g level T
off
amb
= 25°C
Vdd/2-10% Vdd/2 Vdd/2+10% V
ratiometric to Vdd
A
Acceleration range 0V on FS pin ±1.8 ±2.0 ±2.2 g
r
V
on FS pin ±6.0 g
dd
Sensitivity ratiometric to
S
o
V
dd
T
= 25°C
amb
Full-scale = 2g
= 25°C
T
amb
Vdd/5–10% Vdd/5 Vdd/5+10% V/g
Vdd/15–10% Vdd/15 Vdd/15+10% V/g
Full-scale = 6g
N
Non Linearity Best fit straight line
L
±0.3 %
X, Y axis
Full-scale = 2g
Sensing Element
f
uc
X, Y axis 4.0 KHz
Resonant Frequency
a
Acceleration noise
n
density
V
Self test output voltage
t
Ratiometric to Vdd
Vdd = 5V
Full-scale = 2g
T
= 25°C
amb
@ 5V
50
µg/
100 mV
Hz
V
Self test input Logic 0 level 0 0.8 V
st
Logic 1 level 2.8 V
R
C
Output impedance 100 kΩ
out
Capacitive load drive 320 pF
load
dd
V
1 FUNCTIONALITY
1.1 Sensing element
The THELMA process is utilized to create a surface micro-machined accelerometer. The technology allows to
carry out suspended silicon structures which are attached to the substrate in a few points called anchors and
free to move on a plane parallel to the substrate itself. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding
phase.
The equivalent circui t for the sensing element is s hown in the below figure; when a l inear acc eleration is appl ied,
the proof mass displaces from its nominal pos ition, causi ng an imbalance in the capacitiv e half- bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor.
The nominal value of the capacitors, at steady state, is few pF and when an acceleration is applied the maximum
variation of the capacitive load is few tenth of pF.
3/6
LIS2L02AQ
Figure 1. Equivalent electrical circuit
C
ps1
C
pr
C
ps2
C
ps1
C
pr
C
ps2
R
s1
S1x
C
s1x
R
r
C
s2x
S2x
R
s2
R
s1
S1y
C
s1y
R
r
C
s2y
S2y
R
s2
rot
1.2 IC Interface
The complete signal processing uses a fully differential structure, while the final stage converts the differential
signal into a single-ended one to be compatible with the external world.
The first stage is a low-noise capacitive amplifier that implements a Correlated Double Sampling (CDS) at its
output to cancel the offset and the 1/f noise. The produced signal is then sent to two different S&Hs, one for
each channel, and made available to the outside.
The low noise input amplifier operates at 200 kHz while the two S&Hs operate at a sampling frequency of 66
kHz. This allows a large oversampling ratio, which leads to in-band noise reduction and to an accurate output
wavefor m .
All the analog par ameters (output offs et vol tage and sensitivity) are ratiometr ic to the v oltage supply . Increas ing
or decreasing the voltage supply, the sensitivity and the offset will increase or decrease linearly. The feature
provides the cancellation of the error related to the voltage supply along an analog to digital conversion chain.
1.3 Factory calibration
The IC interface is factory calibrated to provide to the final user a device ready to operate. The parameters which
are trimmed are: gain, offset, common mode and internal clock frequency.
The trimming values are stored inside the device by a poly-fuse structur e. Any time the device is turned on, the
memorized bits are downloaded into the registers to be employed during the normal operation. The poly-fuse
approach allows the final user to utilize the device without any need for further calibration
4/6
LIS2L02AQ
mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.70 1.80 1.90 0.067 0.071 0.075
A1 0.19 0.21 0.007 0.008
b 0.20 0.25 0.30 0.008 0.01 0.012
D 7.0 0.276
E 7.0 0.276
e 0.50 0.020
J 5.04 5.24 0.198 0.206
K 5.04 5.24 0.198 0.206
L 0.38 0.48 0.58 0.015 0.019 0.023
P 45 REF 45 REF
OUTLIN E AND
MECHANI CAL DATA
QFN-44 (7x7x1.8mm)
Quad Flat Package No lead
M
G
M
34
33
23
22
N
44
1
11
12
44
1
DETAIL "N"
SEATING PLANE
DETAIL G
5/6
LIS2L02AQ
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent r i ght s of STMi croelectr oni cs. Spec i fications mentioned i n this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approva l of STMicroel ectronics.
The ST logo is a registered trademark of STMicroelectronics
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