SGS Thomson Microelectronics L9903 Datasheet
1/17
L9903
June 2000
This ispreliminary information ona new product now in development. Details are subject to change without notice.
■
OPERATING SUPPLY VOLTAGE 8V TO 20V,
OVERVOLTAGE MAX. 40V
■
OPERATING SUPPLY VOLTAGE 6V WITH
IMPLEMENTED STEPUP CONVERTER
■ QUIESCENT CURRENT IN STANDBY MODE
LESS THAN 50µA
■
ISO 9141 COMPATIBLE INTERFACE
■
CHARGE PUMP FOR DRIVING A POWER
MOS AS REVERSE BATTERY PROTECTION
■ PWM OPERATION FREQUENCY UP TO
30KHZ
■ PROGRAMMABLE CROSS CONDUCTION
PROTECTION TIME
■
OVERVOLTAGE, UNDERVOLTAGE, SHORT
CIRCUIT AND THERMAL PROTECTION
■
REAL TIME DIAGNOSTIC
DESCRIPTION
Control circuit for power MOS bridge driver in automotive applications with ISO 9141bus interface.
SO20
ORDERING NUMBER: L9903
PRODUCT PREVIEW
MOTOR BRIDGE CONTROLLER
BLOCK DIAGRAM
VS
DIR
PWM
EN
RX
TX
CP
CB1
GH1
S1
GL1
CB2
GH2
S2
GL2
K
=
PR
VCC
=
=
ISO-Interface
VCC
GND
ST
Ref er enc e
BIAS
Char ge
pump
Control Logic
Overvoltage
Undervoltage
PWM
R
DIR
R
RX
R
TX
R
0.5 •V
VS
R
S2
R
GL2
R
GL1
R
S1
R
CP
R
EN
VCC
Timer
I
KH
V
S2TH
Thermalshutdown
V
S1TH
DG
VCC
R
DG
V
STH
f
ST
=
+
10
1
2
4
5
3
6
7
8
20
9
16
15
17
18
19
14
12
13
11
L9903
2/17
PIN FUNCTION
PIN CONNECTION (Top view)
N° Pin Description
1 ST Open Drain Switch for Stepup converter
2 DG Open drain diagnostic output
3 PWM PWM input for H-bridge control
4 EN Enable input
5 DIR Direction select input forH-bridge control
6 PR Programmable cross conduction protection time
7 RX ISO 9141 interface, receiver output
8 TX ISO 9141 interface, transmitter input
9 K ISO 9141 Interface,bidirectional communication K-line
10 VS Supply voltage
11 CP Charge pump for driving a power MOS as reverse battery protection
12 GH1 Gate driver for power MOS highside switch in halfbridge 1
13 CB1 External bootstrap capacitor
14 S1 Source/drain of halfbridge 1
15 GH2 Gate driver for power MOS highside switch in halfbridge 2
16 CB2 External bootstrap capacitor
17 S2 Source/drain of halfbridge 2
18 GL2 Gate driver for power MOS lowside switch in halfbridge 2
19 GL1 Gate driver for power MOS lowside switch in halfbridge 1
20 GND Ground
ST
DG
PWM
EN
DIR
RX
PR
TX
K GH1
CB1
S1
CB2
GH2
S2
GL2
GL1
GND1
3
2
4
5
6
7
8
9
18
17
16
15
14
12
13
11
19
10
20
VS CP
SO20
3/17
L9903
ABSOLUTEMAXIMUM RATINGS
For externally applied voltages or currents exceeding these limits damage of the device may occur!
All pins of the IC are protected against ESD. The verification is performed according to MIL883C, human body
model withR=1.5k
Ω, C=100pF and discharge voltage ±2kV, corresponding to a maximum discharge energy of
0.2mJ.
Symbol Parameter Value Unit
V
CB1,VCB2
Bootstrap voltage -0.3 to 40 V
I
CB1,ICB2
Bootstrap current -100 mA
V
CP
Charge pump voltage -0.3 to 40 V
I
CP
Charge pump current -1 mA
V
DIR,VEN
,V
PWM,VTX
Logic input voltage -0.3 to 7 V
I
DIR,IEN
,I
PWM,ITX
Logic input current ±1mA
V
DG,VRX
Logic output voltage -0.3 to 7 V
I
DG,IRX
Logic output current -1 mA
V
GH1,VGH2
Gate driver voltage -0.3 to VSX+10 V
I
GH1,IGH2
Gate driver current -1 mA
V
GL1,VGL2
Gate driver voltage -0.3 to 10 V
I
GL1,IGL2
Gate driver current -10 mA
V
K
K-line voltage -20 to V
S
V
V
PR
Programming input voltage -0.3 to 7 V
I
PR
Programming input current -1 mA
V
S1,VS2
Source/drain voltage -2 to VVS+2 V
I
S1,IS2
Source/drain current -10 mA
V
ST
Output voltage -0.3 to 40 V
I
ST
Step up output current -1 mA
V
VSDC
DC supply voltage -0.3 to 27 V
V
VSP
Pulse supply voltage (T £ 500ms) 40 V
I
VS
DC supply current -10 mA
L9903
4/17
THERMAL DATA
1. see application note 110 for SO packages.
ELECTRICALCHARACTERISTCS (8V < V
VS
< 20V, VEN=HIGH, -40°C≤ T
J
≤ 150°C, unless otherwise spec-
ified. The voltages are refered to GND and currents are assumed positive, when current flows into the pin.
Symbol Parameter Value Unit
T
J
Operating junction temperature -40 to 150 °C
T
JSD
Junction temperature thermal shutdown threshold min 150 °C
T
JSDH
Junction thermal shutdown hysteresis typ 15 °C
R
th j-amb
Thermal resistance junction to ambient
1)
85 °C/W
Symbol Parameter Test Conditio n Min. Typ. Max. Unit
Supply (VS)
V
VS OVH
Overvoltage disable HIGH
threshold
20 22 24 V
V
VSOVh
Overvoltagethreshold hysteresis
2)
1.6 V
V
VS UVH
Undervoltage disable HIGH
threshold
67V
V
VS UVh
Undervoltage threshold
hysteresis
2)
0.66 V
I
VSL
Supply current VEN=0;VVS= 13.5V; TJ<85°C50µA
I
VSH
Supply current VVS= 13.5V; VEN= HIGH;
V
DIR
= LOW;
f
PWM
= 20kHz; C
CBX
= 0.1µF;
C
GLX
= 4.7nF; C
GHX
= 4.7nF;
R
PR
=10kΩ;CPR= 150pF
20 mA
Enable input (EN)
V
ENL
Low level 1.5 V
V
ENH
High level 3.5 V
V
ENh
Hysteresis threshold
2)
1V
R
EN
Input pull down resistance VEN=5V 16 50 100 kΩ
H-bridge control inputs (DIR, PWM)
V
DIRL
V
PWML
Input low level 1.5 V
V
DIRH
V
PWMH
Input high level 3.5 V
V
DIRh
V
PWMh
Input threshold hysteresis
2)
1V
R
DIR
R
PWM
Internal pull up resistance
to internal VCC
3)
V
DIR
=0;V
PWM
= 0 16 50 100 kΩ
5/17
L9903
DIAGNOSTIC output (DG)
V
DG
Output drop IDG= 1mA 0.6 V
R
DG
Internal pull up resistance
to internal VCC
3)
VDG=0V 10 20 40 kΩ
Programmable cross conduction protection
4)
N
PR
Threshold voltage ratio V
PRH
/
V
PRL
RPR= 10kΩ
1.8 2 2.2
I
PR
Current capability
V
PR
=2V
-0.5 mA
ISO interface, transmission input(TX)
V
TXL
Input low level 1.5 V
V
TXH
Input high level 3.5 V
V
TXh
Input hysteresis voltage 2) 1 V
R
TX
Internal pull up resistance to
internal VCC 3)
VTX= 0 10 20 40 kΩ
ISO interface, receiver output (RX)
V
RXL
Output voltage high stage
TX = HIGH; I
RX
=0;VK=V
VS
4.5 5.5 V
R
RX
Internal pull up resistance
to internal VCC
3)
TX = HIGH;
V
RX
=0V
51020k
Ω
R
RXON
ON resistance to ground TX = LOW;
I
RX
=1mA
40 90 W
t
RXH
Output high delay time Fig. 1 0.5 µs
t
RXL
Output low delay time 0.5 µs
ISO interface, K-line (K)
V
KL
Input low level -20V 0.45 ·
V
VS
V
KH
Input high level 0.55 ·
V
VS
V
VS
V
Kh
Input hysteresis voltage 2) 0.025·
V
VS
0.8V
I
KH
Input current VTX= HIGH -5 25 µA
R
KON
ON resistance to ground VTX= LOW; IK=10mA 10 30 W
I
KSC
Short circuit current VTX= LOW 40 130 mA
f
K
Transmission frequency 60 100 kHz
2. not tested in production: guaranteed by design and verified in characterization
3. Internal V
VCC
is 4.5V ... 5.5V
4. see page 18 for calculation of programmable cross conduction protection time
Symbol Parameter Test Conditio n Min. Typ. Max. Unit
ELECTRICAL CHARACTERISTICS
(continued)
L9903
6/17
t
Kr
Rise time VVS= 13.5V; Fig. 1
External loads at K-line:
R
K
=510Ωpull up
to V
VS
CK= 2.2nF to GND
26µs
t
Kf
Fall time 26µs
t
KH
Switch high delay time 4 17 µs
t
KL
Switch low delay time 4 17 µs
t
SH
Short circuit detection time VVS= 13.5V;
TX= LOW
V
K
> 0.55 · V
VS
10 40 µs
Charge pump
V
CP
Charge pump voltage VVS=8V
V
VS
= 13.5V
V
VS
= 20V
V
VS
+
7V
V
VS
+
10V
V
VS
+
10V
VVS+
14V
V
VS
+
14V
V
VS
+14V
I
CP
Charging current
V
CP=VVS
+8V
V
VS
= 13.5V -50 -75 µA
t
CP
Charging time
2)
VCP=VVS+8V
V
VS
= 13.5V
C
CP
= 10nF
1.2 4 ms
f
CP
Charge pump frequency VVS= 13.5V 250 500 750 kHz
Drivers for external highside powerMOS
V
CB1
V
CB2
Bootstrap voltage VVS= 8V; I
CBX
=0;VSX=0
V
VS
=13.5V; I
CBX
=0;VSX=0
V
VS
= 20V; I
CBX
=0;VSX=0
7.5
10
10
14
14
14
V
V
V
R
GH1L
R
GH2L
ON-resistance of SINK stage
V
CBX
= 8V; VSX=0
I
GHX
= 50mA; TJ=25°C
10 W
V
CBX
= 8V; VSX=0
I
GHX
= 50mA; TJ=125°C
20 W
R
GH1H
R
GH2H
ON-resistance of SOURCE stage I
GHX
= -50mA; TJ=25°C
I
GHX
= -50mA; TJ= 125°C
10
20
W
W
V
GH1H
V
GH2H
Gate ON voltage (SOURCE) VVS=VSX= 8V;I
GHX
=0;
C
CBX
= 0.1µF
V
VS
+6.5V
V
VS
+14V
V
VS=VSX
= 13.5V; I
GHX
=0;
C
CBX
= 0.1µF
V
VS
+
10V
V
VS
+14V
V
VS=VSX
= 20V; I
GHX
=0;
C
CBX
= 0.1µF
V
VS
+10V
V
VS
+14V
Symbol Parameter Test Conditio n Min. Typ. Max. Unit
ELECTRICAL CHARACTERISTICS
(continued)
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