SGS Thomson Microelectronics L9823 Datasheet

L9823

Octal Low-Side Driver for bulb, resistive and inductive loads with

serial input control, output protection and diagnostic

■ OUTPUTS CURRENT CAPABILITY UP TO

0.5A

■ CASCADABLE SPI CONTROL FOR

OUTPUTS

■ RESET FUNCTION WITH RESET SIGNAL OR

UNDERVOLTAGE AT V

■ PROGRAMM ABLE INTRINSIC OUTPUT

VOLTAGE CLAMPI N G AT TYP. 5 0V FOR INDUCTIVE SWITCHING

■

OVERCURRENT SHUTDOWN WITH LATCHOFF FOR EVERY WRITE CYCLE (SFPD = LOW)

■ INDEPENDENT THERMAL SHUTDOWN OF

OUTPUTS (SOA PROTECTION)

■

OUTPUT STATUS DATA AVAILABLE ON THE SPI USING 8-BIT I/O PROTOCOL UP TO 3.0 MHZ

■ LOW STANDBY CURRENT WITH RESET =

LOW (TYP 35µA @ VDD)

■ OPEN LOAD DETECTION (OUTPUTS OFF)

■ SINGLE V

LOGIC SUPPLY

■ HIGH EMS IMMUNITY AND LOW EME

(CONTROLL ED OU T P UT S LOP E S)

■ FULL FUNCTIONALITY OF THE REMAINING

DEVICE AT NEGATIVE VOLTAGE DROP ON

SO24 (20+2+2)

ORDERING NUMBER: L9823

OUTPUTS (-1,5V OR -3,0A)

■ OUTPUT MODE PROGRAMMABLE FOR

SUSTAINED CURRENT LIMIT OR SHUTDOWN

DESCRIPTION

L9823 is a Octal Low-Side Driver Circuit, dedicated for automotive applications. Output voltage clamping is provided for flyback current recirculation, when inductive loads are driven. Chip Select and cascadable Serial 8-bit Interface for outputs control and diagnostic data transfer.

BLOCK DIAGRAM

SFPD

CSB

SCLK

Reset

April 2003

SPI

Interface

Shif t Register

Reset

Undervoltage

RESET

OL0

Q0 Q1

SCB

Diag0

Diag1

Diag2

Diag3

Diag4

Diag5

Diag6

Diag7

GND

OT0

17 - 20

Q2 Q3 Q4 Q5 Q6 Q7

Output Latch

Diag0 Diag1 Diag2 Diag3 Diag4 Diag5 Diag6 Diag7

Reset

5 -8

Over

Temperature

Detect

Gate

Control

CH0

CH1

CH2 CH3

CH4 CH5 CH7 CH7

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

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L9823

PIN FUNCTION

N° Pin Description

1 Out 7 Output 7 2 Out 6 Output 6 3 SCLK SCLK. The system clo ck pin (SCLK) clocks the inte rnal shift registers of the L98 23. The serial

input pin (SI) accepts data into the input shift register on the falling edge of the SCLK signal while the serial output pin (SO) shifts data information out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to guarantee validity of data. It is essential that the SCLK pi n be in a log ic low state w hene ver chip select bar pin (CSB) ma kes any transition . For th is reason , it is r ecommend ed thoug h not n ecessary, that the SC LK pin be kept in a low logic state as long as th e device i s not acce ssed (CSB in logic h igh state). Wh en CSB is in a logic h igh state, any signal a t the SCLK and SI p in is ignored and SO is tri- stated (high-impedan ce).

4 SI SI. This pin is fo r the input of ser ial ins tructio n data. SI informati on is r ead in on th e fall ing ed ge

of SCLK. A logic high state present on this pin when the SCLK signal rises will program a specific output O FF, and in turn, turns OFF the specific output on the r ising edge of the CSB signal. Converse ly, a logic low state present on the SI pin wi ll program the output ON, and in turn, turns ON th e specific output on the rising edge of the CSB s ignal. To program the eight outputs of the L9823 ON or O FF, an eight bit serial stream of data is req uired to be en tered into the SI pin starting with Outp ut 7, follo wed by Outpu t 6, Output 5, etc., to Outpu t 0. For eac h rise of the SCLK signal, with CSB held in a logic low state, a databit instruction (ON or OFF) is loaded into t he shift registe r per the da tabit SI state. The shift register i s full after eig ht bits of information have be en ente red. To preserve data integrity, care should be taken to not transition

SI as SCLK transitions from a low-to-high logic state. 5 GND GND 6 GND GND 7 GND GND 8 GND GND 9 SO SO. The serial output (SO) pin is the tri-stateable outp ut from the shift register. The SO pin

remains in a high impe dance state until the CSB pin goes to a logic lo w state. The SO data

reports the drain status, either high or low. The SO pin changes state on the rising edge of SCLK

and reads out on the falling edge of SCLK. When an output is OFF and not faulted, the

corresponding SO databit is a high state. When SO an output is ON, and there is no fault, the

corresponding databit on the SO pin will be a low logic state. The SI / SO shifting of data follows

a first-in-first-out prot ocol with both input and outpu t words transferring the Most Significant Bit

(MSB) first. The SO pin is not affected by the status of the Reset pin.

10 CSB CSB. The system MC U sele cts the L982 3 to be com mun icated with through the use of the CSB

pin. Whenever the pin is in a logic low state, data can be transferred from the MCU to the L9823

and vise versa. C locked-in data from th e MCU is transferre d from the L9823 s hift register and

latched into the powe r outputs o n the ris ing edge of the C SB signa l. On the falling edge of the

CSB signal, dra in status information is transferred fro m the power outp uts and loaded into the

device's shift register. The CSB pin also controls the output driver of the serial output pin.

Whenever the CSB pin goes to a logic low state, the SO pin output driver i s enabled allow ing

information to be transferred from the L9823 to the MCU. To avoid any spurious data, it is

essential that the high-to-low transition of the CSB signal occur only when SCLK is in a logic low

state.

11 Out 5 Output 5 12 Out 4 Output 4 13 Out 3 Output 3

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L9823

PIN FUNCTION

(continued)

N° Pin Description

14 Out 2 Output 2 15 SFPD SFPD. The Short Fault Protect Disable (SFPD) pin is used to disable the overcurrent latch-OFF.

This feature allow s control of incandescent load s where in-rush currents exceed the devi ce's

analog current limits. Essentially the SFPD pin determines whether the L9823 output(s) will

instantly shutdown upon sensing an ou tput short or remain ON in a current limiting m ode of

operation until the output short is removed or thermal shutdown is reac hed. If the SFPD pin is

tied to V

the L9823 output(s) will remain ON in a curr ent limited mode of operation upon

encountering a loa d short to supply. If the SFPD pin is grounded, a sh ort circu it will imm edia tely

shutdown only the output affected. Other outputs not having a fault condition will operate

normally.

16 VDD VDD 17 GND GND 18 GND GND 19 GND GND 20 GND GND 21 NC Not Connected 22 Reset Reset. The Reset pin is active low and used to clear the SPI shift register and in doing so sets all

output switches OF F. With the device in a system with an MCU; upon initial syste m power up,

the MCU h olds the Reset p in of the device i n a logic low state ensuring all outpu ts to be O FF

until the VDD pin voltages are adeq uate for p redic table operatio n. A fter th e L9 823 is Re set, the

MCU is ready to assert system cont rol with all output swi tches initially OFF. The Reset pin is

active low and has an internal pull-down incorpora ted to ensure operational predic tability

should the e xterna l pul l-dow n of the MCU open circ uit. T he in terna l pul l-up i s to afford s afe a nd

easy interfacing to the MCU. The Reset pin of the L9823 should be pulled to a logic low state for

a duration of at least 160ns to ensure reliable Reset.

23 Out 1 Output 1 24 Out 0 Output 0

ABSOLUTE MAXIMUM RATINGS

For voltages and currents applied externally to the device. Exceeding limits may cause damage to the device

Symbol Parameter Value Unit

Inputs and data lines

(CSB, SCLK, SI, Reset, SFPD, SO)

SDO

Outputs (Out0 ... Out7)

OUT Cont

Supply voltage -0.3 to 7 V

Voltage

-0.3 to 7

(CSB, SCLK, SI, Reset, SFPD) Voltage (SO) -0.3 to VDD+0.3 V

Protection diodes current

T ≤ 1ms -20 to 20

Continuous output voltage -1.5 to 45 V

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L9823

ABSOLUTE MAXIMUM RATINGS

(continued)

Symbol Parameter Value Unit

OUT Cont

OUT PEAK

OUTclamp

OUT LIM

Note 1) All inputs are protected against ESD according to MIL 883C; tested with HBM C = 100pF, R = 1500Ω at ±2KV. It corresponds to

Continuous output current -3 to I Output current

Output clamp energy

OUT LIM

to 2

-10 50 mJ

Output current (self limit) 2 A

a dissipat ed energy E ≤ 0.2mJ (data avail abl e upon reques t ).

2) Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3.

3) Max. output clamp energ y at T

= 150°C, using single non-repetitive pulse of 500mA

A A

THERMAL DATA

Symbol Parameter Value Unit

Thermal shutdown

LIM

Thermal resistance (junction-to-Lead)

thjL-one

thjL-all

Thermal shutdown threshold 155 (Min.), 180 (Typ.) °C

Single output (junction lead) 25 (Max.) °C/W All outputs (junction lead) 20 (Max.) °C/W

stg

ELECTRICAL CHARACTERISTCS

Storage Temperature -55 to 150 °C

(4.5V ≤ VDD ≤ 5.5V; -40°C ≤ TJ ≤ 150°C; unless otherwise specified

Symbol Parameter Test Condition Min. Typ. Max. Unit

Supply voltage

DDSTB

DDleak

DDOPM

Standby current leakage current

Operating mode I

Reset = LOW and / or V

DDRES>VDD

< 0.5V

OUT0 ... 7

> 0.5V

= 500mA

35 <1

70 10

6mA SPI - SCLK = 3MHz CSB = LOW SO no load

∆I

DD rev∆IDD

during reverse output

= -2.5A 10 mA

out rev

current

DD RES

Undervoltage Reset Reset of all registers and disable

2.5 3.95 V

of all outputs

Inputs (CSB, SCLK, SI, Reset, SFPD)

Low level -0.3

INL

High level

INH

0.7·V

0.2·V

VDD+0.3

µA µA

V V

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Hysteresis voltage 0.5 1.2

hyst

0.5·V

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