SGS Thomson Microelectronics L9352DIE1 Datasheet
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L9352
June 2002
■
Quad low-side switch
■
2 x 5A designed as conventional switch
■
2 x 2.5A designed as switched current-regulator
■
Low ON-resistance 4 x 0.2Ω (typ.)
■
Power SO-36 - package with integrated
cooling area
■
Integrated free-wheeling and clamping Z-diodes
■
Output slope control
■
Short circuit protection
■
Selective overtemperature shutdown
■
Open load detection
■
Ground and supply loss detection
■
External clock control
■
Recirculation control
■
Regulator drift detection
■
Regulator error control
■
Regulator resolution 5mA
■
Status monitoring
■
Status push-pull stages
■
Electrostatic discharge (ESD) protection
DESCRIPTION
The L9352 is an integrated quad low-side power
switch to drive inductive loads like valves used in
ABS systems. Two of the four channels are current
regulators with current range from 250mA to 2.25A
and an accuracy of 10%.
All channels are protected against fail functions.
They are monitored by a status output.
Figure 1. Pin Connection
36
N.C.
35
IN3
ST4
34
PGND3
33
32
PGND3
Q3
31
Q3
30
29
D3
D3
28
Q2
27
26
Q2
PGND2
25
PGND2
24
23
VS
VDD
22
VCC
21
20
IN2
ST1
19
GND 1
IN4
2
3
ST3
PGND4
4
PGND4
5
6
Q4
Q4
7
D4
8
9
D4
Q1
10
Q1
11
12
PGND1
PGND1
13
EN
14
15
CLK
IN1
16
ST2
17
18
TEST
99AT0060
PowerSO-36 BARE DIE
ORDERING NUMB ERS :
L9352 L9352-DIE1
INTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCH
L9352
2/21
Figure 2. Block Diagram
99AT0059
LOGIC
Overload
Open Load
GND-det.
Overtemperature
Channel 1
Overtemperature
Channel 4
LOGIC
&
DA
Overload
Open Load
GND-det.
IPD
IPD
LOGIC
Overload
Open Load
GND-det.
Overtemperature
Channel 2
Overtemperature
Channel 3
LOGIC
&
DA
Overload
Open Load
GND-det.
IPD
IPD
drift-det.
VS VCC VDD
Q1
D4
Q4
Q2
D3
Q3
GND
TEST
ST3
IN3
ST2
IN2
ST4
IN4
ST1
IN1
CLK
EN
Internal Supply
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L9352
PIN DESCRIPTION
N° Pin Function
1 GND Logic Ground
2, 3 PGND 3 Power Ground Channel 3
4, 5 Q 3 Power Output Channel 3
6, 7 D 3 Free-Wheeling Diode Channel 3
8, 9 Q 1 Power Output Channel 1
10, 11 Q 2 Power Output Channel 2
12, 13 D 4 Free-Wheeling Diode Channel 4
14, 15 Q 4 Power Output Channel 4
16, 17 PGND 4 Power Ground Channel 4
18 NC Not Connected
19 VCC 5V Supply
20 VDD 5V Supply
21 ST 4 Status Output Channel 4
22 IN 2 Control Input Channel 2
23 IN 4 Control Input Channel 4
24 ST 2 Status Output Channel 2
25 EN Enable Input for all four Channels
26 TEST Enable Input for Drift detection
27, 28 PGND 2 Power Ground Channel 2
29 VS Supply Voltage
30, 31 PGND 1 Power Ground Channel 1
32 ST 1 Status Output Channel 1
33 IN 3 Control Input Channel 3
34 IN 1 Control Input Channel 1
35 ST 3 Status Output Channel 3
36 CLK Clock Input
L9352
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ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are the limiting values for this device. Damage may occur if this device is subjected to conditions which are beyond these values.
THERMAL DATA
Symbol Parameter Test Conditions Min Typ Max Unit
E
Q
Switch off energy for inductive loads 50 mJ
Voltages
V
S
Supply voltage -0.3 40 V
V
CC
, V
DD
Supply voltage -0.3 6 V
V
Q
Output voltage static 40 V
V
Q
Output voltage during clamping t < 1ms 60 V
V
IN
, V
EN
Input voltage IN1 to IN4, EN II < |10|mA -1.5 6 V
V
CLK
Input Voltage CLK -1.5 6 V
V
ST
Output voltage status -0.3 6 V
V
D
Recirculation circuits D3, D4 40 V
V
DRmax
max. reverse breakdown voltage of free
wheeling diodes D3, D4
55 V
Currents
I
Q1/2
Output current for Q1 and Q2 >5
internal
limited
A
I
Q3/4
Output current for Q3 and Q4 >3
internal
limited
A
I
Q1/2
,
I
PGND1/2
Output current at reversal supply for Q1
and Q2
-4 A
I
Q3/4
,
I
PGND3/4
Output current at reversal supply for
Q3 and Q4
-2 A
I
ST
Output current status pin -5 5 mA
ESD Protection
ESD Elec trost atical Disch argin g
GND, PGND, Qx, Dx, CLK, ST, IN,
TEST, EN
MIL883C ±2kV
VS,
VCC,VDD
Supply pins vs. GND and PGND ±1 kV
ESD Output Pins (Qx, Dx) vs. Common GND
(PGND1-4 + GND)
±4kV
Symbol Parameter Test Conditions Min Typ Max Unit
T
j
Junction temperature T
j
-40 150 °C
T
jc
Junction temperature during clamping
(life time)
Σ
t = 30min
Σ
t = 15min
175
190
°C
T
stg
Storage temperature T
stg
-55 150 °C
T
th
Overtemperature shutdown threshold
(1)
(1) This parameter will not be tested but assured by design
175 200 °C
T
hy
Overtemperature shutdown hysteresis
(1)
10 °C
R
thJC
Thermal resistance junction to case R
thJC
2 K/W
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L9352
OPERATING RANGE
.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
S
Supply voltage 4.8 18 V
V
CC
, V
DD
Supply voltage 4.5 5.5 V
dV
S
/dt Supply voltage transient time -1 1
V/
µ
s
V
Q
Output voltage static -0.3 40 V
V
Q
Output voltage induced by inductive switching Voltage will be
limited by internal
Z-diode clamping
60 V
V
ST
Output voltage status -0.3 6 V
I
ST
Output current status -1 1 mA
T
j
Junction temperature -40 150 °C
T
jc
Junction temperature during clamping
Σ
= 30min
Σ
= 15min
175
190
°C
ELECTRICAL CHARACTERISTCS
:
(Vs = 4.8 to 18V; T
j
= -40 to 150°C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Power Supply
I
SON
Supply current
V
S
≤ 18V
(outputs ON)
5mA
I
SOFF
Quiescent current
V
S
≤ 18V
(outputs OFF)
5mA
I
cc
Supply current VCC (analog supply) VCC =5V 5 mA
I
dd
Supply current VDD (digital supply) VDD =5V f
CLK
=0Hz 5 uA
I
dd
Supply current VDD (digital supply) VDD =5V f
CLK
=250kHz 5 mA
General Diagnostic Functions
V
QU
Open load voltage
V
S
≥ 6.5V
(outputs OFF)
0.3 0.33 0.36 x V
Q
V
thGND
Signal-GND-loss threshold VCC= 5V 0.1 1 V
V
thPGL
Power-GND-loss thresh old VCC= 5V 1.5 2.5 3.5 V
f
CLK,min
Clock frequency error 10 100 kHz
DC
CLKe_l
ow
Clock duty cycle error detection low f
CLK
= 250 kHz 33,3 45 %
DC
CLKe_
high
Clock duty cycle error detection high f
CLK
= 250 kHz 55 66,6 %
VS
loss
Supply detection VCC = VDD = 5V 2 4.5 V
Additional Diagnostic Functions channel 1 and channel 2 (non regulated channels)
I
QU1,2
Open-load current channel 1, 2
V
S
≥ 6.5V
50 300 mA
I
QO1,2
Over-load current channel 1, 2
V
S
≥ 6.5V
57.59 A
L9352
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Additional Diagnostic Functions channel 3 and channel 4 (regulated channels)
DC
OUT
Output duty cycle range filtered with 10ms 10 90 %
I
QO3,4
Overload current
channel 3,4
V
S
≥ 6.5V
2.5 5 8 A
V
rerr
Recirculation error shutdown
threshold (open D3/D4)
Iout > 50mA 45 50 60 V
PWM
dOU
T
Output PWM ratio during drift
comparison
V
IN3
= V
IN4
= PWM
IN
V
TEST
= H
-14.3 +14.3 %
Digital Inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90%
V
IL
Input low voltage -0.3 1 V
V
IH
Input high voltage 2 6 V
V
IHy
Input voltage hysteresis
(1)
20 500 mV
I
I
Input pull down current
V
IN
= 5V, VS ≥ 6.5V
82040
µ
A
Digital Outputs (ST1 to ST4)
V
STL
Status output voltage in low state
(2))
IST ≤ 40µA
0 0.4 V
V
STH
Status output voltage in high state
(2)
IST ≥ -40µA
2.5 3.45 V
I
ST
≥ -120µA
23.45V
R
DIAGLROUT
+ R
DSON
in low state 0.3 0.64 1.5
k
Ω
R
DIAGHROUT
+ R
DSON
in high state 1.5 3.2 7.0
k
Ω
Power Outputs (Q1 to Q4)
R
DSON
Static drain-source ON-resistance
IQ = 1A; VS ≥ 9.5V
0.2 0.4
Ω
V
F_250mA
Forward voltage of free wheeling path
D3, D4 @250mA
I
D3/4
= -250mA 0.5 1.5 V
V
F_2.25A
Forward voltage of free wheeling path
D3, D4 @2.25A
I
D3/4
= -2.25A 2.0 4.5 V
R
sens
Sense resistor = (V
F_2.25A-VF_250mA
)/
2A
1
Ω
V
Z
Z-diode clamping voltage
I
Q
≥ 100mA
45 60 V
I
PD
Output pull down current VEN = H, VIN = L 10 150
µ
A
I
Qlk
Output leakage current VEN = L; VQ = 20V 5
µ
A
Timing
t
ON
Output ON delay time
I
Q
= 1A
0520
µ
s
t
OFF
Output OFF delay time channel
I
Q
= 1A
01030
µ
s
t
OFFREG
Output OFF delay time regulator
(3)
528
µ
s
t
r
Output rise time
IQ = 1A
0.5 1.5 8
µ
s
ELECTRICAL CHARACTERISTCS
:
(continued)
(Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
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L9352
t
f
Output fall time
I
Q
= 1A
0.5 1.5 8
µ
s
t
sf
Short error detection filter time
f
CLK
= 250kHz DC = 50%
(3)
48
µ
s
t
lf
Long error detection filter time f
CLK
= 250kHz DC = 50%
(3)
16 32
µ
s
t
SCP
Short circuit switch-OFF delay time
(3)
430
µ
s
t
D
Status delay time
(3)
896 1024 us
t
RE
Regulation error status delay time
(3)
(reg. channels only)
10 ms
t
Dreg
Output off status delay time
(3)
(reg. channels only
528
µ
s
Reg. Current Accuracy (reg. channels only)
I
Q3/Q4
Minimum current DC = 10% 200 250 300 mA
I
Q3/Q4
Maximum current DC = 90% 2 2.25 2.5 A
I
REG
Max. regulation deviation @
DC 10% - 90%
250mA < I
Q3/Q4
< 400mA
400mA ≤ I
Q3/Q4
≤ 800mA
800mA < I
Q3/Q4
< 2.25A
±10
±6
±10
%
%
%
∆
I
Q3/Q4
Min. quant. step 5 mA
Frequencies
CLK frequency crystal-controlled 250 kHz
Input PWM frequency (reg. channels only) 2 kHz
(1) This parameter will not be tested but assured by design.
(2) Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW"
(3) Digi t al filtered wit h external cloc k, only functional test
ELECTRICAL CHARACTERISTCS
:
(continued)
(Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
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