SGS Thomson Microelectronics L6611N, L6611D, L6611DTR Datasheet

DIGITALLY PROGRAMMABLE SECONDARY

■

OV/UV DETECTION FOR 3.3V, +5V, ±12V
RAILS AND 5V (OR 3.3V) AUX. VOLTAGE

■

AC MAINS UV (BROWNOUT) DETECTION
WITH HYSTERESIS

■

ON-LINE DIGITAL TRIMMING FOR 5V/12V,

3.3V, 5V (OR 3.3V) AUX. FEEDBACK
REFERENCES AND AC MAINS UV.

■

DIGITALLY SEL EC T ABL E OPT IO N S

■

ERROR AMPLIFIERS FOR 5V/12V RAILS
(MAIN SUPPLY), 3V3 POST-REGULAT OR
(MAG_AMP OR LINEAR) AND AUXILIARY
SUPPLY.

■

MAIN SUPPLY ON/OFF CONTROL AND
POWER GOOD SIGNAL

■

50mA CROWBAR DRIVE FOR AUXIL IARY
OUTPUT OVP .

■

OPEN GROUND PROTEC TI ON

■

8ms DIGITAL SOFT START

■

64 ms UV/OC BLANKING AT START-UP

L6611

HOUSEKEEPING CONTROLLER

BCD TECHNOLOGY

DIP20 SO20

ORDERING NUMBERS:

L6611N L6611D

L6611DTR(T & Reel)

APPLICATION S

■

SWITCHING POWER SUPPLIES FOR
DESKTOP PC'S, SERVERS AND WEB
SERVERS

■

SUPERVISOR FOR DISTRIBUTED POWER

TYPICAL APPLICATION CIRCUIT

+

WIDE RANGE

MAINS

-

April 2002

MAIN

CONTROL

AUXILIARY

CONTROL

Bout

VDD

Cout

MFault

Aout

L6611

Dmon

12V

5V

-12V
3V3

Gnd

+12V

+5V

COM

-12V

+3.3V

+5Vaux

1/28

2/28

L6611

Prog

Dmon

Cinv

Cout

Vdd

Gnd

Ainv

Aout

Bout

Binv

BLOCK DIAGRAM

Vdd

2.50V(B)

uv

ov

ov

OCP Bounce

1.25V (A)

Vdd

L

V

U

V

1.25V (B)

f

V

r

e

Reset

2.50V(A)

2.50V(B)

2.50V(C)

1.25V(A)

1.25V(B)

+5V +12V

2.50V(A)

Soft Start

Logic and Programmable Trimming

2.50V(B)

Programmi ng input

Debounce

75ms

10mA

+

+

_

_

2.50V(C)

Disable

OV

ov

uv

UV

+/-12V UV

ov

uvuvov

3V3 +5V UV

ov

uv

Dfault

Vdd

+12V

+12V

+5V

+5V

Vdd

Vreg

PS-ON / Clock

-

PW-OK / Data

-

50uA

Mfault

ACsns

-

-12V

2.50V(B)

+3V3

+3V3

L6611

DESCRIPTION

The L6611 is a control and housekeeping IC developed in BCD technology; it is intended for acting at the sec­ondary side of desktop PC's or server's switching power supplies, in presence of standard voltage rails (+3.3V,
+5V, ±12V) generated by a main conve rter and of a supply line gen erated by an auxi liar y c onverter. The typic al
application circuit is showed on the front page.

The Housekeeping's main function is to control and monitor the voltages generated by both the main and the
auxiliary converter: it senses those voltages, sends feedback signals to the primary controllers for regulation
and, upon detection of an undervoltage (UV), or overvoltage (OV) condition, reports such fault and takes proper
action to protect the system.

However, the peculiar feature of this IC is its digital programming capability that enables an accurate trimming
of the output voltage rails during product ion test via soft ware, without any use of ex ternal dis crete trimming com­ponents or need for manual intervention on the PSU. It is also possible to program some of the monitoring func­tions and select how UV and OC conditions are handled in the main converter: whether latched-mode (the
information is latched and released only by forcing the restart of the IC) or bouncing-mode (an attempt is made
to automatically restart the converter after 1 second wait).

A key feature of this IC is its contribution to a very low external component count. Besides the extensive use of
onboard programmable switches, which prevents the need for external trimming components, the IC embeds
reference voltages, error amplifiers and most of the housekeeping circuitry normally required.

PIN CONNECTION

PIN DESCRIPTION

Pin # Name Description

MFAULT

1

(top view)

MFAULT

MFAULT

Binv

Binv

Bout

Bout
Aout

Aout

Ainv

Ainv

Cout

Cout

Cinv

Cinv

Dmon

Dmon

DFAULT

DFAULT

Vdd

Vdd

Main converter on/off control. This pin is a 10mA current sink used for driving an opto-isolator. It
is normall y low when PS-O N (#13) is p ulled low. If a fault is detected or PS-ON goes high, this
pin goes high too. To allow power up, the functions are digitally blanked out for a period (U VB
function) and MFAULT (#1) stays low. There is no delay for the OV protection function.

12V

12V

5V

5V
3V3

3V3

PROG

PROG
GND

GND

-12V

-

-12V

­VREF

VREF

PS-ON

-

PS-ON

-

PW-OK

PW-OK
ACsns

ACsns

2

3

Binv

Bout

Inverting input to the error am plifier for the 3V3 po st-regulator (either m ag-amp or line ar). The
non-inverting input is connected to an internal 1.25V reference that can be digitally trimmed.

Output of the 3V3 error amplifier. It typically drives either a PNP transistor that sets the mag-amp
core or the pass elem ent of a linear re gulator. Also node for error amplif ier compe nsation. T he
maximum positive level of this output is clam ped a t abou t 3.5V to improve response time. La rge
signal slew rate is limited to reduce noise sensitivity.

3/28

L6611

g

y

g

PIN DESCRIPTION

Pin # Name Description

4

5

6

7

8

9

10

11

Aout

Ainv

Cout

Cinv

Dmon

DFAULT

Vdd

ACsns

(continued)

Output of the error amplifier for the main converter. This pin typically drives an optocoupler and is
also used for compensation along with Ainv (pin #5).

Main loop error amplifier inverting input. The non-inverting input is connected to an internal 2.5V
reference that can be digitally trimm ed. A high impe dance inter nal divider from +12V and +5V
UV/OV sense pins (#19, #20 ) eliminates t he need for external d ivider in mos t applicatio ns. The
pin is used for error amplifier compensation.

Auxiliary loop optocoupler drive. Also node for error amp compensation. Large signal slew rate is
limited to reduce sensitivity to switching noise.

Inverting input for Auxiliar y error amplifier. The non-inver ting input is con nected to an inter nal

1.25V reference that can be digitally trimmed.
Dual or Auxiliary UV/OV monitor, Dmon is programmable to monitor 3V3 or 5V . To allow a correct

power up, the UV function on this pin is blanked out dur ing initial star t-u p. There is no delay for
the OV function.

Dual or Auxiliar y fault protection. When Dmon (#8) recognizes an over voltage, DFAULT a nd
MFAULT (#1) go high . DFAULT is capable of sourcing up to 50 mA. Possible applications are a
crowbar across the Auxiliary output or an opto-coupled fault signal to the primary side.

Positive input supply voltage. Vdd is normally sup plied from the Auxiliary power supply output
voltage. If Vdd-UVL detects a sustained under voltage, PW-OK (#12) will be pulled low and
sending MFAULT (#1) high will disable the main converter.

of bulk voltage for AC fail warning. The usual sourc e of this analog pin is one of the

Analo
secondar
current sink on this pin that is activated as the volta
(2.5V).

windings of the main trans former. Hysteresis is prov ided through a trimmable 50µA

e at the pin falls below the internal reference

12

13

14

15

16

17

PW-OK

/Data

PS-ON /

Clock

VREF

-12V

GND

PROG

Power good signal for the Main converter. When asserted high, this pin indicates that the
voltages monitored are above their UV limits. There will be typic ally 2 50m s de lay from th e M ain
outputs becom ing good an d PW-OK being ass er ted. This is nominally a n open drain s ignal. To
improve robustness, this output h as a l imited cu rrent sin k ca pabil ity. In programming mode, this
pin is used for data input; then the absolute maximum rating will be Vdd+0.5V.

Control pin to enable the Main converter. This pin has debouncing logic. A recognized high value
on this pin will cause PW-OK (#12) to g o immediately low a nd, after a delay of 2.5 ms, to shut
down the main PWM by allowing MFAULT (#1) to go high. Durin g norma l operation (or if not
used) this pin has to be connect ed to a voltage lower than 0.8V. In pr ogramming mode, this pin
will be used to clock serial data into the chip.

2.5V reference for external applications. This is a buffered pin. Shor ting this pin to ground or to
Vdd (#10) will not affect integrity of con trol or monitor references. An external capacitor (max.
100nF) is required whenever the pin is loaded (up to 5 mA), otherwise it can be left floating.

-12V UV/OV monitor. If connected to a voltage greater than 1.5V (e.g. VR EF, #14), the funct ion
will be disabled.

Ground pin. The conne ction integrity of this pin is cons tantly monitored and in case of either a
bond wire or a PCB trace going open, MFAULT (#1) and DFAULT (#9) will be forced high
switching off the supply.

The chip has 2 operating modes, depending on PROG input pin biasing:

normal mod

–

programming mod

–

(#12) and PS_ON (#13) pins are disconnected from their normal functionality and they become
inputs for DATA and CLOCK allowing the chip to be programmed. The programming mode al­lows selecting some options and adjusting some setpoints;

e: PROG should be floating or shorted to ground;

e: forcing PR OG high (+ 5V), the chi p enters pro gramming m ode. PW_ OK

4/28

L6611

PIN DESCRIPTION

Pin # Name Description

18

19

20

3V3

12V

5V

(continued)

3V3 UV/OV monitor. It uses a separate reference to the feedback reference.
Input pin for 5V feedback, 5V current sense and 5V UV/OV monitor. 5V UV/OV uses a reference

separate from t hat used for feedback. This pin conn ects the 5V par t of the Main error amplifier
feedback divider.

Input pin for 12V feedback, 12V current sense and 12V UV/OV monitor.12V UV/OV uses a
reference separate from that used for feedback. This pin connects the 12V part of the Main error
amplifier feedback divider.

FUNCTION DESCRIPTION

Name Description

OVP

UVP

UVB

Whenever one of the Main output voltage s is detected go ing above its own OVP threshold, this
function set MFAULT (#1) high latching the outputs off. The latch is released after cycling PS-ON
(#13) switch or by reducing Vdd (#10) below the UV threshold.

Whenever one of the Main output voltages is detected going und er its own UVP threshold, this
function sets M FAULT (#1) high; if latc h mode has been selected, this fu nction will be latch ed.
Otherwise an attempt wi ll be made to restar t the device after 1 se cond delay. If ACsns (#11) is
low due to a brownout condition, UVP is disabled.

Undervoltage blanking. When either converter is enabled, the relevant UV/OC monitoring circuits
must not intervene to allow all outputs to come within tolerance. 64 ms timing is provided; for the
auxiliar y converter the timin g star ts as the IC has a valid supply, for the main converter it star ts
as the ACsns pin detects a valid input voltage for the converter.

PW-OK delay

OFF delay

Debounce

AC-hysteresis

Vdd-OVP

Vdd-UVL

Dual-OVP

Dual-UVP

PW-OK delay. After power-up, when the all of the monito red voltages are above their own UV
threshold th e PW-OK pin (# 12) will b e kept low for addit ional 250 ms (typ.) to ma ke sure all the
outputs are settled.

Power-off delay. As soon as PS-ON (#13) pin is recognized high, indicating an imminent turn-off
condition, PW-OK (#12) p in will go low immediately . The conver ter will be turned off after a
delay of 2.5ms.

The PS-ON signa l inp ut has d ebou nce logic to prevent improper acti vation. All of the m onito red
inputs have digital filtering/debounce logic on board for high noise immunity.

AC sense hysteresis. Programmable hysteresis is provided on the ACsns input (#11) to avoid
undesired s hutdown caused by noise as the voltage a t the pin is near the threshold or by the
voltage ripple across the bulk capacitor.

Vdd is moni tored for overvoltage. If a n overvoltage is detected, MFAULT (#1) and DFAULT (#9)
are latched high.

To prevent false signals of any of IC’s output pins, an under voltage lock-out circuit monitors Vdd
and keeps all IC’s output at their default OFF level until Vdd reaches a sufficient minimum
voltage for ensuring int egrit y. When Vdd goes be low th e UV th resho ld, all la tches ar e re set and
volatile programming memory cleared.

Dmon (#8) is monitored to detect an overvoltage condition; in this case MFAULT (#1) and
DFAULT (#9) are latched high.

Dmon (#8) is monitored to detect an undervoltage condition; in this case MFAULT (#1) is latched
high and Cout (#6) is pulled low.

5/28

L6611

FUNCTION DESCRIPTION

(continued)

Name Description

The IC provides an on -board 8ms soft-star t, a qua si-monoton ic ramp from 0V to 2.5V for the A
error amplifie r reference voltage, in order to avoid high current peak s in the pr imar y circuit and

Soft-start

output voltage overshoots at star t -up. In fact, if this reference gets the nominal value as soon as
the power-up occurs, the A E/A will go out of regulation and tend to sink much more current, thus
forcing PWM to work with the maximum duty-cycle.

Bounce or

Latch-mode

This option allows setting either latch ed-mode or auto restart after 1 second delay in case of
undervoltage faults.

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

Vdd Supply voltage -0.5 to +7 V

Voltage on PROG, PS-ON/Clock, DFAULT, VREF, and error
amplifier pins

Voltage on MFAULT, PW-OK, Dmon and positive UV, OV, OC, AC
sense pins.

Voltage on and -12V UV/OV sense pin -16 to +5 V
Maximum current in ESD clamp diodes 10 mA

-0.5 to Vdd+0.5 V

-0.5 to +16 V

Operating Junction Temperature -25 to 150 °C

J

Storage Temperature -50 to 150 °C
Lead Temperature (solde ri ng, 10 seconds) 300 °C

L

T

T

STO

T

THERMAL DATA

Symbol Parameter DIP20 SO20 Unit

R

th j-amb

(*) mounted on board

Max. Thermal Resistance junction-to-ambient (*) 70 120 °C/W

6/28

L6611

ELECTRICAL CHARACTERISTCS

(unless otherwise specified: TJ = 0 to 105°C; VDD = 5V, V
V

= VDD, PS-ON = low)

Dmon

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY SECTION

= 3.3V, V5V = 5V, V

3V3

-12V

= -12V, ,

V

DD(ON)

V

DD(OFF)

Start-up threshold 4.2 4.3 4.6 V
Minimum operating voltage after

3.7 3.8 4.1 V

turn-on

V

DD(H)

V

DDOV

I

DD-ON

Hysteresis 0.25 0.5 0.75 V
Vdd overvoltage 6.1 6.3 6.8 V
Operating supply current No Fault 5 7 mA

FAULT THRESHOLDS
Vout = 3.3V

UV 3V3 undervoltage 2.80 2.90 3.00 V
OV 3V3 overvoltage 4.00 4.15 4.30 V

3V3 bias current 50 65 µ

Vout = 12V

UV 12V undervoltage 10.60 10.80 11.00 V
OV 12V overvoltage 13.50 14.00 14.50 V

12V bias current 100 130 µ

Vout = -12V

A

A

UV -12V undervoltage -9.00 -9.50 -10.0 V
OV -12V overvoltage -14.4 -15.0 -15.6 V
V

-12V disable voltage Voltage to disable comparator 1.3 1.5 1.7 V

D

-12V bias current -65 -50 µ

Vout = 3.3V Aux/Dual (Dmon option)

UV 3V3 undervoltage 2.80 2.90 3.00 V
OV 3V3 overvoltage 4.00 4.15 4.30 V

Vout = 5V Aux/Dual (Dmon option)

UV 5V undervoltage 4.25 4.40 4.55 V
OV 5V overvoltage 6.00 6.25 6.50 V

Bias current 50 65 µ

ACsense / Hysteresis

Bias current V

= 2.7V 5 10 µ

ACsns

A

A

A

7/28

L6611

ELECTRICAL CHARACTERISTCS

(unless otherwise specified: TJ = 0 to 105°C; VDD = 5V, V
V

= VDD, PS-ON = low)

Dmon

(continued)

= 3.3V, V5V = 5V, V

3V3

-12V

= -12V, ,

Symbol Parameter Test Condition Min. Typ. Max. Unit

UV AC undervoltage 2.375 2.50 2.625 V

Trim range -5 +5 %
Trim resolution 0.64 %

I

ACH

Hysteresis current 20 50 80 µ
Hysteresis trim range -20 +20 %

H

Hysteresis adjust step 5 %

S

FAULT OUTPUTS

V
V

MF

POKH

POKL

PW-OK high state No faults 3 V
PW-OK low state I
MFAULT high state leakage PS-ON = high 1 µ

I

L

MFAULT sink current PS-ON = low, V

ISNK

MFAULT OV debounce Minimum OV pulse before

= 15mA 0.4 V

SINK

= 4V 6 10 15 mA

MFAULT

468µ

MFAULT is latched.

A

A

s

DF

D

IOH

FVOH

MFAULT debounce
±12V UV

MFAULT debounce
+5V, 3V3, UV

DFAULT output high source
current

DFAULT output high voltage

Minimum UV pulse before
MFAULT is latched.

Minimum UV pulse before
MFAULT is latched.

Overvoltage condition

DFAULT

= 1.5V

= 0mA, T

amb

= 25oC,

V

I

DFAULT

468µ

250 450 650 µ

-25 -50 -95 mA

2.1 2.4 2.7 V

Overvoltage condition

V

DFAULT output low voltage I

OUT

= 1mA, no faults 0.3 0.5 0.7 V

DFAULT

DFAULT OV debounce Minimum OV pulse before

468µ

DFAULT is latched.

DFAULT UV debounce Minimum UV pulse before

250 450 650 µ

DFAULT is latched.

START-UP / SHUTDOWN FUNCTIONS

t5 DFAULT UV blanking delay Delay from V

(on) to DFAULT

DD

44 64 84 ms

UV active.

t1 MFAULT UV blanking delay Delay from AC

high to Main

SNS

44 64 84 ms

UV active

t2 PW-OK blanking delay Main’s UV good to PW-OK high 175 250 325 ms

s

s

s

s

(t

8/28

t4

DELAY

PS-ON delay time Delay from PS-ON input to

)

MFAULT

1.75 2.5 3.25 ms

L6611

ELECTRICAL CHARACTERISTCS

(unless otherwise specified: TJ = 0 to 105°C; VDD = 5V, V
V

= VDD, PS-ON = low)

Dmon

(continued)

= 3.3V, V5V = 5V, V

3V3

-12V

= -12V, ,

Symbol Parameter Test Condition Min. Typ. Max. Unit

V
V

PS-ON Input High Voltage

IH

PS-ON Input Low Voltage 0.8 V

IL

PS-ON Input high clamp I

= -200µA

I

IN

= 100 µA Vdd

PS-ON

2.0 V

+0.7

R

PS-ON

PS-ON Pull-up to V

DD

t3 PS-ON debounce PS-ON input minimum pulse

V

= 0V 25 50 100

PS-ON

50 75 100 ms

width for a valid logic change.

t

Error Amp. A Soft-Start period VFB quasi-monothonic ramp from

SS

8ms

0 to 2.5V

V

STEP

Soft Start Step Ramp 0V to 2.5V 39 mV

VOLTAGE REFERENCE (BUFFERED EXTERNAL PIN)

V

REF

I

SC

Output Voltage I
Short circuit current V

= 1 - 5 mA; C

REF

= 0 10 20 mA

REF

= 47nF 2.375 2.50 2.625 V

REF

MAIN CONVERTER FEEDBACK (ERROR AMPLIFIER A)

V

Ω

K

V

Input Voltage Tj = 25° C 2.375 2.50 2.625 V

FB

Trim Range About nominal -5 +5 %
Trim resolution 0.64 %

Z

Divider impedance from Ainv to GND. 5V and 12V

FB

35 50 65

connected to GND.

Temperature coefficient 26 Ω/°

W

A

Divider 5/12 weighting 5V contribution to 5/12 feedback 47 50 53 %

5

Voltage gain 2V<V

VOL

<4V 65 dB

OUT

GBW Unity gain bandwidth 3 MHz

PSRR Power supply rejection ratio 4.5V<V

I

OUTL

I

OUTH

V

OUTH

V

OUTL

Output sink current V
Output source current V
Output high level V
Output low level V

FB

FB

FB

FB

<6V 60 70 dB

DD

= 2.7V, V
= 2.3V, V
= 2.3V, I
= 2.7V, I

= 1.1V 2 5 8 mA

OUT

= 4V -1.0 -1.5 -2.0 mA

OUT

SOURCE

SINK

= 1 mA 4 4.5 V

= 2 mA 0.7 1.1 V

MAGAMP OR LINEAR POST-REGULATOR FEEDBACK (ERROR AMPLIFIER B)

V

Input Voltage Tj = 25° C 1.22 1.25 1.28 V

FB

Ω

k

C

Trim Range About nominal -5 +5 %

9/28

L6611

ELECTRICAL CHARACTERISTCS

(unless otherwise specified: TJ = 0 to 105°C; VDD = 5V, V
V

= VDD, PS-ON = low)

Dmon

(continued)

= 3.3V, V5V = 5V, V

3V3

-12V

= -12V, ,

Symbol Parameter Test Condition Min. Typ. Max. Unit

Trim resolution 0.64 %

I

BIAS

A

Input bias current -0.1 -1 µ
Voltage gain 2V<V

VOL

<4V 65 dB

OUT

GBW Unity gain bandwidth 3 MHz

PSRR Power supply rejection ratio 4.5V<V

I

OUTL

I

OUTH

V

OUTH

V

OUTL

Output sink current V
Output source current V
Output high level V
Output low level V

FB

FB

FB

FB

<6V 60 70 dB

DD

= 1.4V, V
= 1.1V, V
= 1.1V, I
= 1.4V, I

= 1.1V 2 5 8 mA

OUT

= 3V -1.0 -1.5 -2.0 mA

OUT

SOURCE

SINK

= 1 mA 3 3.6 4 V

= 2 mA 0.7 1.1 V

AUXILIARY CONVERTER FEEDBACK (ERROR AMPLIFIER C)

V

Input Voltage T

FB

= 25° C 1.22 1.25 1.28 V

amb

Trim Range About nominal -5 +5 %

A

Trim resolution 0.64 %

I

BIAS

A

Input bias current -0.1 -1 µ
Voltage gain 2V<V

VOL

<4V 65 dB

OUT

GBW Unity gain bandwidth 3 MHz

PSRR Power supply rejection ratio 4.5V<V

I

OUTL

I

OUTH

V

OUTH

V

OUTL

V

OUTL

Output sink current V
Output source current V
Output high level V
Output low level V

FB

FB

FB

FB

Output low level Dmon = 2.7V, I

<6V 60 70 dB

DD

= 1.4V, V
= 1.1V, V
= 1.1V, I
= 1.4V, I

= 1.1V 2 5 8 mA

OUT

= 4V -1.0 -1.5 -2.0 mA

OUT

SOURCE

SINK

= 1 mA 4 4.5 V

= 2 mA 0.7 1.1 V

= 5 mA 0.25 V

SINK

PROGRAMMING FUNCTIONS

V

PROGLO

V

PROGHI

R

PROG

V

CLOCKLO

Prog Input Low 1.5 V
Prog Input High 3.5 V
Prog Pull Down 100
Clock Input Low 0.8 V

A

Ω

K

V

CLOCKHI

10/28

Clock Input High 2 V

L6611

ELECTRICAL CHARACTERISTCS

(unless otherwise specified: TJ = 0 to 105°C; VDD = 5V, V
V

= VDD, PS-ON = low)

Dmon

(continued)

= 3.3V, V5V = 5V, V

3V3

-12V

= -12V, ,

Symbol Parameter Test Condition Min. Typ. Max. Unit

F

CLOCK

V

DA TALO

V

DAT AHI

I

FUSE

t

FUSE

Clock Frequency 0.8 MHz
Data Input Low 1.5 V
Data Input High 2 V
PROM Fuse Current 400 mA
PROM Fusing Time 3 ms

11/28

L6611

34567

-50

-250255075

100

125

150

T [OC]

overvoltage

undervoltage

V5V [V]

TYPICAL ELECTRICAL CHARACTERISTICS
Figure 1. Supply start-up, UV and OV

VDD [V]

6.5

Figure 4. Monitored inputs bias current

IB [µA]

80

over voltage

5.5

4.5

3.5

-50 -25 0 25 50 75 100 125 150

start-up

UV

T [OC]

Figure 2. IC Supply current vs. supply voltage

IDD[mA]

10

8

6

4

2

Dmon = V

Tj= 25 °C

DD

70

60

50

40

30

-50-250 255075100125150

5Voutput

12Voutput

3.3Voutput

T [OC]

Figure 5. 3.3V fault threshol ds

[V]

V

3.3V

5

overvoltage

4

3

undervoltage

0

0246810

VDD[V]

Figure 3. IC Sup pl y c urre nt

IDD [mA]

7

6

5

4

3

-50 -25 0 25 50 75 100 125 150

12/28

T [OC]

2

-50 -25 0 25 50 75 100 125 150

T [OC]

Figure 6. 5V fault thresholds

L6611

TYPICAL ELECTRICAL CHARACTERISTICS
Figure 7. 12V fault th resholds

[V]

V

+12V

15

14

overvoltage

13

12

11

10

-50 -25 0 25 50 75 100 125 150

undervoltage

T [OC]

Figure 8. 3.3 V/5 V D mon fault thresh ol ds

V

[V]

DMON

0

-3

+5V ov ervoltage

(continued)

Figure 10. -12V fault thresholds

-6

overvoltage

-9

-12

undervoltage

-15

-18

-50 -25 0 25 50 75 100 125 150

Figure 11. ACsense and external voltage
references

[V]

2.7

-6

+5V undervo ltage

-9

+3.3V overvoltage

-12

-15

-18

-50 -25 0 25 50 75 100 125 150

+3.3V undervoltage

T [OC]

Figure 9. -12V bias current

-20

-30

-40

-50

-50-25 0255075100125150

2.6

2.5

2.4

2.3

-50 -25 0 25 50 75 100 125 150

T [OC]

Figure 12. Error amplifier A, B and C reference

voltage

[V]

3

2.5

A

2

1.5

0.5

1

-50 -25 0 25 50 75 100 125 150

B - C

T [OC]

13/28

L6611

TYPICAL ELECTRICAL CHARACTERISTICS

(continued)

Figure 13. Error am pl ifie rs (A, B, C) Gai n and Ph ase

200

200

150

150

phase

gain

gain

phase

100

100

50

50

0

0

-50

-50

-100

-100

-150

-150

-200

-200
1e+00 1e+01 1e+02 1e+03 1e+04 1e+05 1e+06 1e+07 7e+07

1e+00 1e+01 1e+02 1e+03 1e+04 1e+05 1e+06 1e+07 7e+07

o

o

0

0

o

o

90

90

f

φ

m

m

o

180

14/28

APPLICATION INFORMATION INDEX

1

On board digital trimming and mode selection..................................................................................Page 16

2

Error amplifiers and reference voltages..................................................................................................... 18

Main section: error amplifier A and Soft -Start

L6611

E/A and reference voltage

3.3V section: error amplifier B

Auxiliary section: error amplifier C

3

Normal operation timing diagram...............................................................................................................20

4

Undervoltage, overvoltage and relevant timings........................................................................................21

5

AC sense (mains undervoltage warning)...................................................................................................22

6

Application example...................................................................................................................................23

7

Application ideas........................................................................................................................................25

15/28

L6611

APPLICATION INF ORMATION
1 O NBOARD DIGITAL TRIMMING AND MODE SELECTION

By forcing the PROG input pin high, the chip enters programming mode: the multifunction pins PW_OK and
PS_ON are then disconnected from their normal functions (output pins) and are connected to internal logic as
DATA and CLOCK inputs respectively, allowing chip programming even when the device is assembled on the
application board. Onboard chip programming allows:

– selecting some working options;
– r eferenc e voltage setpoin ts adjusting.
It is also possible to verify the expected results before programming the chip definitively, in first instance, data

can be loaded into a re-writeble volatile memory (a flip-flop array) where they are kept as long as the chip is
supplied and can be changed as many times as one desires. A further operation is necessary to confirm the
loaded data and permanently store them into a PROM (a poly-fuse array) inside the IC.

Several steps compose the trimming/programming process:

1. PROG pin is forced high;

2. a clock signal is sent to the PS-ON/clock pin;

3. a byte with the following structure:

MSB LSB

D3 D2 D1 D0 A3 A2 A1 A0

Data Address

is serially sent to the P W-OK/DATA pin and loaded into the IC's volatil e memor y bit by bit on the falling edges
of the clock signal (see Fig. 14); "Address" is the identification code of the parameter that has to be trimmed
and "Data" contains the tuning bits;

4. PROG pin is forced low (warning: Vdd must never fall below V
tents of the volatile memory will be lost) and the result of the previous step is checked;

5. after any iterations of the steps 1-4 that might be necessary to achieve the desired value, force PROG pin
high and send the following burn code

MSB LSB

00001111

to permanently store the data in the PROM memory.

Table 1 shows the list of the 6 programmable classes of functions, each one identified by a different code
A0..A3, and the corresponding trimmable parameter(s); in table 2 it is possible to find the trim coding for the E/
A reference setpoints and in table 3 all the selections mode option coding are showed. The timing diagram of
fig. 14 shows the details of data acquisition.

during this process otherwise the con-

ddUVL0

Table 1. Programmable functions

Address Parameter(s) Default value Tuning bits

D2D1D

3

D2D1D

3

D2D1D

3

D2D1D

3

D

2
3
3

2

16/28

0001
0010
0011
0100

0101

0110

Error amplifier A threshold 2.50V D
Error amplifier B threshold 1.25V D
Error amplifier C threshold 1.25V D
AC sense threshold 2.50V D
AC sense hysteresis
Latch/Bounce mode selection Latch mode D
Enable/Disable 12V UV/OV function Enabled D
Enable/Disable 5V UV/OV function Enabled D
5V/3V3 Dmon selection 5V selection D

50µA

D1D

1

don’t care

O
O
O
O
O

Table 2. Trim Coding

Parameter

E/A A threshold

2.5V typ.

Address 0001 0010 0011 0010 0101

Tuning Bits

D

3 D2 D1 D0

0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0

D3 D2 D1 D0

∆

V [mV]
+112 +56 +56 +112

+96 +48 +48 +96
+80 +40 +40 +80
+64 +32 +32 +64
+48 +24 +24 +48 +7.5
+32 +16 +16 +32 +5.0
+16 +8 +8 +16 +2.5

00000

-16 -8 -8 -16 -2.5

-32 -16 -16 -32 -5.0

-48 -24 -24 -48 -7.5

-64 -32 -32 -64 -10

-80 -40 -40 -80

-96 -48 -48 -96

-112 -56 -56 -112

-128 -64 -64 -128

E/A B threshold

1.25V typ.

D3 D2 D1 D0

∆

V [mV]

E/A C threshold

1.25V typ.

D3 D2 D1 D0

∆

V [mV]

ACsns threshold

2.5V typ.

D3 D2 D1 D0

∆

V [mV]

L6611

ACsns

Hysteresys

50µA typ.

D2 D1 D0

∆

I [µA]

Table 3. Mode coding

Parameter

Address

Bounce or Latch

Mode

A3 A2 A1 A0

0101

Bit Value

D3 D3 D2 D1

0 Latch Enabled Enabled 5V
1 Bounce Disabled Disabled 3.3V

Enable/Disable

12V UV/OV

Enable/Disable

Tuning Bit

Figure 14. Trimming/programming procedure: timing diagram

MSB

10 0 00 01 1

PROG

PS_ON/Clock

PW_OK/Data

5V UV/OV

A3 A2 A1 A0

0110

LSB

5V/ 3.3V Dmon

Selection

17/28

L6611

2 E RRO R AMPLIFIERS AND REFERENCE VOLTAGES

Three error amplifiers are implemented on the IC to achieve regulation of the output vol tages: a brief descri ption
follows for each section.

Main section: error amplifier A and Soft-Start.

–

The circuit is designed to directly cont rol the Main primary PWM through an optocoupler, provid ing
very good regulation and gal vanic isolation from t he primary side. Typi cal solutions requ ire a shunt
regulator, like the TL431, as a reference and feedback amplifier to sense the output voltage and gen­erate a corresponding error voltage; this voltage is then converted in a current transferred to the pri­mary side through the optocoupler.
The feedback E/A amplifier is integrated in the IC : its non-inv erting input is c onnected to an inter nal ly gen­erated voltage reference, whose default value is typically 2.5V. It can however be trimmed to obtain a better
precision (see "On board trimming and mode operating" section). Then, no TL431 is needed.
The E/A inverting input (Ainv, pin#5) and the E/A output (Aout, pin#4) are externally available and the
frequency compensa tion netwo rk (Zc) will be c onnect ed betwe en them (see fig. 15).
The high impedance (in the hundred kΩ) internal divider from 12 V and 5V UV /OV sense pins elimi­nates the need for an external one in most applications, allowing a further reduction in the number of
external component.
Under closed loop condition, the two upper branches, connected to 12V and 5V pins, supply equally
the current flowing through R3= 80.6K (equal to 2.5V/R3).
In order to avoid high current peaks in the primary circuit and output voltage overshoots at start-up,
the IC provides an o n-board 8 ms sof t-start, a quasi-m onot onic ramp f rom 0V to 2. 5V for t he A error
amplifier reference voltage,. In fact, if this reference gets the nominal value as soon as the power-up
occurs, the A E/A will go out of regulation and tend to sink much m ore c urrent, thus forcing PW M to
work with the maxi mum duty-cycle.

E/A and references voltage

–

Being the inverting input of E/ A externally avail able, it is possible t o change the "wei ght" of the two
contributions or even eliminate one of them by connecting external resistors of much lower value (R
R

and/or RH2 in fig. 15) that bypass the internal ones appropriately.

H1

For example using R

=2.4K, RH1=3.9K and RH2=24K, then the ratio bet ween +5V and +12V output

L

weight will be equal to 6:4.
By simply making R

= RL (for example 2.4K) with no RH2, only the +5V output is kept under feed-

H1

back because the contribution of +12V branch (through the internal 600K resistor) will be negligible.
The pin #24 (12V) has to be connected to +12V output to guarantee the OV/UV monitoring.

L

,

Figure 15. Main feedback section

V

V

DD

to MAIN

to MAIN

control

control

3.3V section, error amplifier B.

–

DD

R

R

B

B

Aout

Aout

L6611

L6611

+12V output

+12V output

+5V output

+5V output

_

_

+

+

+2.5V

+2.5V

Zc

Zc

5V

5V

8ms SS

8ms SS

12V

12V

600K168K

600K168K

80.6K

80.6K

GND

GND

R

R

Ainv

Ainv

optional, to change

optional, to change
feedback we ight

feedback we ight

R

R

H1

H1

H2

H2

R

R

L

L

It is the error amplifier used to set the magamp core through an external circuitry (see a t ypi cal sche­matic in figure 16).
The non-inverting input of the error amplifier is connected t o a trimm able 1.25V internal voltage ref­erence (see "On board tr imming and m ode operat ing" paragraph). The E/A inverting input is exter­nally available (Binv, pin#2) and is connected to the output divider (R

18/28

and RL); the output pin (Bout,

H

pin#3) drives the external circuitry that biases the magamp core. Between these pins it is connected
the compensation network (Z

). The maximum positive output voltage is clamped at abo ut 3.5V to

C

improve response time.
The feedback con trol circuit determi nes t he m agam p "of f " time, c onvert ing the voltage at the ou tput
of error amplifier into a current I
value, V(B
age across R
PWM waveform across D

) decreases; this causes a higher voltage across RC which, in turn, implies a larger volt-

out

and a larger reset current IR (VBE of Q1 is supposed constant). A larger IR causes the

E

2

, which resets the magamp. If the output voltage exceeds its preset

R

to get narrower. This pulls the output voltage back to the desired level and
achieves regulation.
It is possible to use this section to drive a pass transistor to obtain 3.3V with a linear regulator; in the
"Application idea" section an example is showed to implement this solution.

Figure 16. Magamp control feedback section

+3.3V

+3.3V

magamp

magamp

D

D

2

2

D

D

1

1

R

R

I

I

E

E

R

R

Q

Q

L

L

V

V

D2

D2

R

R

C

C

1

1

R

R

S

S

C

C

Bout

Bout

L6611

L6611

Zc

Zc

_

_
+

+

+1.25V

+1.25V

Binv

Binv

R

R

H

H

R

R

L

L

L6611

Auxiliary section, error amplifier C.

–

This section (fig. 17) provides the feedbac k signal for the auxiliar y converte r following th e same oper­ating principles as the Main section. The auxiliary output voltage (Vaux) is often defined as "Standby
voltage" because the converter remains alive during standby condition (the Main converter is stopped)
to supply the chip and all the ancillary circuits. Typical values for its output voltage are 5V or 3.3V.
The inverting input (Cinv, pin#7) is connected to the output voltage through an external resistor divider
whereas the non-inverting one is connect ed to a 1.25V trimmabl e internal voltage reference (see "On
board trimming and mode operating" paragraph).
The compensation network Zc(aux) is placed between E/A inverting input and output pins.
When Dmon recognizes an un derv oltage condition on the auxiliary output, an internal n-cha nnel M OS
(in open drain configuration) grounds E/A output pin; the high current flowing through th e optocoupler
is then transferred to the primary side causing a duty cycle as short as possible; this prevents a high
energy transfer from p rimary to secondary under short circuit conditions, thus reducing the thermal
stress on the power components.

Figure 17. Auxiliary feedback section

V

V

AUX

AUX

to AUX

to AUX
control

control

R

R

B

B

Zc(aux)

Zc(aux)

DMON

DMON

Cout

Cout

OCP bounce

OCP bounce

GND

GND

R

R

H

H

R

R

L

L

Cinv

+1.25V

+1.25V

Cinv

L6611

L6611

_

_
+

+

19/28

L6611

3 NORMAL OPERATION TIMING DIAGRAM (FIG. 18)

The time intervals t1-t5 are listed below

t1:

–

UV/OC blanking of MFAULT. While Main outputs are ramping up, the UV comparators are blanked

for this interval to prevent a false turn-off. No such blanking is applied to OV faults.

t2:

–

PW-OK delay. This period starts when all monitored outputs and AC sense are above their respec-

tive UV levels and finishes at PW-OK going high.

t3:

–

PS-ON debounce period. The voltage on PS-ON must be continuously present in a high or low state

for a minimum period for that state to be recognized.

t4:

–

Tdelay. The time from PS-ON being recogn ized as going high to M FAULT going high . This is to

provide a power down warning. When PS-ON requests power off, PW-OK goes low immediately.

t5:

–

UV blanking of DF AUL T. During ini tial pow er up a perio d of UV bl anking is applied to DFAULT as

soon as Vdd to the chip is in the correct range. No such blanking is applied to OV faults.

Figure 18. Normal Operation Timing Diagram (ON/OFF with PS-ON or the AC power switch ).

On

AC
Vdd

Off

Vdd(on)

Vdd(on)

Vdd-ok

t5

UVBdfault

ACsns

PS-ON

Mfault
Main

OPs
POK

UVBmfault

ACsns_high ACsns_low

Off

On

t3

t2 t4

t1

t3

t2

t1

20/28

L6611

4 UNDERVOLTAGE, OVERVOLTAGE, DETECTION AND RELEVANT TIMINGS

The IC provides on-board undervoltage and overvoltage protection for 3V3, ±5V, ± 12V Main input pins and
Dmon auxiliary input pin. Overcurrent protection is available for 12V and 5V or 3.3V, digitally selectable. The
internal fault logic is illustrated in figure 19.

Figure 19. Simplified Fault logic

Debounce 6µs

Reset

Reset

Debounce 6µs

In Out

In Out

Vdd

Vdd

UVB 64ms

UVB 64ms

In Out

In Out

Vdd

Vdd

In

In

SQ

SQ

Latch

Latch

R

R

Clock Reset

Clock Reset

Debounce 6µs

Debounce 6µs

In Out

In Out

UVB 64ms

UVB 64ms

In Out

In Out

Clock Reset

Clock Reset

Dela y 1 s

Dela y 1 s

Clock

Clock

ResetClock

ResetClock

Reset

Reset

Reset

Reset

Out

Out

ResetClock

ResetClock

Reset

Reset

Reset

Reset

Reset

Reset

D_UV B

D_UV B

Delay 2.5ms

Delay 2.5ms

In

In

Clock

Clock

Mfault

Vdd

Vdd

Mfault

Vdd

Vdd

Dfault

Dfault

Cout

Cout

PW-OK

PW-OK

SQ

SQ

Latch

Latch

R

R

SQ

SQ

Latch

Latch

Reset

Reset

R

R

SQ

SQ

Latch

Latch

Reset

Reset

R

R

Out

Out

Reset

Reset

Reset

Reset

Vdd

Vdd

Delay 250ms

Delay 250ms

Out

Out

ClockInReset

ClockInReset

Main_OV

Main_OV
+/-12V_Main_UV

+/-12V_Main_UV

+3V3 +5V_Main_UV

+3V3 +5V_Main_UV

ACsense

ACsense

Dmon_OV

Dmon_OV

Dmon_UV

Dmon_UV

Vdd_OV

Vdd_OV
Vdd_UVL

Vdd_UVL

Restart Mode

Restart Mode

PS-ON

PS-ON

Vdd

Vdd

Vref

Vref

+

+

Debounce 6µs

Debounce 6µs

In Out

In Out

Debounce 500µs

Debounce 500µs

In Out

In Out

Reset

Reset

Debounce 75ms

Debounce 75ms

ClockInReset

ClockInReset

ResetClock

ResetClock

Reset

Reset

Debounce 500µs

Debounce 500µs

In Out

In Out

ResetClock

ResetClock

Reset

Reset

ON

ON

Out

Out

ResetClock

ResetClock

Main inputs overvoltage:

–

whenever one of main outputs (3.3V, +5V, ±12V) is detected as going over­voltage, MFAULT is l atched hig h (which stops the Main PWM ) and PW-OK goes lo w. Cycling the PS­ON switch or reducing Vdd below its undervoltage threshold releases the latch. A delay of 6µs is i mple­mented before MFAULT latching.
The OV protection for the 12V and 5V outputs can be disabled (see "On board trimming and mode op­erating" section).

Main inp uts un dervol tage:

–

when an un dervoltage on main outputs is d etected, MFAULT i s latched
high (the Main PWM stops) and PW-OK goes low. The latches are released, by default, cycling the PS­ON switch or reduc ing Vdd bel ow its un derv oltage thres hol d (latching m ode); optiona lly, an attempt is
made to restart the supply after of 1 second (bounce mode). The choice depends on the selected mode
(see "On board trimming and mode operating" section).
Debounce logic is implemented for 3.3V and 5V so that an undervoltage condition on these signals has
to last 450µs to be recognized as valid while 6µs debounce logic is implemented for 12V and -12V input
signal. When all main undervoltages are over and ACsns is OK (see the relevant section), PW_OK goes
high after a delay of 250ms.

Dmon input overvoltage:

–

whenever the Dmon input pin is detected as going overvoltage, both
MFAULT and DFAULT are latched high. The latch is released by reducing Vdd below its undervoltage
threshold. Debounce logic is implemented so that MFAULT and DFAULT signals are latched only if the
overvoltage condition lasts more than 6µs.
To protect the load against overvoltage, typical solutions make use of a power crowbar (SCR) driven by

21/28

L6611

DFAULT; in the "Application ideas" section, another simple circuit is showed to guarantee the same pro­tection without the SCR.

Dmon input undervoltage:

–

pulled low (an internal OCP_BOUNCE signal is gen erated, see fig. 19) and PW_OK falls down. This
function is enabled 64m s after the UVLO signal falls down. Debounc e logic is implemented so that
MFAULT and OCP_BOUNCE signals are generated only if the undervoltage condition lasts more than
500µs.
The Dmon UV and OV protections can be set to work with thresholds set for 5V or 3.3V output voltage:
the choice depends on the IC programming.

Figure 20. Fault timing diagram

when an undervoltage on Dmon is detected, MFAULT is put high, Cout is

Output

Mfault

POK

Main output’s overvoltage

(*)

Dmon

Dfault current

Auxiliary output’s overvoltage

(*) Dmon is connected to the Auxiliary output Rail

Dmon

Cout

MfaultMfault

POKPOK

(*)

Output

Mfault

POK

Main output’s undervoltage

Auxiliary output’s undervoltage

5 AC S ENSE (MAINS UNDERVOLTAGE WARNING)

The device monitors the primary bulk voltage and warns the system when the power is about to be lost pulling
down the PW_OK output.

The ACsns pin is typically connected to one of the windings of the main transformer (see fig. 21). Through a
single-diode rectification filter, a voltage equal to V
pacitor on primary side and N is the transformer turn ratio) is present at point B. A resistor (R

B

= V

/N (where V

BULK

is the voltage across the bulk ca-

BULK

) could be useful

F

to clamp voltage spikes present.
The fault signal is generated by means of AC_GOOD, the output of an internal comparator; this comparator is

internally referred to a trimmable 2.5V reference and indicates an AC fault if the voltage applied at its externally
available (non-inverting) input is below the internal reference, as shown in fig. 21.

This comparator is provi ded with current hysteresis i nstead of a more usual volt age hysteresis: an internal 50µA
current generator is ON if the voltage is below 2.5V and is turned off when the voltage applied at the non-invert­ing input exceeds 2.5V.

This approach provides an additional degree of freedom: it is possible to set the ON threshold and the OFF

22/28

L6611

VB

OFF

()

R

2

R1R

2

+

--------------------

⋅

2.5

=

R

2

R

1

2.5

VB

OFF

()

2.5

–

------------------------------------ -

⋅

=

threshold separately by pr operly choosing the resistors of the external divider. The following relationships can
be established for the ON (VB

VB

()

ON

--------------------------------- -

which, solved for R1 and R2, yields:

) and OFF (VB

(ON)

–

2.5

R

1

2.5

------- -

R

2

+=

50µA

) thresholds of the input voltage:

(OFF)

VB

-------------------------------------------------=

R

1

–

()

ON

50µA

VB

()

OFF

Both the ACsns threshold and the hysteresis current can be trimmed (see "On board trimming and mode oper­ating" section).

Figure 21. ACsns circuit and timing diagram

R

R

F

L6611

L6611

AC_GOOD

AC_GOOD

I

I

HYS=50µA

HYS=50µA

+2.5V

+2.5V

_

_

+

+

GND

GND

ACsns

ACsns

B

B

F

VB

VB

VB(on)

VB(on)

AC_GOOD

R

R

R

R

C

C

1

1

2

2

1

1

AC_GOOD

V

V

ACsns

ACsns

PW_OK

PW_OK

∆

∆

∆

∆

=50µA*R

=50µA*R

ON

ON

VB(off)

VB(off)

∆

∆

1

1

6 APPLICATION EXAMPLE

In applications like desktop PC's, server or web server, the system usually consists of two converters (Main and
Auxiliary) that can b e supplied directly from either the AC Mains or a PFC stage. The control a nd supervis ion at
the secondary side is usually entrusted to a housekeeping circuit.

The Auxiliary section supplies a stand-by voltage (5V typ.) through a flyback converter. The Main section, in
forward configuration, presents 4 standard outputs (3.3V, +5V, ±12V).

At the secondary side, the housekeeping circuitry gover ned by the L6611 checks the outputs and sends control
signals to the primary side through three optocouplers. It also generates power good information to the system
while managing all ti mings during power-up and power-down sequen ces. In fig. 22 a detail ed cir cui t for the sec­ondary side is presented; it is possible to note the very low number of external components required.

Simply connecting the power supply outputs to the L6611 r elevant pins ensures the pr otection agai nst over/un­dervoltage in the Main section.

A crowbar on the auxiliary output is switched on through DFAULT in case of overvoltage.
The L6611 is supplied by the Auxiliary output; the signals sent to the primary side are:
– a "digital" ON/OFF signal through an optocoupler that drives the relevant pin of primary Main controller

to switch the Main converter ON and OFF;

– two analog signals that provide voltage feedback for both the Auxiliary and the Main section, driving the

primary controller pins responsible for the duty cycle modulation.

23/28

L6611

Figure 22. Detailed Secondary Side

PRIMARY SIDE CONTROL & POWER MANAGEMENT

+12V

+5V

COM

-12V

+3.3V

L6611

M-FAULT
Binv
Bout

Aout
Ainv
Cout

Cinv
DMON
DFAULT

Vdd

12V

5V

3V3

PROG

GND

-12

VREF

PS-ON

PW-OK

ACsns

+5Vaux

24/28

L6611

7 APPLICATION IDEAS

In fig. 23 a circuit is suggested to obtain the regulated +3.3V output with a linear configuration instead of the
Magamp circuitry.

In this case the output of the E/A modulates the gate-source voltage of a power MOS in series with the power
stage.

In fig. 24 a simple and cheap latch circuit is showed to manage an OV fault on the Auxiliary output in the same
way of an OC (UV) fault, without having recourse to a (expensive) power crowbar. By tuning the value of R
it is possible to set the voltage value that triggers the latch circuit; C

defines the turn-on delay. A diode con-

DEL

nected between the collec tor of Q1 and C out pull s down the output of the auxiliary E/A: this has the same effect
of the OCP_bounce internal signal that guarantees the reduction of duty cycle.

Figure 23. Controlling a Line a r R egu lat o r with the Error Ampl ifi e r B

+5V

+5V

+3.3V

+3.3V

L

+12V

+12V

L

R

R

B

B

C

C

1

1

Bout

Bout

L6611

L6611

_

_

+

+

+1.25V

+1.25V

C

C

2

2

R

R

H

H

Z

Z

C

C

Binv

Binv

R

R

L

L

SET

Figure 24. Auxiliary OVP without Crowbar

DMON

DMON

Cout

Cout

L6611

L6611

D1

D1

BAT42

BAT42

Q1

Q1

BC548

BC548

5K6

5K6

C

C

DEL

DEL

100

100

Q2

Q2

BC558

BC558

V

V

R

R

SET

SET

5K6

5K6

AUX

AUX

25/28

L6611

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.254 0.010

B 1.39 1.65 0.055 0.065

b 0.45 0.018

b1 0.25 0.010

D 25.4 1.000

E 8.5 0.335

e 2.54 0.100

e3 22.86 0.900

F 7.1 0.280

I 3.93 0.155

L 3.3 0.130

Z 1.34 0.053

mm inch

OUTLINE AND

MECHANICAL DATA

DIP20

26/28

L6611

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2.65 0.093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

E 7.4 7.6 0.291 0.299

e 1.27 0.050

H 10 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.4 1.27 0.016 0.050

K 0˚ (min.)8˚ (max.)

mm inch

OUTLINE AND

MECHANICAL DATA

SO20

B

e

D

1120

110

L

h x 45˚

A

K

A1

C

H

E

SO20MEC

27/28

L6611

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