SGS Thomson Microelectronics L6387 Datasheet
®
HIGH-VOLTAGE HIGH AND LOW SIDE DRIVER
HIGH VOLTAGE RAIL UP TO 600 V
dV/dt IMMUNITY +- 50 V/nsec IN FULL TEM-
PERATURE RANGE
DRIVER CURRENT CAPABILITY :
400 mA SOURCE,
650 mA SINK
SWITCHING TIMES 50/30 nsec RISE/FALL
WITH 1nF LOAD
CMOS/TTL SCHMITT TRIGGER INPUTS
WITH HYSTERESIS AND PULL DOWN
INTERNAL BOOTSTRAP DIODE
OUTPUTS IN PHASE WITH INPUTS
DESCRIPTION
The L6387 is an high-voltage device, manufactured with the BCD"OFF-LINE " technology. I t has
a Driver structure that enables to drive independent referenced N Channel Power MOS or
L6387
SO8 Minidip
ORDERING NUMBERS:
L6387D L6387
IGBT. The Upper (Floating) Section is enabled to
work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices.
BLOCK DIAGRAM
V
3
CC
DETECTION
2
HIN
1
LIN
UV
BOOTSTRAP DRIVER
LOGIC
LEVEL
SHIFTER
R
S
LVG
DRIVER
V
CC
HVG
DRIVER
D00IN1135
Vboot
8
H.V.
HVG
7
OUT
6
LVG
5
GND
4
Cboot
TO LOAD
May 2001
1/9
L6387
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
Vout Output Voltage -3 to Vboot - 18 V
Vcc Supply Voltage - 0.3 to +18 V
Vboot Floating Supply Voltage - 1 to 618 V
Vhvg Upper Gate Output Voltage - 1 to Vboot V
Vlvg Lower Gate Output Voltage -0.3 to Vcc +0.3 V
Vi Logic Input Voltage -0.3 to Vcc +0.3 V
dVout/dt Allowed Output Slew Rate 50 V/ns
Ptot Total Power Dissipation (Tj = 85 °C) 750 mW
Tj Junction Temperature 150 °C
Ts Storage Temperature -50 to 150 °C
Note:
ESD immunity for pins 6, 7 and 8 is guaranteed up to 900V (Human Body Model)
PIN CONNECTION
LIN
HIN
Vcc
GND
1
2
3
4LVG
D97IN517
7
6
5
Vboot8
HVG
OUT
THERMAL DATA
Symbol Parameter SO8 Minidip Unit
R
th j-amb
Thermal Resistance Junction to Ambient 150 100 °C/W
PIN DESCRIPTION
N. Name Type Function
1 LIN I Lower Driver Logic Input
2 HIN I Upper Driver Logic Input
3 Vcc I Low Voltage Power Supply
4 GND Ground
5 LVG (*) O Low Side Driver Output
6 VOUT O Upper Driver Floating Reference
7 HVG (*) O High Side Driver Output
8 Vboot Bootstrap Supply Voltage
(*) The circuit guarantees 0.3V maxim um on the pin (@ I
and the source of the external MOSFET normally used to hold the pin low.
= 10mA). This allows to omit the "bleeder" resistor connected between the gate
sink
2/9
L6387
RECOMMENDED OPERATIN G CONDITIONS
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
Vout 6 Output Voltage Note 1 580 V
Vboot-
Vout
fsw Switching Frequency HVG,LVG load CL = 1 nF 400 kHz
Vcc 2 Supply Voltage 17 V
T
Note 1:
ELECTRICAL CHARACTERISTICS
AC Operation (Vcc = 15V; Tj = 25°C)
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
ton 1 vs 7 High/Low Side Driver Turn-On
toff 2 vs 5 High/Low Side Driver Turn-Off
tr 7,5 Rise Time CL = 1000pF 50 ns
tf 7,5 Fall Time CL = 1000pF 30 ns
DC OPERATION (Vcc = 15V; Tj = 25°C)
8 Floating Supply Voltage Note 1 17 V
j
If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V.
Junction Temperature -45 125 °C
Vout = 0V 110 ns
Propagation Delay
Vout = 600V 105 ns
Propagation Delay
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
Low Supply Voltage Section
Vcc 3 Supply Voltage 17 V
Vccth1 Vcc UV Turn On Threshold 5.5 6 6.5 V
Vccth2 Vcc UV Turn Off Threshold 5 5.5 6 V
Vcchys Vcc UV Hysteresis 0.5 V
Iqccu Undervoltage Quiescent Supply
Vcc ≤ 9V 150 220 µA
Current
Iqcc Quiescent Current Vcc = 15V 250 320 µA
R
dson
Bootstrap Driver on Resistance (*) Vcc ≥ 12.5V 125 Ω
Bootstrapped supply Voltage Section
VBS 8 Bootstrap Supply Voltage 17 V
IQBS VBS Quiescent Current HVG ON 200 µA
ILK High Voltage Leakage Current VS = VB = 600V 10 µA
High/Low Side Driver
Iso 5,7 Source Short Circuit Current VIN = Vih (tp < 10µs) 300 400 mA
Isi Sink Short Circuit Current VIN = Vil (tp < 10µs) 450 650 mA
Logic Inputs
Vil 2,3 Low Level Logic Threshold Voltage 1.5 V
Vih High Level Logic Threshold Voltage 3.6 V
Iih High Level Logic Input Current VIN = 15V 50 70 µA
Iil Low Level Logic Input Current VIN = 0V 1 µA
(*) R
is tested in the following way: R
DSON
where I1 is pin 8 current when V
CBOOT
= V
DSON
CBOOT1
(
V
CC
=
(
I
V
1
, I2 when V
− V
CBOOT1
CC,VCBOOT1
CBOOT
− (VCC − V
)
) −
(
I
V
2
CC,VCBOOT2
= V
CBOOT2
CBOOT2
.
)
)
3/9
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