SGS Thomson Microelectronics L6285 Datasheet

L6285
3 CHANNELS MULTIPOWERSYSTEM
ADVANCE DATA
CHANNEL-A AND CHANNEL-B FOR UNIPO­LAR STEPPER MOTORS – LOWSIDE: R – HIGH SIDE ; R
DSON
DSON
= 1.2
= 1.2
CHANNEL-CFOR DC MOTORS – LOWSIDE: R – HIGH SIDE: R
DSON
DSON
= 1.7
= 1.2
CHOPPING MODE DRIVING FOR C.L. CUR­RENT CONTROL ON CHA AND CHB AND O.L. VOLTAGECONTROL ONCHC.
INTERNALFOUR DRIVINGLATCHES 16 BIT INTERNAL SHIFTREGISTER DIRECTINTERFACE TO µP SERIALDRIVINGSEQUENCE LOADING CMOSCOMPATIBLEINPUTS PRE-ALARMOUTPUT SIGNAL THERMAL SHUTDOWN
DESCRIPTION
This Combo Motor Driver uses large scale inte­gration to incorporate several functions into the same chip.
1) Two unipolar steppermotor driver
2) A full bridgeDC motor driver
BLOCK DIAGRAM
MULTIPOWER BCD TECHNOLOGY
PLCC44 SDIP42
ORDERING NUMBERS:
L6285 L6285S
3) Serial microprocesor interface
The poweroutput stages areDMOS and the input can be interfaced to a CMOS Microprocessor logic.
The phase current in the unipolar stepper motor windings is controlled by two external sensing re­sistors in fixed frequency choppingmode.The os­cillator block provides clocks each other 180° out of phase to the two stepper motor driver in order to avoidsymultaneous currentpeaks.
For the DC motor driver is used a bridge; the RMS voltage to supply this motor is fixed by a
May 1994
This is advanced informationon a new product now in development or undergoing evaluation. Details are subject tochange without notice.
1/16
L6285
simple PWMopen loop. The 3 motorsare control­led by the micro through 4 latches of 4 bit each. The loading of these registers is in serial mode. The I.C. operates at 5V supply forthe logic and at
PINCONNECTION (Top view)
PWGND
OUT1A
S1,2A
OUT2A
CLAMPA
OUT3A
S3,4A OUT4A BOOT1 BOOT3
GND
7 8 9 10 11 12 13 14 15 16 17
COM3,4A
PWGND
SID
BOOT2
P
COM1,2A
V
PLCC44
STB
SCK
S1,2C
OUT2C
123564
2322211918 20 28272624 25
S
V
N.C.
OUT1C
COM1,2B
N.C.
A0TH
P
V
A1TH
PWGND
COM3,4B
40414244 43
39 38 37 36 35 34 33 32 31 30 29
V2
OSC RESET
PWGND OUT1B S1,2B OUT2B CLAMPB OUT3B S3,4B OUT4B VLOW COSC GND
D94IN067
24V supply for the power stages. The packages are SDIP42 and PLCC44 with 6 pins devoted to ground and to sink out the heat produced by powerdissipation.
OUT2C
COM1,2A
COM3,4A
PWGND
OUT1A
S1,2A
OUT2A
CLAMPA
OUT3A
S3,4A OUT4A BOOT1 BOOT3
BOOT2
1 2
V
3
P
4
N.C. COM3,4B
5 6 7 8 9 10
SDIP42
11 12 13 14 15 16
GND
17
N.C.
18 19
SID
20
SCK
21
STB
D94IN060A
42 41 40 39 38
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
S1,2C OUT1C COM1,2B V
P
PWGND37 OUT1B S1,2B OUT2B CLAMPB OUT3B S3,4B OUT4B V
LOW
C
OSC
GND V2 OSC RESET A1TH A0TH V
S
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V V V
I
LOW
I
HIGH
I
pLOW
I
pHIGH
V
bout
Power Supply Voltage 30 V
P
Logic SupplyVoltage 7 V
S
Logic Input Voltage -0.3 toVS+ 0.3 V
in
Low Side DMOS max DC Current 1 A High Side DMOS max DC Current 1 A Low Side DMOS max Peak Current (1µs On; 50µs OFF) 2 A High Side DMOS max Peak Current(1µs On; 50µsOFF) 2 A Max Output Voltage of Stepper Motor Driver(transient
60 V
rcirculation)
V
1;2 Max Voltage ON Vsense (CHA/CHB) -1 to2 V
sense
3 Max Voltage ON V
V
sense
Ι
fdDC
Ι
fdpk
Max DC Currentof Forward Diode(DMOS Source DrainDiode) 1 A Max Peak Current of ForwardDiode (DMOS Source Drain
(CHC) -1 to 2 V
sense
2A
Diode) (1µs On;50µs OFF)
P
tot
T
op
T
stg
Total Power Dissipation (Tpins = 90°C) With minimized dissipatingcopper area (T
amb
=70°C)
5
1.6 Operating Temperature Range 0 to 150 °C Storage Temperature Range -40 to 150 °C
THERMAL DATA (PLCC44)
Symbol Description SDIP42 PLCC44 Unit
R
th j-pins
R
th j-amb
Thermal Resistance Junction-pins Thermal Resistance Junction-ambient
Max. Max.
15 48
12 50
W W
°C/W °C/W
2/16
PINDESCRIPTION
SDIP42
o
N
42 1 S1,2C Full bridge common source output to separate between power GND
1,41 2,44 OUT 1C, OUT 2C Output of the channel C bridge.
2 3 COM 1,2A High side DMOS channel A for current chopping in the windings
3,39 4,42 V
4 5 COM 3,4A High side DMOS channel A for current chopping in the windings
6,37 6,7,39,40 GND PowerGround and heatsinkpins.
7,9,
11,14
8 9 S1,2A ChannelA sourcesof theDMOS OUT 1A, OUT 2A. A sensing resistor
10,33 11,35 CLAMP A, CLAMP B These pinshave to be connected to an external zener diodeto
12 13 S3,4A Channel Asources of the DMOSOUT 3A,OUT 4A. A sensingresistor
14 15 BOOT 1 A capacitor between this pin and V
15 16 BOOT 3 A capacitor between this pinand internal diodes allows the change
16,27 17,29 GND Logic Ground and Heatsink pins.
18 18 BOOT 2 Charge pump oscillator output. 19 19 SID Serial data input. 20 20 SCK Serial clock for serial data input. 21 21 STB Strobe to transfer the16 bit shift register contentsto the latch
5,17 22,24 NC Notconnected. 22,39 23 V 23,24 25,26 A0TH / A1TH Open collector outputs for thermal informations to the µP.
25 27 OSC/ RESET An RC network connected to this pin defines the oscillatorfrequency
26 28 V2 A voltage to this pindefines the outputduty cycle ofChannel C. 28 30 C
29 31 V
30,32,
34,36
31 33 S 3, 4B Same as S 3, 4A,but for channelB. 35 37 S 1, 2B Same as S 1, 2A,but for channelB. 38 41 COM 3, 4B Same as COM 3, 4A, but for channel B. 40 43 COM 1, 2B Same as COM 1, 2A, but for channel B.
PLCC44
o
N
8,10
12,14
32,34 36,38
Name Functions
and logic GND.
connected pins to OUT 1A, OUT 2A.
p
Power Supply Voltage.
connected topins OUT 3A, OUT 4A.
OUT 1A, OUT 2A
Low side DMOS outputs of channel A stepper motor driver.
OUT 3A, OUT 4A
has to be connected from this pin and ground, forcurrent controlof phase1,2 A.
clamp the output voltage spikes of channel A/B.
has to be connected from this pin and ground, forcurrent controlof phase3,4 A.
high side DMOS driver gate.
pump to transfer energy to the capacitor at the pin BOOT 1.
registers.
s
Logic Supply Voltage.
for stepper drivers. When OSC/RES is <1V, a reset signal is internally generated.
osc
A capacitor connected to thispin defines the chopping frequency of channel C.
low
This pin is low when thechopping low voltage (V2 low level) is selected; it is in highimpedance when the chopping high voltage(V2 high level) is selected. Only for CHC operation.
OUT4B, OUT3B
Low side DMOS outputs of channel B stepper motor driver.
OUT2B ,OUT1B
stores theovervoltage for each
p
L6285
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L6285
ELECTRICAL CHARACTERISTICS (Tj=25°C, Vs=5V, Vp= 24V unless othewise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
p
I
p
V
s
I
s
LOGICLEVEL
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
inL
V
inH
I
inL
I
inH
CHANNEL A AND CHANNEL B (UNIPOLARMOTORS)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
R
DSONL
R
DSONH
Power Supply Voltage 9 26.5 V Quiescent Power Supply
(note 1) 7 mA
Current Logic SupplyVoltage 4.5 5.5 V Quiescent Logic Supply
(note 1) 20 mA
Current
Input Low Voltage -0.3 1.35 V Input High Voltage 3.15 VS+0.3 V
Input Low Current Vin =V Input High Current Vin =V
inL inH
-10 µA 10 µA
Low Side DMOS ON Res. IDS = 0.7A 1.2 High Side DMOS ON Res. IDS = 0.7A 1.2
I
DSSL
Low Side DMOS Leakage
VDS= 60V;output OFF 2 mA
Current
I
DSSH
High Side DMOS Leakage
VP = 30V; VO= 0V -1.5 mA
Current
V
REF
Voltage reference to the Comparator
LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4
T
d
Turn OFF Delay on HIGH Side DMOS afterthe
(note 2)
100 220 340 465
125 250 375 500
150 280 410 535
1 µs
Sensing Current Reach the Threshold Value
f
max
Max Chopping Frequency 40 KHz
CHANNEL C (DC MOTORS)(see Fig.5)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
f
osc
DC Duty Cycle V2 = 1/2V
I
b2
V
low
R
DSONH
R
DSONL
I
LH
I
LL
V
fddc
f
max
V
boot
I
Lboot
Oscillator Frequency Cosc = 3.3nF; V1 = 2/3VS 17 22 28 KHz
S
72 75 81 % Comparator Input Bias V2 = 200mV -1 µA Open Drain Output I = 5mA 0.2 0.4 V High Side DMOS ON Res. IDS= 0.7A 1.2 Low Side DMOS ON Res. IDS= 0.7A 1.7 HSD MOS Leakage Current VP= 30V; VO=0V -1 mA LSD MOSLeakage Current VO = 30V; Vsense = 0V -1.5 mA Forward Diode DC Voltage
I
= 0.7A 1.4 2 V
fdcc
(DMOS Diode) Max Chopping Frequency 40 KHz Voltage on pin Boot1 Vp+7 V Leakage Currenton pin Boot1 V
bott=Vp
+12V; Vp= 26.5V 200 µA
mV mV mV mV
4/16
ELECTRICAL CHARACTERISTICS (continued) OSCILLATOR (see Fig.6)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
f
osc
Oscillator Frequency
COSC = 3.3nF; R
= 10K 27 41 46 KHz
OSC
Pin OSC/RESET
V
T
dsc
reset
Capacitor Discharge Time (protect deadtime)
C
= 3.3nF; R
OSC
(see Fig.1)
OSC
= 10K
0.8 1.4 2 s
Reset Threshold Voltage 1 V
INTERFACE TIMING
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t1 SCK Data Clock Cycle (see Fig. 2) 200 ns t2 SCK Data Set-upTime 30 ns t3 SCK Data Hold Time 20 ns t4 SCK-STB Interval Time 30 ns t5 STB Pulse Width 100 ns
Note 1: No output loaded; all register tolow condition;no resetapplied; VP= 26.5V;VS= 5.5V Note 2: The effectof theinternal filter (RC Network)is not considered.
L6285
µ
Figure 1: Discharge timet
or ProtectionTime
dsc
Figure 2: InterfaceTiming (Serialloading Mode)
Serial Input Data
b15
b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D15
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Register 4 Register 3 Register 2 Register 1
D0
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