SGS Thomson Microelectronics L6275 Datasheet



L6275

5V DISK DRIVE SPINDLE & VCM, POWER

& CONTROL“COMBO”

PRODUCT PREVIEW

GENERAL

5V (+/-10%)OPERATION.
REGISTERBASEDARCHITECTURE
MINIMUMEXTERNAL COMPONENTS
BICMOS+ VERTICAL DMOS(1.5mm)

VCM DRIVER

1.5ADRIVE CAPABILITY

0.9Ω TOTALBRIDGE IMPEDANCEAT 25°C
LINEARMODE
PHASESHIFT MODULATION(PWM MODE)
INSTANTANEOUS, (GLICH FREE) SWITCH

BETWEENTHE 2 MODES
CLASS ABOUTPUT DRIVERS
ZEROCROSSOVERDISTORSION
14 BIT DACDEFINEOUTPUT CURRENT
SELECTABLETRANSCONDUCTANCE
4 PROGRAMMABLEPARKING VOLTAGE
DYNAMICBRAKE

SPINDLEDRIVER

2.0ADRIVE CAPABILITY

0.8Ω TOTALBRIDGE IMPEDANCEAT 25°C
BEMF, INTERNAL OR EXTERNAL, PROC-

ESSING
SENSOR-LESSMOTOR COMMUTATION
PROGRAMMABLE COMMUTATION PHASE

DELAY
LINEARMODEAND CONSTANT TOFF PWM

OPERATIONMODE
INTERNAL FREQUENCY LOCKED LOOP

SPEEDCONTROL (FLL)
BEMFRECTIFICATIONDURING RETRACT
BUILT-INALIGNAMENT&GOSTART-UP
INDUCTIVE SENSINGSTART UP OPTION
RESYNCHRONIZATION
DYNAMIC& REVERSEBRAKE
CONTROLLABLEOUTPUTSLEWRATE

OTHER FUNCTIONS

5V MONITORING WITH EXTERNAL SET
TRIP POINTSAND HYSTERESIS

POWERUP/DOWN SEQUENCING
LOW VOLTAGESENSE

BICMOS TECHNOLOGY

TQFP44 (10x10mm)

ORDERING NUMBER: L6275

3.3V INPUTLOGIC COMPATIBILITY
THERMAL SHUTDOWN AND PRETHERMAL

WARNING
SYSTEMCLOCK WATCHDOG

DESCRIPTION

The L6275 integratesinto a single chip both spin­dle and VCM controllers as well as power stages.
The device isdesigned for 12V disk drive applica­tion requiring up to 2.0A of spindle and 1.5A of
VCM peak currents.

A serial port with up to 25 MHz capabilityprovides
easy interface to the microprocessor. A register
controlled Frequency Locked Loop (FLL) allows
flexibility in setting the spindle speed. Integrated
BEMF processing, digital masking, digital delay,
and sequencingminimize the number of external
componentsrequired.

Power On Reset (POR)circuitry is included. Upon
detection of a low voltage condition, POR is as­serted, the internal registers are reset, and spin­dle powercircuitry is tri-stated.The BEMF is recti­fied providing power for actuator retraction
followed bydynamicspindle braking.

The device is built in BICMOS technology allow­ing dense digital/analog circuitry to be combined
with a highpower DMOS outputstage.

April 1999

This is preliminaryinformation on a new product now in development. Details are subject to change without notice.

1/17

L6275

BLOCK DIAGRAM

SW1

SDATA

SCLK

SDEN

CLK_MON

TR_5V

CS

CP

CHARGE

PUMP

ISO

DRIVER

SERIAL

INTERFACE

SUPPLY

CLOCK FAULT

&

MONITORS

POR_DELAY

PORB

FLL_RES

FLL_FILTER

INDEX

FREQUENCY

LOCK LOOP

START-UP

REGISTERS

THERMAL

SUPPLY

VDD

SYS_CLK

GND

DGND

FCOM

SPINDLE SEQUENCER

RE_SYNC

DYNAMIC/
REVERSE

BRAKE

VCM CURRENT

CONTROL PSM/LIN

VCM

CALIBRATION

BIT

DAC

REFERENCE

GENERATOR

14

VCM DAC

SPN_COMP

PROCESSING

ZERO CROSS

VOLTAGE

V5/2

BRK_CAP

PWM/SLEW

BEMF

DETECTION

SPINDLE
CURRENT
CONTROL

PWM/LIN

PARKING

BEMF

RECTIFICATION

VCM_CAL

ERROR_IN

+

-

A

B

C

A+

A-

A=4

SENSE_OUT

ERROR_OUT

VDD

­+

D99IN1050

OUT_A
CTAP

OUT_B
RSENSE

OUT_C
ISENSE

VCM_A+
VDD

VCM_A­VCM_GND

SENSE_IN­SENSE_IN+

PIN CONNECTION

2/17

FCOM

CTAP

PWM/SLEW

OUT_C

I_SENSE

R_SENSE

OUT_B

GND

R_SENSE

OUT_A

INDEX

SPN_COMP

VDD

AGND

DAC

ERROR_IN

CLK_MON

ERROR_OUT

SENSE_OUT

44 43 42 41 3940 38 37 36 35 34

1
2
3
4
5
6
7
8
9

10

12 13 14 15 16

VDD

BRK_CAP

DGND

SDEN

SYS_CLK

171118 19 20 21 22

VDD

SCLK

SDATA

POR_DELAY

TR_5V

PORB

V5/2

VCM_CAL

FLL_FILTER

33
32
31
30
29
28
27
26
25
24
23

SW1
FLL_RES
VDD
VCM_A+
SENSE_IN­VCM_GND
SENSE_IN+
VCM_A­VDD
CS
CP

D99IN1051

PIN DESCRIPTION(PinTypes: D = Digital,P = Power,A = Analog)

N. Name Function

1 FCOM Output of the Spindle zero cross or Current Sense circuit.
2 CTAP Spindle Central Tap used for differential BEMF sensing.
3 PWM/SLEW RC network sets the Spindle Linear Slew Rateand PWM OFF-Time.
4 OUT_C Spindle DMOS Half Bridge Output and Input C for BEMF sensing.
5 I_SENSE Input to sense the voltage the SPINDLE Sense Resistor.
6 R_SENSE Output connection for the Motor Current Sense Resistor to ground.
7 OUT_B Spindle DMOS Half BridgeOutput and Input B for BEMF sensing.
8 GND Spindle Ground (Substrate).

9 R_SENSE Output connection for the Motor Current Sense Resistor to ground.
10 OUT_A Spindle DMOS Half Bridge Output and Input A for BEMF sensing.
11 INDEX Input to allow Spindle to be locked to Index (servo) pulse.
12 BRK_CAP Storage Capacitor for brake circuit. typically 5.9V.
13 VDD +5V Power Supply for Spindle Power section.
14 DGND Digital Ground.
15 SYS_CLK Clock Frequency for system timers and counters.
16 SDEN Serial DataEnable. Active high input pin for the serial port enable.
17 SDATA Serial Port Data. Input/Output pin for serial data, 8bits of instruction/address followed by 8

bits of data. Open pin is at logic low as an input.
18 SCLK Serial Port Data Clock. Positive edge triggered clock input for the serial data.
19 VDD Digital/Analog power supply. +5V nominally.
20 V12/2 Reference Output for VCM control loop. Typically, half of the VCC except when parking.
21 FLL_FILTER Speed loop R/C compensation connection used for FLL mode operation.
22 VCM_CAL VCM loop offset voltage used forcalibration.
23 CP External Main Charge Pump Capacitor, Typically, Vz+Vcc is about 17.8V
24 CS External Charge Pump Capacitor.
25 VDD +5V Power Supply for VCM Power section.
26 VCM_A- VCM Power Amplifier negative output terminal.
27 SENSE_IN+ Non inverting Input of the Sense Amplifier for VCM block.
28 VCM_GND Ground for VCM Power section.
29 SENSE_IN- Inverting Input of the Sense Amplifier for VCM block.
30 VCM_A+ VCM Power Amplifier positive output terminal.
31 VDD +5V Power Supply for VCM Power section.
32 FLL_RES Resistor for setting accurate bias current sources for the chip (62K required).
33 SW1 External ISOFET driver.
34 PORB Power on Reset Output. Low signal indicates the failure of the supplies.
35 TR_5V Set Point Input for 5V Supply Monitor ( 2Vthreshold, 100mV Hysteresis)
36 POR_DELAY Capacitor connection to set the Power on Reset Delay (3V threshold, 2µA charging)
37 SENSE_OUT Output of the Sense Amplifier.
38 ERROR_OUT Output of the Error Amplifier.
39 ERROR_IN Inverting Input of the Error Amplifier.
40 CLK_MON Watchdogclock monitoring pin
41 DAC Output of the VCM DAC.
42 AGND Analog Ground. For bang gap voltage reference.
43 VCC +12V Power Supply for Spindle Power section.
44 SPN_COMP External RC network that defines the compensation of theSpindle Transconductance Loop

in Linear Mode.

L6275

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L6275

ABSOLUTEMAXIMUM RATINGS

Symbol Parameter Value Unit

V

CC

V

dd

V

in max

V

in min

SPINDLE I

VCM I

peak

P

(*) Maximum Total Power Dissipation ≈ 1.7 W

tot

T

stg,Tj

THERMAL DATA

Symbol Parameter Value Unit

R

th j-case

R

th j-amb

(*) In typicalapplication with multilayer 120X120mm Printed Circuit Board

Maximum Supply voltage -0.5 to 14 V
Maximum Logic supply -0.5 to 6 V
Maximum digital input voltage Vdd+0.3V V
Minimum digital input voltage GND - 0.3V V
Spindle peak sink/source output current 2.1 A

peak

VCM peak sink/source output current 1.6 A

Maximum Storage/Junction Temperature -40 to 150 °C

Thermal Resistance Junction to Case ≈ 20 °C/W

(*) Thermal Resistance to Junctionto ambient

40 °C/W

≈

RECOMMENDED OPERATINGCONDITIONS

Symbol Parameter Value Unit

V

dd

T

amb

T

j

ELECTRICAL CHARACTERISTICS

Supply Voltage 4.5 to 5.5 V
Operating Ambient Temperature 0 to 70 °C
Junction Temperature 0 to 125 °C

(All specifications are for 0 < T

<70°C, VCC= 12V; VDD= 5V,

amb

FLL_RES= 62kΩ, unlessotherwisespecified.)

Symbol Parameter Test Condition Min. Typ. Max. Unit

POWER SUPPLIES

V

rectified

V

dd

I

Vdd

THERMAL SENSING

T

SD

T

HYS

T

EW

VCCSupply Rectified 3.5 13.2 V
5V supply 4.5 5.5 V
5V supply SPINDLE + VCM 6 mA

SPINDLE ONLY 7 mA
VCM ONLY 12 mA

Shutdown Temperature 150 180 °C
Hysteresis 60 °C
Early Warning TSD-25 °C

4/17

ELECTRICALCHARACTERISTICS (Continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY MONITOR

V

TR

V

HYS

I

DLY

R

on_por

V

DLY

I

IN

VOLTAGE BOOST

V

BOOST

F

osc

SYSTEM CLOCK WATCHDOG

Min_Clk Min. System Clock Time 7 10 13 µs

SW1 OUTPUT

R

GATE

V

GATE

DIGITAL LOGIC LEVELS

V

IH

V

IL

V

OH

V

OL

F

SYSCLK

VCM, DAC

T

C

VCM, ERROR AMPLIFIER

A

VOL

V

OS

I

IB

V

ICM

Trip Point Input Rising 1.92 2 2.08 V
Hysteresis Voltage Input falling 100 mV
Porb Delay Current TR_5V, TR_12V > V

TR

1.5 2 2.5

Vpordly = 2V

Porb Pull Down Ron Vdd> 2V and sink 1mA

V

=2V

pordly

Porb Dly Threshold TR_5V > V

TR

2.0 V

500

Input Current VIN<4V -1 1 µA

Output Voltage Vdd+5 Vdd+6.3 V
Internal Oscillator 130 200 250 kHz

Gate Driver for External Mosfet Internal Resistor to CP 200 kΩ
Off Gate State Voltage for

IO= 1mA Vdd= 3.5V 0.7 V

External Mosfet

Input Logic ”1” 2.5 V
Input Logic ”0” 0.5 V
Output Logic ”1” I
Output Logic ”0” I

=20µAV

SOURCE

= -400µA 0.4 V

SOURCE

-0.2 V

dd

System Clock 20 25 MHz

Resolution 14 Bits
Differential Linearity 1 LSB Change

-Tested

-By design

-1

-0.5

1

0.5
Integral Linearity 9 Bits
Midscale Offset Referenced to V

/2 -5 5 mV

CC

Convertion Time 5 µs
Full Scale Voltage Referenced to V

/2 ±1V

CC

Full Scale Error -4 4 %

Open Loop Gain DC 50 db
Input Offset Voltage -5 5 mV
Input Bias Current --250 250 nA
Input Common Mode Range VCC/2-

0.5

VCC/2+

0.5

L6275

A

µ

Ω

LSB

V

5/17

L6275

ELECTRICALCHARACTERISTICS (Continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Vclamp Output Clamp Voltage -1mA < I

Lowside/Highside clamp

F

ODB

Unity Gain Bandwidth 10 MHz

VCM, POWER STAGE

R

DS(ON)

I

O

I

O(LEAK)

Output ON Resistance (Each
device)

Tj=25°C
T

= 125°C

j

Operating Current 1.3 A
Output Leakage Current VCC= 5.5V 1.0 mA

VCM, CURRENT SENSEAMPLIFIER

V

V

F

A

OCM

V

V

ICM

OS

3dB

Voltage Gain 3.88 4 4.12 V/V
Input Common Mode Range -0.3 Vdd+0.3 V
Output Common Mode Range -3mA < IO<3mA 2 Vdd-2 V
Output Offset Voltage SENSE_IN (±)=Vdd/2 -15 15 mV
3dB Bandwidth 1 MHz

CMRR Input Common Mode Rejection 50 dB

PSRR Power Supply Rejection Ratio 60 dB

VCM, RETRACT

V

park

RETRACT VOLTAGE PKV_1= 0 & PKV_2 = 0

PKV_1 = 0 & PKV_2 = 1
PKV_1 = 1 & PKV_2 = 0
PKV_1 = 1 & PKV_2 = 1

Tretract Retract Time

limited by the internal oscillator
200kHz

RT0 = 0 & RT1 = 0
RT0 = 0 & RT1 = 1
RT0 = 1 & RT1 = 0
RT0 = 1 & RT1 = 1

SPINDLE, PWM CURRENT SENSE COMPARATOR

T

DLY

Delay to FCOM Out 200 500 ns

SPINDLE, POWER STAGE

R

DS(ON)

I

O

I

O(LEAK)

dV

O/dt

Output On Resistance (Each
device)

Tj=25°C
T

= 125°C

j

Start-Up Current 2A
Output Leakage Current VCC = 14V 1.0 mA
Output Slew Rate (Linear) R

slew

Output Slew Rate (PWM) Reg#8Eh, Bit 0 = 0

Reg#8Eh, Bit 0 = 1

BEMF

Minimum BENF Voltage for

MIN

Detection

V

HYS

Hysteresis 15 mV

FLL CHARGE PUMP OUTPUT

I

LEAK

I

O

Off State Leakage 0 < Vfll_res , 3V -50 +50 nA
On State Current FLL_RES = 62k

ICP = ”1”
ICP = ”0”

V

RCP

Current Set Voltage FLL_RES = 62k

<1mA

O

Vdd/2

±

1.4V

0.5

0.8

0.850

0.650

1.600

1.150
160

320

80

160

0.45

0.74

= 100kΩ 0.2 0.3 0.5 V/µs

10
20

20 28 40 mVp-p

Ω

22
80

Ω

1.18 1.225 1.25 V

25

100

32

120

V

Ω
Ω

mV
mV
mV
mV

ms
ms
ms
ms

Ω
Ω

V/µs
V/µs

µA

A

µ

6/17