SGS Thomson Microelectronics L6269 Datasheet

L6269
12VDISK DRIVE SPINDLE& VCM, POWER
& CONTROL“COMBO”
PRODUCT PREVIEW
GENERAL
12V (+/- 10%) OPERATION. REGISTERBASEDARCHITECTURE MINIMUMEXTERNAL COMPONENTS BICMOS+ VERTICALDMOS (1.5mm)
VCM DRIVER
1.5ADRIVE CAPABILITY
0.9WTOTALBRIDGE IMPEDANCEAT 25°C LINEARMODE PHASESHIFT MODULATION(PWM MODE) INSTANTANEOUS, (GLICH FREE) SWITCH
BETWEENTHE 2 MODES CLASS ABOUTPUTDRIVERS ZEROCROSSOVERDISTORSION 14 BIT DAC DEFINE OUTPUTCURRENT SELECTABLETRANSCONDUCTANCE 4 PROGRAMMABLEPARKINGVOLTAGE DYNAMICBRAKE
SPINDLEDRIVER
2.0ADRIVE CAPABILITY
0.8WTOTALBRIDGE IMPEDANCEAT 25°C BEMF, INTERNAL OR EXTERNAL, PROC-
ESSING SENSOR-LESSMOTOR COMMUTATION PROGRAMMABLE COMMUTATION PHASE
DELAY LINEARMODE AND CONSTANT TOFF PWM
OPERATIONMODE INTERNAL FREQUENCY LOCKED LOOP
SPEEDCONTROL (FLL) BEMFRECTIFICATIONDURING RETRACT BUILT-INALIGNAMENT&GOSTART-UP INDUCTIVE SENSINGSTART UP OPTION RESYNCHRONIZATION DYNAMIC& REVERSEBRAKE CONTROLLABLEOUTPUTSLEW RATE
OTHER FUNCTIONS
12V AND 5V MONITORINGWITH EXTERNAL SET TRIP POINTSANDHYSTERESIS
POWERUP/DOWN SEQUENCING
BICMOS TECHNOLOGY
TQFP44 (10x10mm)
ORDERING NUMBER: L6269
LOW VOLTAGESENSE
3.3V INPUT LOGICCOMPATIBILITY THERMAL SHUTDOWN AND PRETHERMAL
WARNING
DESCRIPTION
The L6269 integrates into a single chip both spin­dle and VCMcontrollers as well as power stages. The device isdesigned for 12V diskdrive applica­tion requiring up to 2.0A of spindle and 1.5A of VCM peak currents.
A serialport with up to25 MHz capabilityprovides easy interface to the microprocessor. A register controlled Frequency Locked Loop (FLL) allows flexibility in setting the spindle speed. Integrated BEMF processing, digital masking, digital delay, and sequencing minimize the number of external componentsrequired.
Power On Reset(POR) circuitry is included.Upon detection of a low voltage condition, POR is as­serted, the internal registers are reset, and spin­dle powercircuitryis tri-stated.The BEMF is recti­fied providing power for actuator retraction followed by dynamicspindlebraking.
The device is built in BICMOS technology allow­ing dense digital/analog circuitry to be combined with a highpower DMOS outputstage.
April 1999
This is preliminary information on a new product now in development. Details are subject to change withoutnotice.
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L6269
BLOCK DIAGRAM
SW1
SDATA
SCLK
SDEN
TR_12V
TR_5V
CS
CP
CHARGE
PUMP
ISO
DRIVER
SERIAL
INTERFACE
SUPPLY
FAULT
MONITORS
POR_DELAY
PORB
FLL_RES
FLL_FILTER
INDEX
FREQUENCY
LOCK LOOP
START-UP
REGISTERS
THERMAL
SUPPLY
VDD
SYS_CLK
GND
DGND
FCOM
SPINDLE SEQUENCER
RE_SYNC
DYNAMIC/ REVERSE
BRAKE
VCM CURRENT
CONTROL PSM/LIN
VCM
CALIBRATION
BIT
DAC
REFERENCE GENERATOR
14
VCM DAC
SPN_COMP
PROCESSING
ZERO CROSS
VOLTAGE
V12/2
BRK_CAP
PWM/SLEW
BEMF
DETECTION
SPINDLE CURRENT CONTROL
PWM/LIN
PARKING
BEMF
RECTIFICATION
VCM_CAL
ERROR_IN
+
-
A
B
C
A+
A-
A=4
SENSE_OUT
ERROR_OUT
VCC
­+
D99IN1042
OUT_A CTAP
OUT_B RSENSE
OUT_C ISENSE
VCM_A+ VCC
VCM_A­VCM_GND
SENSE_IN­SENSE_IN+
PIN CONNECTION
2/17
FCOM
CTAP
PWM/SLEW
OUT_C
I_SENSE
R_SENSE
OUT_B
GND
R_SENSE
OUT_A
INDEX
SPN_COMP
VCC
AGND
DAC
ERROR_IN
TR-12V
ERROR_OUT
SENSE_OUT
44 43 42 41 3940 38 37 36 35 34
1 2 3 4 5 6 7 8 9
10
12 13 14 15 16
VCC
BRK_CAP
DGND
SDEN
SYS_CLK
171118 19 20 21 22
VDD
SCLK
SDATA
POR_DELAY
TR_5V
PORB
V12/2
VCM_CAL
FLL_FILTER
33 32 31 30 29 28 27 26 25 24 23
D98IN847
SW1 FLL_RES VCC VCM_A+ SENSE_IN­VCM_GND SENSE_IN+ VCM_A­VCC CS CP
PIN DESCRIPTION(Pin Types:D = Digital,P = Power,A = Analog)
N. Name Function
1 FCOM Output of the Spindle zerocross or Current Sense circuit. 2 CTAP Spindle Central Tap used for differential BEMF sensing. 3 PWM/SLEW RC network sets the Spindle LinearSlew Rateand PWM OFF-Time. 4 OUT_C Spindle DMOS Half BridgeOutput and Input C for BEMF sensing. 5 I_SENSE Input to sense the voltage the SPINDLE Sense Resistor. 6 R_SENSE Output connection for the Motor Current Sense Resistor to ground. 7 OUT_B Spindle DMOS Half Bridge Output and Input B for BEMF sensing. 8 GND Spindle Ground (Substrate).
9 R_SENSE Output connection for the Motor Current Sense Resistor to ground. 10 OUT_A Spindle DMOS Half BridgeOutput and Input A for BEMF sensing. 11 INDEX Input to allow Spindle to be locked to Index (servo) pulse. 12 BRK_CAP Storage Capacitor for brake circuit. typically 5.9V. 13 VCC +12V Power Supply for Spindle Power section. 14 DGND Digital Ground. 15 SYS_CLK Clock Frequency for system timers and counters. 16 SDEN Serial DataEnable. Active high input pin for the serialport enable. 17 SDATA Serial Port Data. Input/Output pin for serial data, 8bits of instruction/address followed by 8
bits of data. Open pin is at logic low as an input. 18 SCLK Serial Port Data Clock. Positive edge triggered clock input for the serial data. 19 VDD Digital/Analog power supply. +5V nominally. 20 V12/2 Reference Output for VCM control loop. Typically, half of the VCC except when parking. 21 FLL_FILTER Speed loop R/C compensation connection used for FLL mode operation. 22 VCM_CAL VCM loop offset voltage used forcalibration. 23 CP External Main Charge Pump Capacitor, Typically, Vz+Vcc is about 17.8V 24 CS External Charge Pump Capacitor. 25 VCC +12V Power Supply for VCM Power section. 26 VCM_A- VCM Power Amplifier negative output terminal. 27 SENSE_IN+ Non inverting Input of the Sense Amplifier for VCM block. 28 VCM_GND Ground for VCM Power section. 29 SENSE_IN- Inverting Input of the Sense Amplifier for VCM block. 30 VCM_A+ VCM Power Amplifier positive output terminal. 31 VCC +12V Power Supply for VCM Power section. 32 FLL_RES Resistor for setting accurate bias current sources for the chip (62K required). 33 SW1 External ISOFET driver. 34 PORB Power on Reset Output. Low signal indicates the failure of the supplies. 35 TR_5V Set Point Input for 5V Supply Monitor ( 2Vthreshold, 100mV Hysteresis) 36 POR_DELAY Capacitor connection to set thePower on Reset Delay (3V threshold, 2µA charging) 37 SENSE_OUT Output of the Sense Amplifier. 38 ERROR_OUT Output of the Error Amplifier. 39 ERROR_IN Inverting Input of the Error Amplifier. 40 TR_12V Set PointInput for 12V Supply Monitor (2V threshold, 100mV Hysteresis) 41 DAC Output of the VCM DAC. 42 AGND Analog Ground. For bang gap voltage reference. 43 VCC +12V Power Supply for Spindle Power section. 44 SPN_COMP External RC network that defines the compensation of theSpindle Transconductance Loop
in Linear Mode.
L6269
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L6269
ABSOLUTEMAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
V
dd
V
in max
V
in min
SPINDLE I
VCM I
peak
P
(*) Maximum Total Power Dissipation 2.0 W
tot
T
stg,Tj
THERMAL DATA
Symbol Parameter Value Unit
R
th j-case
R
th j-amb
(*) In typical application with multilayer 120X120mm Printed Circuit Board
Maximum Supply voltage -0.5 to 14 V Maximum Logic supply -0.5 to 6 V Maximum digital input voltage Vdd+0.3V V Minimum digital input voltage GND - 0.3V V Spindle peak sink/source output current 2.1 A
peak
VCM peak sink/source output current 1.6 A
Maximum Storage/Junction Temperature -40 to 150 °C
Thermal Resistance Junction to Case 11 °C/W
(*) Thermal Resistance to Junction to ambient
40 °C/W
RECOMMENDED OPERATINGCONDITIONS
Symbol Parameter Value Unit
V
CC
V
dd
T
amb
T
j
ELECTRICAL CHARACTERISTICS
Supply voltage 10.8 to 13.2 V Maximum Logic supply 4.5 to 5.5 V Operating Ambient Temperature 0 to 70 °C Junction Temperature 0 to 125 °C
(All specificationsare for 0 < T
<70°C, VCC= 12V; VDD= 5V,
amb
FLL_RES= 62kΩ, unless otherwisespecified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
POWER SUPPLIES
V
I
VCC
V
rectified
V
I
CC
dd
Vdd
12V Supply 10.8 13.2 V VCCCurrent SPINDLE + VCM 20 mA
SPINDLE ONLY 7 mA
VCM ONLY 12 mA VCCSupply Rectified 3.5 13.2 V 5V supply 4.5 5.5 V 5V supply SPINDLE + VCM 6 mA
SPINDLE ONLY 7 mA
VCM ONLY 12 mA
4/17
ELECTRICALCHARACTERISTICS (Continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
THERMAL SENSING
T
SD
T
HYS
T
EW
SUPPLY MONITOR
V
TR
V
HYS
I
DLY
R
on_por
V
DLY
I
IN
VOLTAGE BOOST
V
BOOST
F
osc
SW1 OUTPUT
R
GATE
V
GATE
DIGITAL LOGIC LEVELS
V
IH
V
IL
V
OH
V
OL
F
SYSCLK
VCM, DAC
T
C
VCM, ERROR AMPLIFIER
A
VOL
V
OS
I
IB
Shutdown Temperature 150 180 °C Hysteresis 60 °C Early Warning TSD-25 °C
Trip Point Input Rising 1.92 2 2.08 V Hysteresis Voltage Input falling 100 mV Porb Delay Current TR_5V, TR_12V > V
TR
1.5 2 2.5 µA
Vpordly = 2V Porb Pull Down Ron Vdd> 2V and sink 1mA
V
=2V
pordly
Porb Dly Threshold TR_5V, TR_12V > V
TR
2.5 3.0 3.5 V
500
Input Current VIN<4V -1 1
Output Voltage VCC+5 VCC+6.3 V Internal Oscillator 130 200 250 kHz
Gate Driver for External Mosfet Internal Resistor to CP 200 k Off Gate State Voltage for
IO= 1mA VCC= 3.5V 0.7 V External Mosfet
Input Logic ”1” VDD= 5.5V 2.4 V Input Logic ”0” VDD= 4.5V 0.5 V Output Logic ”1” I Output Logic ”0” I
=20µAV
SOURCE
= -400µA 0.4 V
SOURCE
-0.2 V
dd
System Clock 20 25 MHz
Resolution 14 Bits Differential Linearity 1 LSB Change
-Tested
By design
-1
-0.5
1
0.5 Integral Linearity 9 Bits Midscale Offset Referenced to V
/2 -5 5 mV
CC
Convertion Time 5 Full Scale Voltage Referenced to VCC/2
1V
±
Full Scale Error -4 4 %
Open Loop Gain DC 50 db Input Offset Voltage -5 5 mV Input Bias Current -250 250 nA
L6269
A
µ
LSB
s
µ
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L6269
ELECTRICALCHARACTERISTICS (Continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
ICM
Vclamp Output Clamp Voltage -1mA < I
F
ODB
VCM, POWER STAGE
R
DS(ON)
I
O
I
O(LEAK)
VCM, CURRENT SENSE ANPLIFIER
A
V
V
ICM
V
OCM
V
OS
F
3dB
CMRR Input Common Mode Rejection 50 dB
PSRR Power Supply Rejection Ratio 60 dB
VCM, RETRACT
Vpark RETRACT VOLTAGE PKV_1 = 0 & PKV_2 = 0
Tretract Retract Time
SPINDLE, PWM CURRENT SENSE COMPARATOR
T
DLY
SPINDLE, POWER STAGE
R
DS(ON)
I
O
I
O(LEAK)
dV
O/dt
BEMF
V
HYS
FLL CHARGE PUMP OUTPUT
I
LEAK
Input Common Mode Range VCC/2-
0.5
<1mA
O
Lowside/Highside clamp
VCC/2±
2.2V
VCC/2+
0.5
Unity Gain Bandwidth 10 MHz
Output ON Resistance (Each device)
Tj=25°C T
= 125°C
j
0.5
0.8 Operating Current 1.3 A Output Leakage Current VCC= 14V 1.0 mA
Voltage Gain 3.88 4 4.12 V/V Input Common Mode Range -0.3 VCC+0.3 V Output Common Mode Range -3mA < IO<3mA 2 VCC-2 V Output Offset Voltage SENSE_IN (±)=VCC/2 -15 15 mV 3dB Bandwidth 1 MHz
850
650 1600 1150
320
640
160
320
limited by the internal oscillator 200kHz
PKV_1 = 0 & PKV_2 = 1 PKV_1 = 1 & PKV_2 = 0 PKV_1 = 1 & PKV_2 = 1
RT0 = 0 & RT1 = 0 RT0 = 0 & RT1 = 1 RT0 = 1 & RT1 = 0 RT0 = 1 & RT1 = 1
Delay to FCOM Out 200 500 ns
Output On Resistance (Each device)
Tj=25°C T
= 125°C
j
0.45
0.74 Start-Up Current 2A Output Leakage Current VCC = 14V 1.0 mA Output Slew Rate (Linear) R Output Slew Rate (PWM) Reg#8Eh, Bit 0 = 0
Minimum BENF Voltage for
MIN
= 100k
slew
Reg#8Eh, Bit 0 = 1
0.2 0.3 0.5 V/µs 10
20
20 28 40 mVp-p
Detection Hysteresis 15 mV
Off State Leakage 0 < Vfll_res , 3V -50 +50 nA
V
V
Ω Ω
mV mV mV mV
ms ms ms ms
Ω Ω
V/µs V/µs
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