SGS Thomson Microelectronics L6260 Datasheet

L6260

4.5 – 5.5V DISK DRIVER SPINDLE & VCM, POWER & CONTROL COMBO’S

GENERAL

5V OPERATION. *REGISTERBASED ARCHITECTURE

MINIMUMEXTERNALCOMPONENTS SLEEP AND IDLE MODES FOR LOW

POWERCONSUMPTION SELECTABLE GAINS FOR BOTH V.C.M.

AND SPINDLE 10 BIT (+ SIGN + GAIN ) VCM & 8 BIT SPIN-

DLE DACs HIGH BANDWIDTH SPEED REGULATION

LOOP (ONCE PER MECH\ELEC CYCLE ACCURACY)

VCM DRIVER

CURRENT SENSE CONTROL (VOLTAGE PROPORTIONALTO CURRENT)

300mADRIVE CAPABILITY TWO CURRENT RANGES FOR SEEKING

AND TRACKING INTERNAL REGISTER FOR POWER AMP

CONTROLLINES

SPINDLEDRIVER

BEMF PROCESSING FOR SENSORLESS MOTOR COMMUTATION

PROGRAMMABLE COMMUTATION PHASE DELAY

PROGRAMMABLE SLEW-RATE FOR REDUCED E.M.I.

0.8Ω FOR ANYHALF BRIDGE WORST CASE SYNCHRONOUS RECTIFICATION OF THE

B.E.M.F.DURING RETRACT OPERATION BIPOLAR\ TRIPOLAR OPERATION SYNTHESIZEDHALL OUTPUTS

1.0 AMPDRIVE CAPABILITY

OTHER FUNCTIONS

POWERUP SEQUENCING POWERDOWN SEQUENCING LOW VOLTAGE SENSE ACTUATORRETRACTION DYNAMICBRAKE THERMALSHUTDOWN

BICMOS TECHNOLOGY

TQFP64

ORDERING NUMBER: L6260

THERMAL& CURRENT PROTECTION

DESCRIPTION

The L6260 is single chip sensorless (DC) spindle motor and voice coil controllers including power stages suitablefor usein smalldisk drives.

These devices have a serial interfacefor a microprocessorrunning up to 10 Mega bits per second. There are registers on chip to allow the setting of the desired spindle speed via the on chip FrequencyLocked Loop (F.L.L.). No externalcomponents are requiredin the sensor-lessoperation as the control functions are integrated on chip (e.g. B.E.M.F.processing, digital masking, digitaldelay and sequencing).

The V.C.M. driversuses a transconductanceamplifier, able to provide 2 different current ranges, suitable forseeking and tracking.

When a low voltage is detected,a Power On Reset (P.O.R.) is issued and the internal registers are reset, the spindle power circuitry is tri-stated, B.E.M.F.synchronous rectification is enabled, the actuator retracts and then dynamic braking of the spindle is applied.

These devices are built in BICMOStechnologyallowing dense digital circuitry to be combined with MOS\Bipolarpower devices.

November 1996

1/30

L6260

BLOCK DIAGRAM

VREFOUT

VREF/MINUS

DAC/GND

UV1 UV2

POR/DLY

POR

FCLK

SDIO

SCLK

SLOAD

R/W

TEST

TRISTATE

ATEST DTEST

177

SERIAL

PORT

INTERFACE

POWER

MONITOR

CIRCUIT

BIAS

PARK/V VCM/COMP

VCM LOGIC &

VCM

PARK

ANALOG TEST

CIRCUIT

DAC

BEMF

AMP

SPINDLE

LOGIC

SPINDLE

FLL

DIGITAL TEST

CIRCUIT

VCM/PLUSVCM/I/SNS/2VCM/I/SNS/1

VOLTAGE

TRIPLER

CENTER TAP

DRIVER

SPINDLE

BLOCK & DAC

CURRENT

GENERATOR

CHARGE

PUMP

VCM/MINUS VVCM/2 VVCM/1 C1LOW C1HIGH C2LOW C2HIGH

VHTRIP VLTRIP

VPARKOUT

CTAP

SYNTH/HALL VRECT VSPIN/1 VSPIN/2 SPN/I/SNS COIL/A COIL/B COIL/C SPIN/GND1 SPIN/GND2 VPDOWN BRK/DLY SPN/I/COMP

SPN/SLEW FLL/RES

SPD/COMP SPD/COMP/SHT

D94IN087

PIN CONNECTION(Top view)

SPN_DSBL_DLY

POR_DLY

VCM_I_SNS1

VVCM_1 VCM_MINUS VCM_I_SNS2

VCM_PLUS

VVCM_2

C1HIGH

C1LOW

TRIPGND

C2HIGH

2/30

GND

CTAP

ATEST

GND

PARKV

AGRND

DACGND

VFER_MINUS

REF OUT

VCC

SPIN SLEW

FLL RES

SPD COMP SHT

116

2 C

RIP T

L V

RIP

P HT V

COM M

C V

GND IG

C D V

D A O L S

DIO

SPD COMP

K L C F

T C E R V

GND

N P S

GND

GND VSPIN_2

VPDOWN COIL_C BRK_DLY SPIN_GND_2 EXTFLL/DTEST COIL_B TRISTATE VSPIN_1 SYNTH_HA LL TEST COIL_A R/W_ SPN_GND_1 GND

GND

VPARKOUT

SPN1 COMP

PIN DESCRIPTION

Pin Types:I = Input,O = Output,P = Power, A= Analog (passive)

Power

L6260

PIN # PIN NAME DESCRIPTION

8 VDC Digital power. Positivenominally 5V or 3V AI No No 41 VCC Analog power. Positivenominally 5Vor 3V AI No No 54 VVCM_1 VCM power supply. Positive nominally 5V or 3V AI No No 58 VVCM_2 Same as above AI No No 23 VSPIN_1 Spindle power pin.Positive nominally 5V or 3V AI No No 31 VSPIN_2 Same as above AI No No

1 GND Ground AI No No

15-17 GND Ground AI No No 32-34 GND Ground AI No No 47-49 GND Ground AI No No

18 SPN_GND_1 Ground forspindle circuit AI No No 27 SPN_GND_2 As above AI No No 44 DAC_GND Ground forall DACs AI No No 45 AGND Analog ground AI No No

7 DIG_GND Digital ground AI No No 63 TRIPGND Voltage triplerground AI No No

TYPE

I\O

MAPPED?

TRI-STATE

@SLEEP/@POR

Serial Interface& Test Pins

PIN # PIN NAME DESCRIPTION

12 FCLCK System clock. 4-12MHz selectable via the

CLK_PRESCALE bit inthe System Control Register B (Reg 4 Bit 4).

11 SDIO Serial port data I/O running up to 10MHz. For full

details of allserial port signals see theCircuit

Description section. 10 SCLK Serial port clock (max 10Mbits/s) DI Yes No 19 R/W Read / Write signal for serial interface DI Yes No

9 SLOAD Chip select input. DI Yes No

21 TEST Used to enable one of the test modes. The mode is

selcted in conjunction with the TRISTATE pin (see

below for more details). 24 TRISTATE Used to enable one of the test modes. The mode is

selcted in conjunction with the TEST pin (see below

for more details).This pin has no effect on the

spindle or VCM drivers, this is a test pin only. 60 ATEST Analog test pin. This pin carries the required analog

signal to allow external testing. 26 DTEST Digital Test Output Pin. This pin also doubles as the

Clock input if an external FLL is used.

TYPE

DI Yes No

DI/O Yes Yes

DI No No

AO No No

DI/O No No

I\O

MAPPED?

TRI-STATE

@SLEEP/@POR

Test Mode TEST pin TRISTATE pin

IOMAPPING Test 1 0 DIGITAL Test* 1 1 ANALOG Test* 1 1 TRISTATE Test 0 1 Normal Operation (non

test mode)

For a detailed description please refer to the Test Circuit section of the CIRCUIT OPERATION portion ofthis datasheet

* These two test modes operatesimultaneously through separate

test pins (ATESTand DTEST).

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L6260

PIN DESCRIPTION(continued)

Pin Types:I = Input,O = Output,P = Power, A= Analog (passive)

VCM Driverand DAC

PIN # PIN NAME DESCRIPTION

53 VCM_I_SNS1 High side ofVCM sense resistornetwork. This pin

provides the current to the network as well as

sensing the total voltage across both sense

resistors. Sensing the total drop across both

resistors results in the low transconductancegain

feedback used fortrack following. 56 VCM_I_SNS2 Sensing across the lower VCM sense resistor for

high transconductance gain feedback for seek

operations.

6 VCM_COMP VCM compensation network. Typically, 200KΩin

series with 100nF is connected from this pin to

Ground. 57 VCM_PLUS VCM Power Amplifierpositive output terminal A No No 55 VCM_MINUS VCM Power Amplifier negativeoutput terminal A No No 46 PARK_V A resistor conneced between this pin and

VCM_PLUS determines the Parking Voltage 35 VPARKOUT Output from the retract circuit. This pinis usually

directly connected to the VCM_MINUS.

TYPE

ANo No

AO No No

Spindle Driver and DAC

PIN # PIN NAME DESCRIPTION

40 SPN_SLEW The External.SpindleDriver Slew Rate resistor

(Rslew), typically250K isconnected from thispin to

Ground. When in nExternal Slew Rate Mode

(System Control Register B, Bit 10=0), the slew rate

is determined by:

SlewRate = (0.5Vto Rslew) X (DACslew+1) +20pF

DAC slew = System Control Register bits 7 - 9. 36 SPN_I_COMP A seroies RC network from this pin to ground sets

the spin drivercompensation. Typical a single 4nF

capacitor will provide adequate compensation. 14 SPN_I_SNS A current sensing resistor (2.5KΩTypical ).is

connected from this pin to ground. See the Circuit

Operation section for details. 20 COIL_A Spindle Power Amplifieroutput A. Also serves as

BEMF sensing forPhase A. 25 COIL_B Spindle Power Amplifieroutput B. Also serves as

BEMF sensing forPhase B. 29 COIL_C Spindle Power Amplifier output C. Also serves as

BEMF sensing forPhase C. 59 CTAP Spindle Motor Center Tap connection A No No 22 SYNTH_HALL CMOS level spindle speed output.When SYNHALL

(System Control Register B, bit 5) is set to 0, this

output switches stateat every zerocrossing of any

phase. With SYNHALL = 1, the output only switches

every zero crossingof Phase A. 37 SPD_COMP Change Pump RC network connection pin for FLL

mode operation. 38 SPD_COMP_SHTThis pin allows for shorting ofto the Charge Pump

Network resistor. This operation provides a quick

charge on the Charge Pump capacitor, reducing

settling time oncedesired speed isreached.

Operation is controlledby bit 9 of System Control

(Rep), typically 12.5KΩ , is connectedfrom this pin

to Ground. Change Pump current is determined by:

I = (0.5Vto Rcp) X (FLLGAIN DAC +1)

FLLGAIN DAC = System Control Register B bits 0-4

TYPE

ANo No

AO No No

ANo No ANo No ANo No

DO Yes Yes

ANo No ANo No

ANo No

I\O

MAPPED?

I\O

MAPPED?

@SLEEP/@POR

TRI-STATE

4/30

PIN DESCRIPTION(continued) Pin Types:I = Input,O = Output,P = Power, A= Analog (passive)

Power down sequencing, POR, other voltage pins

L6260

PIN # PIN NAME DESCRIPTION

13 VRECT Outputofthe synchronous rectifiersupplying powerto

28 BRK_DLY An external parallel RC network from thispoint to

30 VPDOWN Voltage triplerreservoir capacitor. Thisis used for

61 C1HIGH Positive terminalof charge pump capacitor.

62 C1LOW Negative terminal of charge pump capacitor.

64 C2HIGH Positive terminalof charge pump capacitor for

2 C2LOW Negative terminal of charge pump capacitor for

52 POR_DLY An external capacitor from this pinto ground sets

5 POR Power On Reset. Thisopen drain output goeslow

50 UV1 Under voltage detector 1.This defines the

51 SPN_DSBL_

DLY

4 VHTRIP High tripler/Doubler output. 330nF (typ). 11V max. AO No No 3 VLTRIP Low tripler/Doubler output. 330nF (typ). for stability. AO No No

theretractcircuitry.Filteredbyan internal 400pF

capacitor.Normally notexternallyconnected.However,

ifretractcommandistobeused, asmall signalsilicon

diodemustbeconnectedbetweenthispinandVcc

(Cathode to VRECT)to supply theadditional current

whichmaybe requiredtobrakethe VCM.

ground sets the Brake dELAY:T= 0.45 RC.

Typical values are R = 4MΩ, C=0.1µF (0.16sec,

delay).

the brake operation when power is removed from

the chip. NoDC load allowed.1µF minimum, 10µF

prefered.

10nF (typ) for Tripler operation;

330nF (typ0 or Doubler operation

10nF (typ) for Tripler operation;

330nF (typ)or Doubler operation

Tripler operation. 330nF (typ).

Connected tp VHRTRIP for Doubler operation.

Tripler operation. 330nF (typ).

Not connected forDoubler operation.

the duration of POR after power has been re-

established. T (por)= 32 X C (por)

where: C (por)is in pFand T is expresssed in µs.

when the voltageat either UV1 or UV2 goesbelow

1.25V.

VOLTAGE GOOD thresholdby comparing the

voltage on this pin to the internal 1.25V reference.

An external resistor divider network and capacitor

filter provides the selection of threshold and supply

noise rejection. There is an internal pull-up (2µA

max). Hysteresis is 20mV.

Spindle Disable Delay. A capacitor connected

between this pin and Vcc programs the delay

between POR and the disabling of the Spindle

section..

Delay = 80 xC (C in pF; Delay in µs)

TYPE

AO No No

ANo No

DO Yes No

AI Yes No

I\O

MAPPED?

TRI-STATE

@SLEEP/@POR

5/30

L6260

PIN DESCRIPTION(continued)

Pin Types:I = Input,O = Output,P = Power, A= Analog (passive)

AuxiliaryFunctions

PIN # PIN NAME DESCRIPTION

TYPE

I\O

MAPPED?

TRI-STATE

@SLEEP/@POR

42 REFOUT Output from auxiliaryOPAMP. A No No

43* VREF_MINUS

(L6260 only)

26 EXTFLL/

DTEST

Negative input toauxiliary OPAMP. This is prsent

ONLY on the L6260.

See previous description of this pin(Serial interfaca

& Test Pinsection).

ANo No

DI/O No No

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Units

dd,Vp max

in max

in min

peak

tot

stg,Tj

Maximum Supply voltage 6.5 V Maximum input voltage Vdd + 0.3V V Minimum input voltage GND - 0.5 V V Peak sink/source output current 1.5 A DC sink source output current 1.0 A Maximum Total Power Dissipation 1.0 W Maximum storage/junction temperature -40 to 150 °C

POWERDISSIPATION

Symbol Parameter Test Condition Min. Typ. Max. Units

dd,Vp

READY QUIESCENT CURRENT VCM ENABLED SPINDLE

IDLE QUIESCENT CURRENT VCM DISABLEDSPINDLE

SLEEP QUIESCENT CURRENT VCM DISABLEDSPINDLE

Supply voltage range 4.5 5.5 V

20 mA

ENABLED

10 mA

ENABLED

5mA

DISABLED

THERMAL DATA

Symbol Parameter Value Unit

th j-case

th j-amb

(*) In typical application with multiplayer printed circuit board.

Thermal Resistance Junction to Case 10

(*) Thermal Resistance Junction toCase 41.5

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

Supply Voltage 4.5 to 5.5 V Operating Ambient Temperature 0 to 70 °C Junction Temperature 0 to 125 °C

6/30

ddn

amb

C/W

ELECTRICALCHARACTERISTICS VCM Driver

Symbol Parameter Test Condition Min. Typ. Max. Units

ocr

ofr

ABEF Source & Sink On Resistance

dson

jump

deadband

csbias

PSRR DC Power Supply Rejection

BW Current LoopBandwidth La = 1mH Ra=40ohms

Max Current Coarse Range 300 mA Max Current Fine Range 75 mA

Coarse

Tj=125 °C,

= 300 mA

load

1.0 2.5 Ohms

CD Sink On ResistanceFine Range C, D VCM drive transistors 5.0 10.0 Ohms

Current SenseJump

1 LSB

Discontinuity Current SenseDeadband 200 µV Current SenseBias Current 1 µA

4.5 to5.5 V 50 dB

Ratio

20 KHz

=75mA

max

Figure 1: Vjumpvs. Deadband

Y(at) UNITS imax 1024

L6260

Operational Nominal

Area

UNITS L.D.D.

X(in) DAC

Value

-1

-2

-3

+3 +2 +1 +1 +2 +3

D94IN090

VCM DAC

Symbol Parameter Test Condition Min. Typ. Max. Units

Resolution 10 Bits Resistive Ladder PlusSign (1 Bit)

N.L. Differential Non-Linearity 1 LSB

I.N.L. Integral Non - Linearity 3.0 LSB

Conversion Time 0 - 90 % From Input Of LastBit (for any

FSTC Full ScaleTemperature

Coefficient

Voh High Output Voltage 25 °C, No Load 0.240 0.250 0.260 V

Vol Low output Voltage 25 °C, No Load 100 µV

PSRR Power SupplyRejection 50 dB

Unipolar 11 bits

1.0 µs

change of code) 0 to 125°C 250 ppm/C

7/30

L6260

ELECTRICALCHARACTERISTICS(continued) Spindle Motor

Symbol Parameter Test Condition Min. Typ. Max. Units

Sink Sink On Resistance Tj=125°C,I

dson

Total Total drive resistance

dson

dv/dt Voltage Slew Rate 0.2 2 V/µs

Spindle Current Sense FET

linearity

Large signal

Linearity

small signal

BW Current loopbandwidth small

FS Full scale current error 5 %FS

matching Current sense matching 25 to 250 mA 5 %

DAC AccelerationControl

res Resolution Full scale 8 bits

NL Differential Non-linearity 0.5 LSB

INL Integral Non-linearity 1 LSB

FS Full scale accuracy 5 % CT Conversion time 10 ms

FSTC Full ScaleTemp Coefficient 250 ppm/°C

Gain1X Current SenseGain at 500:1 502 525 554 Gain5X Current SenseGain at 2500:1 2400 2900

Step-up Converter

su3

Digital Inputs (Alldigital inputs are CMOS compatible)

Power On Reset(Either lowvoltage detectorcan be disabled bytrying the dividerto a high voltage)

delay

ref

Retract

Maximum Output Current 1 A

= 1A 0.4 Ohms

load

dson

sink +R

dson

source

Current sense circuit linearity

=125 °C, I

1% to fullscale current 5 %FS

= 1A 0.8 Ohms

load

(spin-up). 2000:1 current sense. Current sense circuit linearity(at

1% to 10%full scale 0.5 %

speed). 500:1current sense.

Lmotor 100µHto1µH 20 KHz

signal (atspeed)

1.235 1.25 1.245 V 0 0.2 0.3 V

Step-up converter voltage (using Tripler as a doubler)

= 4.5 to 5.5 volts,

Maximum load

above 5V.

High level input voltage Iin= TBD 30%

Low level inputvoltage Iin= TBD 70%

High level output voltage I Low level outputvoltage I

= TBD Vdd-0.6 V

out

= TBD 0.4 V

out

Input leakage current Tj=125°C+1-1

Minimum delay powerOK to RESET high

POR_DELAY

= 0.22*H 50.32 70.4 64.46 ms

Voltage reference 1.235 1.25 1.265 V

I for V

8/30

retract

dson

Retract time beforebrake power low detected

= 0.4 x RC

retract

TBD TBD ms

Total switch circuitresistance 10 Ohms 2 quadrant retract voltage V

retract

> PARK_Voltage 11 13 15 µA

BEMF

INTERNAL REGISTERDEFINITION System Status Register(Reg 0) Reg: 0 Name: SystemStatus Register Type: Readonly.

BIT LABEL DESCRIPTION @POR

0 THERMAL Thermal shutdown = 1, normal = 0.One signifies that the chip

temperature has exceeded the 180°C. The bit will reset when the temperature falls from 180°C to 140°C (the hysteresis prevents rapid changing ofthis bit). When this bitis activated,the spindle logic will tristateboth high and low side driversto allow thedisk to coast and cooldown the chip.

1 UV Under Voltage=0, good voltage =1. This signals whether the under

voltage circuit has been activatedor not. NOTE: When UV=0,the POR is activated and allserial port controllogic is reset. This means that writes are impossible, however, the user can still poll the status ofthis registerprovided the logicvoltage is sufficient for the logicto function.

2 FLL_UP Providing mainly for testing. When the FLL is sourcing current into

the charge pump capacitor this isset to 1. A 0 means that the sourcing current isdisabled.

3 FLL_DOWN Providing mainly for testing. When the FLL is sinking current from

the charge pump capacitor this isset to 1. A 0 means that the

sourcing current isdisabled. 4 BEMF_SENSE Toggles with BEMF. 0 5 MASK_TIME Mask time currently in use = 1. When 1this means theBEMF

comparator will notsense the zero crossingat this time. A 0

means zero crossingsensing will occur. 6 DELAY Delay time currently in use = 1. e.g. A commutation delay isactive

and at theend of this delay the next commutation is executed. 7 AT_SPEED 1=spindle is at speed (set by the first ”down pulse”of the FLL.It is

reset at POR. 8 UNUSED 0 9 UNUSED 0

10 UNUSED 0 11 UNUSED 0

L6260

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