SGS Thomson Microelectronics L6258 Datasheet

®

PWM CONTROLLED - HIGH CURRENT

DMOS UNIVERSAL MOTOR DRIVER

ABLE TO DRIVE BOTH WI NDINGS OF A BI­POLAR STEPPER MOTO R OR TWO DC MO­TORS

OUTPUT CURRENT UP TO 1.5A EACH
WINDING

WIDE VOLTAGE RANGE : 12V TO 45V
FOUR QUADRANT CURRENT CONTROL,

IDEAL FOR MICROSTEPPING AND DC MO­TOR CONTROL

PRECISION PWM CONTR O L
NO NEED FOR RECIRCULATION DIODES
TTL/CMOS COMPATIBLE INPUTS
CROSS CONDUCTION PRO TECTION
THERMAL SHUTDOWN

DESCRIPTION

L6258 is a dual full bridge for motor control appli­cations realized in BCD technology, with the ca­pability of driving bot h windings of a bipolar step­per motor or bidirectionally control two DC
motors.

L6258 and a few external components form a

L6258

PRELIMINARY DATA

PowerSO36

ORDERING NUMBER:

complete control and drive circuit. It has high effi­ciency phase shift chopping that allows a very low
current ripple at the lowest current control levels,
and makes this device ideal for steppers as well
as for DC motors.
The power stage is a dual DMOS full bridge capa­ble of sustaining up to 45V, and includes the di­odes for current recirculation.
The output current capability is 1.5A per winding
in continuous mode, with peak start-up current up
to 2A.
A thermal protection circuitry disables the outputs
if the chip temperature exceeds the safe limits.

L6258

BLOCK DIAGRAM

C

C2

R

C2

VS

POWER
BRIDGE

1

+

C

-

+

-

BRIDGE

C

POWER

2

VBOOT

D96IN430D

OUT1A

OUT1B
SENSE1B

SENSE1A
DISABLE

VS

OUT2A

OUT2B
SENSE2B

SENSE2A

C

BOOT

R

s

R

s

1/18

INPUT

&

SENSE

AMP

INPUT

&

SENSE

AMP

EA_IN2 EA_OUT2VCP2

THERMAL

PROT.

EA_IN1 EA_OUT1GND

TRI_0

+

TRI_180

C1

TRI_0

TRI_180

C

-

+

C

-

ERROR

V

R

AMP

+

-

ERROR

V

R

AMP

+

-

R

C1

C

VDD(5V)

VCP1

VREF1

I3_1
I2_1
I1_1
I0_1

PH_1

VREF1

I3_2
I2_2
I1_2
I0_2

PH_2

TRI_CAP

C

FREF

C

P

CHARGE

PUMP

DAC

VR GEN

DAC

TRIANGLE

GENERATOR

VR (VDD/2)

TRI_0

TRI_180

April 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

L6258

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

Vs Supply Voltage 50 V

V

V

ref1/Vref2

I
I

V

V

boot

V

boot - Vs

T

T

CC

O
O

in

j

stg

Logic Supply Voltage 7 V
Reference Voltage 2.5 V
Output Current (peak) 2 A
Output Current (continuous) 1.5 A
Logic Input Voltage Range -0.3 to 7 V
Bootstrap Supply 60 V
Maximum Vgate applicable 15 V
Junction Temperature 150 °C
Storage Temperature Range -55 to 150 °C

PIN CONNECTION

(Top view)

PWR_GND

PH_1

I1_1
I0_1

OUT1A
DISABLE
TRI_CAP

V

CC

GND
VCP1
VCP2

VBOOT

VS

OUT2A

I0_2
I1_2

PH_2

PWR_GND

1
2

3
4
5
6
7
8
9

36
35

34
33
32
31
30
29

28
10 27
11
12

26

25
13 24
14
15
16
17
18

23

22

21

20

19

PWR_GND
SENSE1

OUT1B
I3_1
I2_1
VS
EA_OUT1
EA_IN1
VREF1
SIG_GND
VREF2
EA_IN2
EA_OUT2
I2_2
I3_2
OUT2B
SENSE2
PWR_GND

2/18

D96IN432E

PIN FUNCTIONS

Pin # Name Description

1, 36 PWR_GND Ground connection (1). They also conduct heat from die to printed circuit

2, 17 PH_1, PH_2 These TTL compatible logic inputs set the direction of current flow through

3I

4I

1_1

0_1

5 OUT1A Bridge output connection (1)
6 DISABLE Disables the bridges for additional safety during switching. When not

7 TRI_cap Triangular wave generation circuit capacitor. The value of this capacitor

8V

(5V) Supply Voltage Input for logic circuitry

CC

9 GND Power Ground connection of the internal charge pump circuit
10 V
11 V
12 V

13, 31 V

CP1
CP2
BOOT
S

14 OUT2A Bridge output connection (2)
15 I

16 I

0_2

1_2

18, 19 PWR_GND Ground connection. They also conduct heat from die to printed circuit copper
20, 35 SENSE2, SENSE1 Negative input of the transconductance input amplifier (2, 1)

21 OUT2B Bridge output connection and positive input of the tranconductance (2)
22 I
23 I

1_3
2_2

24 EA_OUT_2 Error amplifier output (2)
25 EA_IN_2 Negative input of error amplifier (2)

26, 28 V

REF2

, V

REF1

27 SIG_GND Signal ground connection
29 EA_IN_1 Negative input of error amplifier (1)
30 EA_OUT_1 Error amplifier output (1)
32 I
33 I

2_1
3_1

34 OUT1B Bridge output connection and positive input of the tranconductance (1)

Note: The number in parenthesis shows the relev ant Power Bridge of the circui t. Pins 18, 19, 1 and 36 are connected together.

copper.

the load. A high level causes current to flow from OUTPUT A to OUTPUT B.
Logic input of the internal DAC (1). The output voltage of the DAC is a

percentage of the Vref voltage applied according to the thruth table of page 7
See pin 3

connected the bridges are enabled

defines the output switching frequency

Charge pump oscillator output
Input for external charge pump capacitor
Overvoltage input for driving of the upper DMOS
Supply voltage input for output stage. They are shorted internally

Logic input of the internal DAC (2). The output voltage of the DAC is a
percentage of the VRef voltage applied according to the truth table of page 7

See pin 15

See pin 15
See pin 15

Reference voltages for the internal DACs, determining the output current
value. Output current also depends on the logic inputs of the DAC and on
the sensing resistor value

See pin 3
See pin 3

L6258

3/18

L6258

THERMAL DATA

Symbol Parameter Value Unit

R

th j-amb

R

th j-case

(*) Depending on board and soldering.

ELECTRICAL CHARACTERISTICS

S

= 42V; VCC = 5V; V

(V

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

S

V

CC

V

BOOT

V

Sense

V

S(off)

V

SH/VCC14

V

CC(off)

I

S(on)

I

S(off)

I

CC (OFF )

T

SD

∆T

SD-H

T

J

f

osc

TRANSISTORS

I

DSS

R

ds(on)

V

f

Thermal Resistance Junction Ambient 20 °C/W
Thermal Resistance Junction-case (*) 2.2 °C/W

boot

= 52V; Tj = 25°; unless otherwise specified.)

Supply Voltage 12 40 V
Logic Supply Voltage 4.75 5.25 V
Storage Voltage VS = 12 to 45V VS+6 VS+12 V
Max Drop Across Sense Resistor 1.25 V
Power on Reset Off Threshold 6 7.2 V
Power on Histeresys 0.3 V
Power on Reset Off Threshold 3.3 4.1 V
VS Quiescent Current Both bridges ON, No Load 15 mA
VS Quiescent Current Both bridges OFF 7 mA
VCC Operative Current DISABLE = LOW 7 mA
Shut Down Temperature 145 °C
Shut Down Hysteresis 25 °C
Thermal Shutdown 150 °C
Triangular Oscillator Frequency (*) C

= TBD 12.5 15 17.5 KHz

FREF

Leakage Current OFF State 500 µA
On Resistance ON State 0.6 0.75 Ω
Flywheel diode Voltage If =1.0A 1 1.4 V

CONTROL LOGIC

V

in(H)

V

in(L)

I

in

I

dis

V

ref1/ref2

I

ref

FI =

V

ref/Vsense

V

FS

V

offset

lnput Voltage All Inputs 2 V

CC

Input Voltage All Inputs 0 0.8 V
Input Current (Note 1) 0 < Vin < 5V -150 +10 µA
Disable Pin Input Current -10 +150 µA
Reference Voltage operating 0 2.5 V
V

Terminal Input Current V

ref

= 1.25 -2 5 µA

ref

PWM Loop Transfer Ratio 2

DAC Full Scale Precision Vref = 2.5V I0/I1/I2/I3 = L 123 134 mV
Current Loop Offset Vref = 2.5V I0/I1/I2/I3 = H -30 +30 mV
DAC Factor Ratio Normalized @ Full scale Value -2 +2 %

SENSE A MPLIFIER

V

cm

I

inp

lnput Common Mode Voltage

-0.7 VS+0.7 V

Range
Input Bias sense1/sense2 -200 0 µA

ERROR AMPLIFIER

G

V

SR Output Slew Rate Open Loop 0.2 V/µs

GBW Gain Bandwidth Product 400 kHz

Note 1: This is true for all the logic inputs except the disable input.
(*) Chopping frequency is twice fosc value.

Open Loop Voltage Gain 70 dB

V

4/18

L6258

FUNCTIONAL DESCRIPTION

The circuit is intended to drive both windings of a
bipolar stepper motor or two DC motors.

The current control is generated through a switch
mode regulation.

With this system the direction and the amplitude
of the load current are depending on the relation
of phase and duty c ycle bet ween the two outputs
of the current control loop.

The L6258 power stage is composed by power
DMOS in bridge configuration as it is shown in fig­ure 1, where the bridge outputs OUT_A and
OUT_B are driven to Vs with an high level at the
inputs IN_A and IN_B while are driven to gr ound
with a low level at the same inputs .

The zero current condition is obtained by driving
the two half bridge using signals IN_A and IN_B
with the same phase and 50% of duty cycle.

In this case the outputs of the two half bridges are
continuously switched between power supply (Vs)
and ground, but keeping the differential voltage
across the load equal to zero.

In figure 1A is shown the timing diagram of the
two outputs and the load current for this working
condition.

Following we consider positive the current flowing
into the load with a direction from OUT_A to
OUT_B, while we consider negative the current
flowing into load with a direction from OUT_B to
OUT_A.

Now just increasing the duty cycle of the IN_A
signal and decreasing the duty cycle of IN_B sig­nal we drive positive current into the load.

In this way the two outputs are not in phase, and
the current can flow into the load trough the di­agonal bridge formed by T1 and T4 when the out­put OUT_A is driven to Vs and the output OUT_B
is driven to ground, while there will be a c urrent
recirculation into the higher side of the bridge,
through T1 and T2, when both the outputs ar e at
Vs and a current recirculation into the lower side
of the bridge, through T3 and T4, when both the

outputs are connected to ground.
Since the voltage applied t o the load for recircula-

tion is low, the resulting current discharge time
constant is higher than the current charging time
constant during the period in which the current
flows into the load through the diagonal bridge
formed by T1 and T4. In this way the load current
will be positive with an average amplitude de­pending on the diff erence in dut y cycle of t he two
driving signals.

In figure 1B is shown the timing diagram in the
case of positive load current

On the contrary, if we want to drive negative cur­rent into the load is necessary to decrease the
duty cycle of the IN_A signal and increase the
duty cycle of the IN_B signal. In this way we ob­tain a phase shift between the two outputs such
to have current flowing into the diagonal bridge
formed by T2 and T3 when the output OUT_A is
driven to ground and output OUT_B is driven to
Vs, while we will have the same current recircula­tion conditions of the previous case when both
the outputs are driven to Vs or to ground.

So, in this case the load current will be negative
with an average amplitude always depending by
the difference in duty cycle of the two driving sig­nals.

In figure 1C is shown the timing diagram in the
case of negative load current .

Figure 2 shows the device block diagram of the
complete current control loop.

Reference Voltage

The voltage applied to V

pin is the reference

REF

for the internal DAC and, together with the sense
resistor value, defines the maximum current into
the motor winding according to the following rela­tion:
I

MAX

=

0.5 ⋅ V
R

S

REF

=

FI

V

1

REF

⋅

R

S

where Rs = sense resistor value

5/18

L6258

Figure 1.

Power Bridge Configuration

IN_A IN_B

OUTA

OUTB

V

S

T1

OUT_A OUT_B

T3

LOAD

T2

T4

Iload

OUTA

OUTB

Iload

OUTA

OUTB

Iload

Fig. 1A

0

Fig. 1B

0

Fig. 1C

0

D97IN624

6/18