SGS Thomson Microelectronics L6256 Datasheet

DESCRIPTION

The 12 Volt Combo chip is a combination spindle
motor driver, voice coil driver and D/A converter.
The part can be used in,application like HDD.

The VCM amplifiers drive a low impedance coil
and are set up to accept RC compensation, which
allows a wide bandwidth with absolute minimum
phase lag. The sense resistor/amplifier arrange­ment allows full current loop operation. The loop
gain is changeable by attenuating the VCM DAC
voltage amplitude in cascadable stages.

The Spindle driver is a PWM only voltage loop
with power supply feedforward, driving a 3 phase
sensorless brushless DC motor. Since it uses
PWM operation at full run speed, it has output
slew rate control during start and run modes.
There is an inductive clamp circuit to limit flyback
voltage transients across the supply voltage dur­ing motor phase changes and during the braking
sequence. Only the 2 phase or bipolar commuta­tion pattern is produced by the internal commuta­tion circuitry. A commutation register allows arbi-

Figure 1. Block Diagram

L6256

12V COMBO

PLCC44

ORDERING NUMBER:

trary winding sequencing during certain opera­tions. Internal protection against crossover
spikes is built in.

3 phase or tripolar commutation can be supported
in software during start by writing a commutation
pattern directly to the preload register.

Tripolar operation requires that more than two
phase drivers contribute current simultaneously.
The current limit circuitry reflects this and allows
33% higher current limit, which produces nearly

L6256

CP_OUT

CP_CAP

H_VPWR

VDD

VCC

nPOR

POR_RC

PARK

SCLK

SDIO

CSELB

BYPASSC

QDRIVE

VREG_IN

CUR_IN

December 1997

18

19

33

34

15

10

9

27

13

14

28

16

20

21

22

3.3V LINEAR
REGULATOR

6,7,17,29,39,40

CHARGE

PUMP

VPWR

2

UV

DETECT

POR

CLK

SYNC

SERIAL INTERFACE

3

ANALOG

TEST MUX

3

VCM

LOGIC

h_vpwr

BRAKE
DELAY

COUNTER

SH_
OUT

A_INI_VCIO_VC

BEMF SENSING

ZERO CROSSING

DETECTION

BEMF_

DET

DAC

VCM

COMMAND

10 BIT

DAC

8 11 36 37 5 38 12 35 44 4

R_

SLEW

CHANNEL

VCM CONTROL

BANDGAP

24

FEEDFORWARD
COMPENSATION

PWM_INPWM_DCFF_

VOLTAGE

REFERENCE

SPINDLE SEQUENCER

SYNC

CLAMP

COMP

VCM

RETRACT

CURRENT
SOURCES

SPINDLE LOGIC

SP_
CLK

THERMAL

upper

lower

PRE-DRIVERS

VCM CLASS AB

DRIVERS

-

+

A

AMP

CURRENT

LIMIT

SENSING

REF_

IN

A_OUT B_OUT

232530263132

PWR GND

SPINDLE DRIVERS

DYNAMIC

CLAMPING

SP_G2SP_

AMP

B

24

VC_PWR

-

+

h_vpwr

2

SP_P1

42

SP_P2

43

SP_A

1

SP_B

3

SP_C

41

C_TAP

D97IN571

G1

1/28

L6256

DESCRIPTION

(Continued)

constant torque. This is a very high power dissi­pation mode, meant only for momentary opera­tion in unusual circumstances.

Spindown during a power failure uses the back
EMF voltage generated by the spindle motor to
provide power to the VCM amplifier. The Spindle
motor coasts during the Brake Delay time to allow
time to park the head actuator. The park circuit is
a constant voltage circuit settable externally.

After the head is parked, braking commences.
The brake operates by shorting all 3 windings.

required to bring the motor to a complete stop,
even if no power is applied to the part.

A Power On Reset (POR) function provides pulse
stretching for the bidirectional POR\ bus, to en­sure that the processor and clocks are at running
speed before allowing them to function.

5 volt and 12 volt pins are used directly for the un­dervoltage detect circuit.

This allows direct use internally of both supplies.
Voltage monitor margining is supported.

An external 3.3V linear regulator is provided and
tied into the POR circuit.

The spindle output stages stay on as long as is

OPERATING CONDITIONS

= 4.5 to 5.5V

V

CC

= 10.8 to 13.2V

V

dd

0°C < T

amb

< 70°C.

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

PWR

V

PVR

V

dd

V

CC

I_VCM, Aout -2 to V

Logic I/O, SH_Out, PWM_DC -0.3 to V

All other pins -0.3 to V

T

stg

(1) Limited by chip clamp voltage.

Normal Operating Voltage 15 V
Inductive Clamp Voltage @ 2mH, 1.6A, 3% Duty Cycle <20 V (1)

Storage Ambient Temperature -65 to +150 °C
ESD capability

15 V

6.4 V
+2V

PWR

+0.3

CC

+0.3V

PWR

2kV

±

PIN CONNECTION

2/28

GND

R_SLEW

POR_RC

nPOR

PWM_IN

BEMF_DET

SCLK

SDIO

VCC

BYPASSC

5V_GND

7

8

9

10

11

12

13

14

15

16

17

SP_CLK

GND

CP_CAP

CP_OUT

SP_C

SP_G1

QDRIVE

VREG_IN

SP_B

SP_P1

123564

2322211918 20 28272624 25

B_OUT

CUR_IN

SP_G2

SP_A

A_OUT

VC_PWR

C_TAP

SP_P2

I_VC

PARK

GND

40414244 43

CSELB

39

38

37

36

35

34

33

32

31

30

29

GND

SH_OUT

FF_COMP

PWM_DC

REF_IN

VDD

H_VPWR

DAC

IO_VC

A_IN

GND

D97IN572

THERMAL DATA

Symbol Description Value Unit

R

th j-pins

R

th j-amb

(*) Mounted on board with minimized dissipating copper area.

Thermal Resistance Junction-pins
Thermal Resistance Junction-ambient (*)

Max.
Max.

12
50

PIN DESCRIPTION

Pin # Pin Name Pin Description Type

1 SP_B Spindle Output, Ph B Power/Output

2, 42 SP_P1, SP_P2 Spindle driver Supply Power/Input

3 SP_C Spindle Output, Ph C Power/Output

4,44 SP_G1,SP_G2 Spindle Driver Ground Power/Output

5 SP_CLK Spindle Clock Input Cmos/Input

6,7,29,39,40 GND Power Ground Ground/Heatsink

8 R_SLEW Spindle Slew/FeedFwd Osc. Freq. Analog/Input

9 POR_RC Ext. POR Timing Cap. Analog/Output

10 nPOR POR Reset (Active LOW) Cmos/BIO

11 PWM_IN Spindle PWM Input Cmos/Input

12 BEMF_DET Spindle BEMF Output Cmos/Output

13 SCLK Serial Data Clock Cmos/Input

14 SDIO Bidirectional Serial Data I/O Cmos/BIO

15 VCC 5V Digital Supply Supply/Input

16 BYPASSC Not to be used -

17 5V_GND 5V Supply Ground Ground/Output

18 CP_OUT Charge Pump Pumping Cap Analog/Output

19 CP_CAP Charge Reservoir Cap Analog/Input

20 QDRIVE 3.3V Regulator Base Drive Analog/Output

21 VREG_IN 3.3V Regulator Voltage Feedback Analog/IO

22 CUR_IN 3.3V Regulator Current Feedback Analog/IO

23 B_OUT VCM Driver Output, B Power/Output

24 VC_PWR VCM Drivers Supply Power/Input

25 A_OUT VCM Driver Output, A Power/Output

26 I_VC VCM Sense Amplifier Input Analog/Input

27 PARK VCM Park Pin Analog/Input

28 CSELB Chip Select -

30 A_IN VCM A-Amplifier Input Analog/Input

31 IO_VC VCM Sense Amplifier Output Analog/Output

32 DAC VCM DAC Command Output Analog/Output

33 H_VPWR VCM Vpwr/2 Reference Voltage Analog/Output

34 VDD 12V Analog Supply Supply/Input

35 REF_IN Spindle Current Limit/Win Threshd Analog/Input

36 PWM_DC Spindle Filtered PWM Input Analog/Input

37 FF_COMP Spindle Feedforwd Ramp Generator Analog/Input

38 SH_OUT Spindle BEMF Sample/Hold Analog/Output

41 C_TAP Spindle Centre Tap Analog/Input

43 SP_A Spindle Output, Ph A Power/Output

L6256

C/W

°

C/W

°

3/28

L6256

TYPICAL APPLICATION DIAGRAM

SP_CLK SP_C SP_B SP_A C_TAP

SP_C SP_B SP_A C_TAP

SP_CLK

5

33

H_VPWR

BEMF_DET

V

3.3V

C3

22µF

esr 0.5Ω

nPOR

PWM

SCLK

SDIO

CC

R

1.5Ω

S

+

V

-

R

SLEW

100KΩ

C2 47nF

R

PWM

33KΩ

RDIO 1.2KΩ

R

REF2

R

REF

62.5KΩ

Cbyp
10nF

R_SLEW

POR_RC

nPOR

PWM_IN

BEMF_DET

SCLK

SDIO

VCC

5V_GND

120KΩ

REF_IN

QDRIVE

CUR_IN

VREG_IN

BYPASSC

C

HVPWR

100nF

8

9

10

11

12

13

14

15

17

35

20

22

21

16

37

FF_COMP

SP_P1

C

ffc

470pF

SPINDLE

vpwr

C1

4.7µF

D4

33nF

51KΩ

p1

R

p2

100KΩ

R

sh

pwindc

25V

D5

D1

+

V

V

DD

-

R

b

4.3KΩ

R

a

1.5KΩ

R

fb

120KΩ

C

fb

390pF

R

SENSE

0.75Ω

I_VC

VCM

B_OUT

C

sh

3.3nF

C

dc

10nF

SP_P2

414313

SP_G2

42

6,7,29,39,40

GND

CSelB (from µP)

2

4

SP_G1

44

28

24

19

18

34

32

31

30

27

25

26

23

38

36

CSELB

VC_PWR

CP_CAP

CP_OUT

VDD

DAC

IO_VC

A_IN

PARK

A_OUT

I_VC

B_OUT

SH_OUT

PWM_DC

C

PCAP

2.2µF

35V

C

POUT

R

100KΩ

R
100KΩ

D97IN573

DESIGN FORMULAS:

1.

Spindle Run Mode Slew Rate:

1500 ⋅ 10

SR

=

2.

Feedforward Compensation:

Fpwm =

Dout =

=

V

ref

Vrslew =

Fpwm = PWM chopping frequency
Din = Input duty cycle at pwm_in
Dout = Spindle output duty cycle

4/28

Rslew

1

Tpwm

Tpwm

Tpwm

Rpwmdc

Rpwm

Vpwr

(

3

(Volts

=

Cffc

+ 0.7µs

⋅ 2.47 (V

0.8

+

1.86

/µs

)

(V

⋅

⋅

)

1

Rslew

Vref

Vrslew

)

)

(

Hz

⋅

Din

Vcc

3.

Current Limit: Ilimit = 20 ⋅ 10

4.

BEMF Zero Crossing Detector:

- Slope Compensation: Csh ⋅ Rsh =
Vbemf = Amplitude of bemf

3

(A

⋅

Rref

)

5.9683

Vbemf

⋅ N

(sec

)

N = Run mode speed of the motor in RPM

)

- Window width:

t

= 15404

win

5.

VCM PARKING VOLTAGE:

V

= 0.5

A,park

6.

3.3V REGULATOR:

Max Load Current: I

Vcc ⋅ Rref

⋅

Rref



1 +

⋅




Rref2

+

Rp2

Rp1





MAX

⋅ Vbemf ⋅ N

V

)

(

0.3

=

Rs

Polepair (µs

⋅

(A)

)

L6256

GENERAL BLOCK DESCRIPTIONS

(see figure 1)

Charge Pump

The Charge Pump provides bias for the upper driv­ers, for the brake circuit, and for internal circuitry as
required for normal and spindown operation. Slew
rate control is built in for quiet operation.

Serial Interface

The serial interface will transfer all control, status
and data to and from the processor. Internal test­ing provisions have also been made through this
port. The interface is compatible with an
8X196MP,NU or K17 series processor at low
speed only, due to internal limitations of the proc­essors. External chip select is mandatory on the
L6256. Chip Select is also used to reset and syn­chronize the serial port. The serial port is used to
indicate thermal shutdown of the Dolphin chip.

Brake Delay Timer

The brake delay will, upon start of a park or brake
sequence, delay 128 negative zero crossings of
the A spindle phase to allow the park circuit to op­erate. (The delay will typically be on the order of
400 msecs.) Then the braking sequence can be­gin. The output of this timer is provided to the se­rial port registers to indicate the start of the brake
action, and to indicate the start and end of the
park period.

Spindle Section

SPINDLE CURRENT LIMIT
The spindle current limit value in start mode is set

by the value of the external resistor on the Ref_In
pin during start (which at start is shorted to Vcc,
and the current out of the pin sets the current limit
value).

During run, various internal methods are used to
set a nominal maximum current value for circuit
protection only. Consult the data sheets and ap­plication notes for a description of this circuitry.

Current limit operates on a cycle by cycle basis.
The current limit comparator output is provided to
the serial port to indicate when the spindle is in
current limit. The current limit bit is reset when
the status register is read.

NOTE: Current limit operation involves chaotic
states, and careful firmware control can be used,
if desired, to prevent audible squels. Actual cur­rent limit value is also affected significantly by
motor inductance. See application notes.

COMMUTATION COUNTER (CCTR)
The Commutation Counter provides commutation

control for the spindle motor. It advances the
spindle phases according to the bipolar phase
control sequence, every time a SPIN_CLK posi­tive edge is received. Its reset state (B C\) is gov­erned by the Commutation Preload Register
(CPR). Operation of the register is synchronous
with SP_CLK, but the reset is asynchronous.

3.3V Regulator

The 3.3V external regulator provides a logic 3.3V
using an external pass element (N channel FET),
tied into the undervoltage detection system. It has
the following features:

●

Voltage mode control, using no external com­pensation.

●

3:1 foldback current limit to protect the pass
element in case of component failure.

●

Absolute regulation of 8% under all operating
conditions

Control Registers

See serial port section.

Internal Testing

This circuitry is per vendor’s specifications. No
test functions actuated by the serial port software
allow chip or drive damage to inadvertently occur.
Double level write enabling is used. Differing ven­dor test requirements are accomodated using the
unique vendor code bits. Various external pins
are used for this function; consult the manufac­turer’s data sheets.

COMMUTATION PRELOAD REGISTER (CPR)
During the initial start period, phase on/off control

is preloaded into the counters from the Commuta­tion Preload Register, which is loaded from the
serial port. This allows direct commutation con­trol from the processor. Various commutation
schemes are implemented during startup by soft­ware through this register. High side bits take
precedence over low side bits.

For both high and low drivers, logic high input to
this register turns on the respective driver. Any
pattern other than all 1’s holds the CCTR in reset,
and sets the MUX to bring data from the CPR
register for the drive pattern. An all 1’s pattern
(an illegal state) releases the CCTR reset and
switches the MUX to read the CCTR.

An all 0 pattern in the CPR spindle control bits
both tristates the spindle drivers and resets the
commutation counter.

The commutation latch holds data from either the
CPR or the CCTR depending on whether all 1’s
are loaded into the CPR. The latch loads the pre­vious state of the counter when the SP_CLK edge
comes in. The latch circuitry also provides chop
commutation information.

5/28

L6256

UPPER AND LOWER SPINDLE DRIVERS
The spindle drivers provide commutation

switches. Internal inductive flyback protection is
provided, dumping the energy into Vpwr node.
This protection network also provides the energy
transfer to the VCM to allow parking after power
is lost.

The high/low and low/high slew rate of the drivers
during run mode is controlled by the R_Slew pin
to ensure that cross conduction with the lower
drivers does not occur, and that excessive volt­age slew rates are not produced. Provisions are
made to drive inductive loads due to the possible
filtering requirements. Windings must be damped
with suitable external resistors to allow back EMF
to be detected through the chopping waveform.

INDUCTIVE CLAMP CIRCUIT
The inductive clamp is applied to the motor pins

to prevent the energy from the spindle motor coils
from producing excessive voltages on the part,
when the spindle drivers are tristated or when
commutation occurs.

Back Emf Detect

The back EMF voltage from the spindle motor is
monitored by a sample/hold circuit. First order
slope compensation, set by the value of Rsh and
Csh on the SH_Out pin, is used to reduce jitter.
Sampling will occur during the spindle PWM on
time, and hold during the off time and the
ON_DELAY time. Slope compensation must be
optimized for operation at run speed. During
startup, the zero crossings are detected from all
three phases. During run, only the falling edge of
phase A is useful for timing. A very small amount
of hysteresis is provided to prevent noise glitches.
A fixed offset of approximately

Vebias

millivolts is
internally introduced to the comparator during
start mode.

The inductive flyback pulse must be masked by
the width of the SP_CLK pulse provided by the
Western Digital controller chip. The width of this
pulse is affected by motor speed and current, as
well as inductance.

Additional back EMF conditioning circuitry is be­ing provided by Western Digital’s digital controller
chip. The back EMF_Det pin is masked for ap­proximately 1/4 of the expected commutation cy­cle, and is latched to prevent multiple transitions.

At power on reset, BEMF_Det is tristated to allow
for in circuit testing.

During run mode, the Ref_In pin sets a prequali­fier comparator voltage level, which enables the
zero crossing detection circuit about 20µs ahead
of the actual position. Once speed has been sta­bilized, the spindle phase advance is used to ad­just the EMF crossing to be coherent with the

PWM timing. This is done by observing the output
of the preqalifier comparator and comparing it
with the ON_DELAY signal internal to the chip.
This output comparison is provided through the
serial port.

Feedforward Compensation (FFWD Comp)

Any VPWR variations are nulled out by the ra­tiometric adjustment of the PWM duty cycle. This
circuit converts the fixed processor PWM fre­quency down to a frequency determined by the
R_Slew resistor and the FF_Comp capacitor.
This frequency is very constant over the entire
specified supply voltage range.

VCM Section

VCM DAC
The VCM DAC buffer brings the VCM_DAC out-

put up to the required drive capability. A 10 bit
monotonic DAC is provided for the VCM.

ATTENUATOR SWITCHES
These provide variable attenuators for the VCM

current control loop, settable from the control reg­ister. Attenuation settings are cascadable in bi­nary form, thus requiring 1 bit for each attenuator.
Ratios of 1.5:1, 2:1 and 4:1 give the additional
combinatorial gains of 3:1 (1.5*2), 6:1 (1.5*4), 8:1
(2*4) and 12:1 (all 3 attenuators on simultane­ously). Attenuator gain ratios are not precisely
controlled relative to one another and differ
slightly between manufacturers.

An overall attenuator enable bit has been added
to the VCM_DAC register address field. If this bit
is a 1 (Combo compatible mode), then the attenu­ators are enabled. If the bit is a 0, then full gain is
requested. This enables the VCM_DAC write to
accomplish a complete gain shift and DAC write
in a single serial port operation (2 bytes).

LEVEL SHIFT
The level shift circuitry shifts the center voltage of

the VCM current command up to approximately
half of the supply voltage, to provide for symmet­ric operation of the VCM power amplifiers.

The reference voltage output is a high impedance
input point of approximately

Rref

ohms to allow

for external bypassing.

VCM AMPLIFIERS
The VCM amplifiers are complementary class AB

output amplifiers, with Bout having higher gain
than the Aout amplifier. This ensures uniform
saturation in either direction.

6/28

SATURATED SEEK BIT
The processor can command the VCM amplifiers

to hard saturate, in the polarity determined by the
sign bit of the DAC. The saturation detector bit is
not the echo of this bit, but is a separate compa­rator bit representing the true state of the ampli­fier. Thus, it can be used for loopback testing of
the DOLPHIN.

VCM CURRENT SENSE AMPLIFIER
The input differential voltage of the amplifier can

be limited to low voltage, but common mode re­jection is very high. The amplifier is capable of
operating smoothly when the VCM amplifiers are
saturated, providing no input charge buildup or
other anomalies. Charge does not build up on
the inputs even when VCM inductance forces the
inputs substantially above the supply or below
ground.

SATURATION DETECTOR
This detector notifies the processor when the

commanded VCM current does not match the ac­tual VCM current. The threshold is set by
VC_Sat.

L6256

●

An interlock circuit which provides for dis­charge of the one shot, and a clamp to hold
the POR\ line low during the timing interval.

●

Circuitry to pull POR\ high quickly after the 1
shot has timed out.

●

A current source or weak pullup to pull the
POR\ line high against external leakage cur­rents.

Undervoltage conditions override external inputs
and force POR\ low. External inputs do not cause
pulse stretching; all internal inputs do.

PCBA in-circuit testing can arbitrarily pull this line
low as necessary to restart the system. Alter­nately, a 1 milliamp current can be introduced to
the timing capacitor to speed up the POR timeout.

THERMAL LIMIT
The thermal limit of the chip is set for

THhyst

relative voltage, above

degrees of hysteresis. Thermal limit is a

Thwarn

sons, and must protect the part; it indicates that
thermal limit is taking place by disabling the serial
port (see serial port section). A park and a spin­dle driver tristate is performed when thermal limit
occurs.

THlimit

with

for tolerance rea-

Fault Detection

UV DETECTION
The power supply undervoltage protection is set

up for the appropriate tolerances, and causes a
low signal on POR\. A small hysteresis is in­cluded on the voltage comparators, and band­width limiting techniques are used. Current limit
from the 3.3V regulator has been added to the
POR error inputs.

POWER ON RESET (see appendix B)
The power on reset circuit provides the following

functions:

●

A retriggerable one shot of several millisec­onds.

THERMAL WARNING
Thermal warning is made available to the proces-

sor as a status bit in every register, to allow a
modified control algorithm strategy that reduces
power dissipation and drops chip temperature.

PARK CIRCUIT
The park circuit provides smooth head retraction.

In Park, the VCM is switched to voltage mode.

Bout

is grounded. The A amplifier’s positive in­put is switched from the normal half supply refer­ence down to

Vpark

age determined by

Vpark

, and

Aout

applies the volt-

Rp1

and

and

Rp2

. This
damps any motion that may been in progress and
causes the head to retract into the latch.

7/28

L6256

Figure 2:

Spindle State Diagram.

POWER

UP

CPR*

CPR

BRAKE

CPR

START

NO SLEW

3ph EMF

CPR

limit

POR

SPINDLE

Z

(defaults)

START*
SP_EN*

SP_CLK

CPR=1's*

SP_CLK

START

CCTR

No Slew

3ph EMF

limit

START*

SP_CLK

D97IN585

UV

POR

RUN

SLEW

1ph EMF

CCTR

No limit

SP_CLK*

SP_EN*
START*

REG BRAKE

SP_EN

POR

REG BRAKE

UV

THSHUT

THWARN

UV

BRAKE

FAULT

TRISTATE

THERMAL
TRISTATE

BRAKE
DELAY

NOTE: In the spindle state diagram, in transitioning from Start mode to Brake, the CPR register is shown
as being one possible path. The CPR register can be used to command a brake, which then causes the
outputs to brake. This is called CPR Brake mode. However, a true brake state does not really occur.
Specifically, current limit is still active.

NOTE: START and SP_EN bits and CPR is rewritten to get out of Spindle Z state. SP_EN must be
pulsed.

NOTE: All spindle state transitions require an SP_CLK edge.

Figure 3:

VCM section state diagram.

POWER

ON

GROUNDED

VCM_TRISTATE

VCM

VC_EN

VC_EN

(FAULT)= POR or UV or TH_LIMIT

TRISTATE

DELAY

DAC

VCM

ACTIVE

REG PARK

REG PARK

REG BRAKE

(DONE=1)

SP_ENB

FAULT

D97IN586

REGISTER

PARK

FAULT

FAULT

PARK

BRAKE
DELAY

NOTE: VC_EN must be rewritten to get out of VCM Grounded state.
NOTE: At start, the spindle and VCM can now be simultaneously enabled. This is a VERY HIGH
POWER DISSIPATION mode. If this is done, be sure to use the SAT_SK bit and duty cycle the
VCM to keep chip power dissipation at a reasonable level.

8/28

L6256

ELECTRICAL CHARACTERISTICS
Power On Reset Section

POR SPECIFICATIONS

Specification Parameter Required Value

Vcc max undervoltage detect trip point, Vuv 4.06 to 4.3
Vcc trip point hysteresis 1%
Vdd undervoltage detect trip point Vuvd 9.3 to 9.8 volts
Vdd trip point hysteresis 1%
Max POR\ delay timing 100 msecs
Forcing current to reset POR_RC (for in circuit test only) nominal 1 milliamp
AC UV detection - nondetectable pulse Tuvmin (1) 1 µsec
AC UV detection - detectable pulse Tuvmax (1) 20 µsecs

(1) AC detection test: done on either supply. With either supply at 0.2 volts above the trip point, a 1.2 volt negative pulse is applied.
Chip must not respond to pulse width of Tuvmin, and must respond to Tuvmax.

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

min

Required VCC or Vdd for valid
POR\@25°C (7)

V

tcap

V

cth

T

strech

T

% POR\ pulse tolerance

tol

T

pmin acc

Timing Cap timeout threshold 2/3 V
Timing Cap threshold (10)
POR\ pulse strech width 5 40 100 ms (5)

external POR\ input required
pulse width

V

lw

Voltage measurement point for
Tpmin

I

weak

Pullup Current, POR\, steady

100

state (at 3V)

T

rise

Rise time on POR\, internal
driver with 100pF load (2)

I

pullup

Pullup Current, POR\,

3.2 mA

momentary

Notes

:
(1) dVmarg% The margining limit is determined as a fraction of the actual chip margin circuitry.
(2) hysteresis on POR\ is optional.
Load: POR\ will see approximately 90 pF plus an external pullup source of approximately 6k ohms. No external bulk capacitance is used
on POR\.
(3) fall time measured from 2 volts to 0.8 volts.
(4) pulse width measured from Vporint volts on falling edge to 1.6 volts on rising edge.
(5) is capable of meeting this timing with a 0.1µF or less, 20% tolerance ceramic capacitor. Nominal design point, .047µF is 40 ms ±20%.
(6) Timing tolerance on POR pulse width irrespective of external parts.
(7) POR\ is valid if either Vcc or Vdd exceeds this voltage.
(8,9) Tpmin acc is the minimum POR\ pulse width which the combo must recognize as a valid external POR. This corresponds to the width of
the reset pulse from the processor. Pulse widths narrower than this may or may not be recognized. Tpmin rej is the value of pulse width
above which the combo should not recognize a pulse.
(10) V
in order to prevent deadly embrace with the microprocessor. The specified value is needed with 3.3V logic circuitry.

is caused by the transition between the external POR circuit and the internal POR clamp circuitry.

bounce

1.3 2.0 V

CC

20% (6)

±

300 ns (9)

0.8 V

µ

100 ns

V

A

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