Datasheet L6245 Datasheet (SGS Thomson Microelectronics)

L6245

5V HARD DISK DRIVE POWER COMBO

PRODUCT PREVIEW

General

+5V OPERATION
REGISTERBASEDARCHITECTURE
MINIMUMEXTERNALCOMPONENTS
SLEEP AND IDLE MODES FOR LOW

POWERCONSUMPTION
SELECTABLE GAINS FOR BOTH VCM AND

SPINDLEGm LOOP
LINEAR CURRENT CONTROL LOOPS FOR

BOTH VCM AND SPINDLE
8 BIT D/A FOR ACTUATOR DRIVER AND

SPINDLEDRIVER

VCM Driver

CURRENT SENSE CONTROL (VOLTAGE
PROPORTIONALTO CURRENT)

VOLTAGE SENSE CONTROL (VOLTAGE
PROPORTIONAL TO THE VOLTAGE
ACROSSTHE VCM)

TWO CURRENT RANGES FOR SEEKING
ANDTRACKING

INTERNAL REGISTER FOR POWER AMP
CONTROLLINES

SPEED OUTPUT (VOLTAGE PROPOR­TIONALTO BEMF)

Spindle Driver

BEMF PROCESSING FOR SENSORLESS
MOTORCOMMUTATION

PROGRAMMABLE COMMUTATION PHASE
DELAY

PROGRAMMABLE SLEW-RATE FOR RE­DUCEDEMI

0.7Ω TYP. FOR ANY HALF BRIDGE
CROSS CONDUCTION PROTECTION
SYNTHESIZEDHALL OUTPUT

OtherFunctions

POWER UP SEQUENCING
POWER DOWN SEQUENCING
LOW VOLTAGE SENSE
ACTUATOR RETRACTION
DYNAMICBRAKE
THERMAL SHUTDOWN

MULTIPOWERBCD TECHNOLOGY

PQFP64

ORDERING NUMBER: L6245

DESCRIPTION

The L6245 contains in a single chip all the func­tions to operate a sensorlessbrushless (DC) mo­tor and a voice coil motor, suitable for hard disk
drive applications.
The device is configured to interface directly to
an 8 bit parallel microprocessor bus, and has a
register based architecture to reduce number of
interconnection lines. All the positioning loop for
sensorless spindle is integrated, including BEMF
sensing, digital masking, digital delay and se­quencing. All timing function are performed digi­tally, thus no external filtering componentsare re­quired.
The VCM driver is a transconductanceamplifier,
able to provide2 differentcurrentranges, suitable
for seeking or tracking of the head actuator.
When a low voltage is detected, a monitor, in se­quence, resets the internal registers, puts in tris­tate the spindle powers, retractsthe actuator, and
appliesthe dynamic brake ofthe spindle.
The L6245 is realized in Multipower-BCD 2 tech­nology, which combine isolate DMOS power tran­sistors with CMOS and Bipolar circuits in the
same monolithic layer, and is assembled in a 64­pin PQFP.

October 1992

This is advanced information on a new product now indevelopment or undergoing evaluation. Details are subject to change without notice.

1/15

L6245

BLOCK DIAGRAM

2/15

PIN CONNECTION (Top view)

L6245

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

ds sus

; Vcc Supply Voltage Power (VP)

V

P

V

V

I
I

P

T

stg,Tj

Peak Output SustainingVoltage 14 V

8

Logic(V

Logic input Voltage 0 to 6 V

i

Charge Pump Input Voltage 18 V

cp

Sink-Source Peak Output Current 1.5 A

p

Sink-Source DC OutputCurrent 1 A

O

Total Power Dissipation (T

tot

=60°C) 1 W

amb

CC

)

6

Storage and Junction Temperature –40 to 150 °C

THERMAL DATA

Symbol Parameter Value Unit

R

thj-amb

(*) Mounted on a typical PCB layout (see Fig. 7)

Thermal Resistance Junction-ambient (*) max. 90 °C/W

V
V

3/15

L6245

PIN DESCRIPTION [Pin Types:I =Input, O =Output, P =Power, A= Analog (passive)]
Power

Pin Number Pin Name Pin Type Description

12, 17

24,

3

7, 42, 64 GND P Ground.

10 V
59 POR 0 POWER ON RESET - Goes lowwhen the supplyvoltage is below the

61 POR_DLY A POR DELAY. An external parallel RC networkfrom thispin to ground

62 POR_FILT A An external capacitor from this pinto ground provides filtering for the

5 CPC A Charge pump capacitor
6 CPL A Charge pump inductor

VPOWER

VDIG

V

CC

REF

MicroprocessorInterface

Pin Number Pin Name Pin Type Description

25
26
27
28
29
30
31
32

38 RD I READ A low level on thispin allows the busto be driven by the IC.
39 WR I A low level on WRITE allows the ICto read data from thesystem bus.
35 MC_CS I CHIP SELECT A low level on this pin selects the IC for bus

41 SYSCLK I Microprocessor clock used forinternal timing.
33

34
35

37 AS I ADDRESS STROBE The address appearing on A [0:2] is latchedon

43 MC_ERR O A maskable interrupt signal which isasserted low when anerror flag in

40 DTACK O An open drain, activelow signal used for asynchronousbus

D7
D6
D5
D4
D3
D2
D1
D0

A0
A1
A2

P Positive supply, nominally 5V.

I All analog signals are referenced to thisvoltage, nominally 2V.

VOLTAGE GOOD threshold.POR is anopen collector output with an
internal 20kΩ pull-up.

sets the time thePOR signal staysactive after voltage good.

V

sense inputof the POR circuit.

CC

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I
I
I

An 8-bit bidirectional databus which is connected to the internal
registers.

transactions.

The lowest three bits of thesystem addressbus; used to address
internal registers

the falling edge of the AS pulse.

the Status Registeris set. The output is open-drain with an internal
20KΩ pull-up.

transactions.

Brushless,SensorlessMotor Driver and 8 bit D/A

Pin Number Pin Name Pin Type Description

47 SPIN_DAC O The output ofan 8 bit D/A used for the command to thespindle driver.
48 SPIN_CMD I The input to the spindledriver transconductance amplifier.
45 COIL_CT I The center tap of the motor is connected to this pin.

O The motor coilsare drivenby these outputs. Back EMF isalso sensed

at these pins.

4/15

53
57
60

COIL_U
COIL_V

COIL_W

PIN DESCRIPTION (continued)

Pin Number Pin Name Pin Type Description

44 SYNTH_HALL O A TTL compatible signal thatemulates one ofthe Hall signals.

SYNTH_HALL is an opendrain output with an internal20KΩ pull-up.

49, 50,

58

SPIN SENSE

1,2,3

A The current sensing resistors is connectedfrom these pinsto ground.

46 PWM_OFFT A A parallelR-C from thispin to ground sets the PWM mode OFF time.
56 SLEW A A resistor from thispin to ground setsthe slew rate of the driver.
51 S_COMP A An R-C network from this pin to GND setsthe spin driver

compensation.

VCM Driver and8 bit D/A

Pin Number Pin Name Pin Type Description

8 VCM_DAC O The output of an 8 bit D/A usedto command the VCM driver.

9 VCM_CMD I VCM driver input command which is relativeto V
21 VCM_COMP A An R-C network from this pin to ground compensates theVCM driver.
14 VCM_RS1 A The highgain current sense resistor is attached from this pin to ground.
23 VCM_RS2 A The low gain current sense resistor isconnected from this pin to

VCM_RS1
13 VCM+ O One end ofthe load is attached to this pin (Positive).
15 VCM- O The other end of the load is attached to this pin (Negative).
20 OV_VOLT O A voltagewhich is proportional to the voltage across the load,

referenced to V

REF

.

19 OV_CUR O A voltagewhich is proportional to the current through the load,

referenced to V

REF

.
16 OV_SUM– I Over-velocity summing op-amp inverting input.
18 OV_SUM_OUT O Over-velocity summing op-amp output.

REF

.

L6245

22 ISENSE O A voltagewhich is proportional to the current through the VCM load as

sensed by thesense resistor. This signal isenabled bysetting bit 2 in
the VCM ControlRegister.

54 VCM_STRB I The 8 bitinput to the VCM D/A is updated on therising edge of

VCM_STRB.

SolenoidPre-drivers and Power Down Sequencing

Pin Number Pin Name Pin Type Description

11,55,

63

2 LOAD_SOL O When a logic one is writtento bit 3 ofthe VCM Control Register,

1 UNLOAD_SOL O When alogic one is writtento bit 4 of the VCM Control Register,

4 PD_SEQ_CAP A When power is removed, the chargestored on thiscapacitor keeps

52 BRK_DLY A An external parallel RC network from thispoint toground delays

V_RECIR P Under normal conditions, power is supplied to variousblocks via the

V_RECIR pin. When externalpower is removed, energy stored in the
rotating spindle is converted toa voltage which suppliesthe park circuit.

current is sourced from the LOAD_SOL pin. Otherwise, the pin is high
impedance.

current is sourced from the UNLOAD_SOL pin. Otherwise, the pin is
high impedance.

selected blocks alive long enough toeffect an orderlypower down.

activation of the dynamic brake after power is removed.

5/15

L6245

ELECTRICALCHARACTERISTICS (VS= 5V, Tj=25°C; unlessotherwisespecified)
PowerSupply Characteristics

Symbol Parameter Test Condition Min. Typ. Max. Units

V

S

ID-READY

Supply Voltage VS=VP=V
Quiescent Current Dissipation No load attached VCM andSpin

ID_IDLE

ID_SLEEP

VCM Driver (Notes1, 2)

CC

drivers enab.
VCM driver disabled Spin driver
enabled
VCM and Spin driversdisabled

4.5 5.5 V
25

20

4

mA
mA
mA

I

OS

Maximum Load Current

Output Devices A, B, E, F (Fig. 1) 0.3 A

(Seeking)

I

OT

Maximum Load Current

Output Devices C, D (Fig. 1) 0.1 A

(Traking)

R

R

DS(on)

DS(on)

Source & Sink OutON
Resistance

Output Devices A, B, E, F
T

= 125°C (Fig. 1)

j

Sink Out On Resistance Output Devices C, D

1 Ω

2.4 Ω

Tj = 125°C (Fig.1)

R

DS(on)

V

F

V

jump

V

DB

V

CMOS

(*) The range of input voltages applied tothe VCM_CMD pin (with respectto V
deadband voltage (VDB) canbe expressed either in mV or in LSBs, where one LSBis equal to11.7mV.

(**) A condition in which the transfer characteristic (i.e., load current vs. VCM_CMD-V
desired value. The range of currents for which this condition exists is termed IJUMP. This current is referred o the VCM_CMD inputaccording
to the following equation: VJUMP = IJUMP x 3 x RSENSE
In this document, RSENSEis assumed to be2.01Ω. VJUMP can be expressed either in mV or in LSBs, where one LSBis equal to11.7mV.

(***) The value of VCM_CMD (with respect to V
offset is defined to be at the midpoint of the deadband region. RSENSE is assumed to br 2.01Ω.

VCM Current sense amplifier(I

V

off

Sink Out On Resistance Parking Device Tj = 125°C12Ω
Body Diode Forward Drop I = 0.3A 1.5 V
Jump Discontinuity (**) R
Deadband Discontinuity (*) R
Offset (***) R

) for which the load current is zero. In parts which exihibit a DEADBAND dicontinuity, the

REF

)

SENSE

Output Offset Voltage VCM_RS2 Shorted to GND O/Sis

= 2.01Ω 30 mV

sense

= 2.01Ω 6mV

sense

= 2.01Ω 40 mV

sense

) for which only negligible current is presentin the load. This

REF

) exhibits a slope which is significantly graterthan the

REF

–50 50 mV

V

(Isense)-Vref

G Closed Loop Voltage Gain 3V/V nominal 2.85 3.15 V/V

PSRR Power Supply RejectionRatio at DC 50 dB

BW Banwwidth 200 KHz
V

OR

Output Range VCC= 4.5V (note 4) –0.2 3.5 V

VCM Full waverectifying amplifier

I

B

I

imp

G Closed Loop Gain 0.320 0.347 V/V

PSRR Power Supply RejectionRatio at DC 50 dB

GBW Unity Gain Bandwidth 200 KHz
CMR Input Common ModeRange VCM_CMD pin 0.3 3.7 V

V

OR

6/15

Input Bias Current VCM_CMD = V

ref

Input Impedance Impedance seen at VCM_CMD

wrtV

ref

5KΩ

2 µA

Output Range 0 1 V

ELECTRICALCHARACTERISTICS (Continued)
VCM DAC (Notes5, 6)

Symbol Parameter Test Condition Min. Typ. Max. Units

Res Resolution 8 bit
N.L. Differential Nonlinearity ±0.5 LSB

I.N.L. Integral Nonlinearity ±0.5 LSB

CT Conversion Time From 50% pointof WR fallingto

2 µs

1% settling

Z

O

Output Z 100 Ω

FSTC Full Scale Temp. Coeff. 200 ppm/°C

V

OH

V

OL

V

ZSO

High Output Voltage Relative to V
Low OutputVoltage Relative to Vref Input Code = 80h –1.53 –1.47 V
Zero Scale Offset Relative to V

Input Code = 7Fh 1.46 1.52 V

ref

Input Code = 00 ±10 mV

ref

Over velocity detector,coil voltage sense amplifier

Symbol Parameter Test Condition Min. Typ. Max. Units

V

O

Output Offset Voltage VCM+ = VCM–, within input

common mode range.
Measure wrt to V

I

BC

Input Bias Current (Note 3) 10 µA

ref

G Closed Loop Voltage Gain Av = 0.25V/V nominal 0.242 0.258 V/V

PSRR Power Supply RejectionRatio at DC 50 dB

BW Bandwidth 200 KHz

CMR Input Common ModeRange Above and below these values

the op amp will be in saturation
and will not invert sign.

V

DR

V

OR

I

O

Input Differential Range 0 V
Output Range 0.3 3.5 V
Output Current æ400 µA

–50 +50 mV

0V

POWER

POWER

L6245

V

V

Over velocity detector,coil currentsense amplifier

Symbol Parameter Test Condition Min. Typ. Max. Units

V

O

Output Offset Voltage VCM_RS1 shorted to GND for:

(a) VCM_CMD < V
b) VCM_CMD > V
V

ref

and

ref

. Measure wrt

ref

G Closed Loop Voltage Gain Av = 2.5V/V nominal 2.425 2.575 V/V

PSRR Power Supply RejectionRatio at DC 50 dB

Bw Bandwidth 200 KHz

CMR Input Common ModeRange –0.1 2 V

V

R

I

O

Output Range 0.5 3.5 V
Output Current +400 mA

–50 +50 mV

7/15

L6245

ELECTRICALCHARACTERISTICS (Continued)
Over velocity detector,summingamplifier

Symbol Parameter Test Condition Min. Typ. Max. Units

V

O

I

BC

G Open Loop Gain 60 dB

PSRR Power Supply RejectionRatio at DC 50 dB

GBW Unity Gain Bandwidth 200 KHz

V

R

I

O

Over velocity detector,window comparator

Symbol Parameter Test Condition Min. Typ. Max. Units

t

S

V

TL

V

TH

Solenoidpre-driver (Note 7)

Symbol Parameter Test Condition Min. Typ. Max. Units

I

OH

Three phase sensorless motor driver

Input Offset Voltage 10 mV
Input Bias Current 1 µA

Output Range 0.5 3.5 V
Output Current +400 µA

Switching Time 50 µs
Low Threshold Relative to V

ref

–1.32 –1.18 V

High Threshold Relative to Vref 1.18 1.32 V

Output Current VOH= 1.5V, VCC= 4.4V 10 mA

Symbol Parameter Test Condition Min. Typ. Max. Units

Max. Load Current 0.5 A
Out OnResistance Tj= 125°C 0.75 Ω

R

I

O

DS(on)

dV/dt Slew Rate 0.05 V/µs

V

F

Body Diode Forward Drop I = 0.5A 1.2 V

Motor Current Sense Amplifier

Symbol Parameter Test Condition Min. Typ. Max. Units

I

BC

G Closed Loop Voltage Gain Low Gain mode

Input Bias Current 1 µA

High Gain mode

19.4

4.85

20.6

5.15

PSRR Power Supply RejectionRate at DC 50 dB

BW Bandwidth 200 KHz

I

O

Output Range 0 3.2 V

Spin DAC (Notes8, 9)

Symbol Parameter Test Condition Min. Typ. Max. Units

Res Resolution 8 bit

NL Differential Nonlinearity ±0.5 LSB

INL Integral Nonlinearity ±0.5 LSB

CT Conversion Time From 50% pointof –WR falling to

1% settling

Zo Output Z 14 KΩ

FSTC Full Scale Temp. Coeff. 200 ppm/°C

V

OH

V

OL

High Output Voltage 2.85 3.15 V
Low OutputVoltage Unloaded 0 20 mV

5 µs

V/V
V/V

8/15

ELECTRICALCHARACTERISTICS (Continued)
Step-upconverter

Symbol Parameter Test Condition Min. Typ. Max. Units

V

SU

Step-up Voltage Relative to V

CC

711V

Microprocessorinterface (Note 10)

Symbol Parameter Test Condition Min. Typ. Max. Units

V

IH

V

IL

V

OH

V

OL1

High Level Input Voltage 3 V
Low Level Input Voltage 0.8 V
High Level Output Voltage VCC = 5V, IOH= 400µA 4.4 V
Low Level Output Voltage –MCERR, –POR, –DTACK

0.4 V

IOL = 4mA

V

OL2

Low Level Output Voltage SYNT_ALL

0.4 V

IOL = 0.5mA

I

IN1

Input Leakage Current –RD, –WR, AS, –MC_CS,

1 µA

SYSCLK, A [0:2]

I

IN2

Input Leakage Current D [0:7] 10 µA

Microprocessorinterface timing

Trddh Read Data Hold 5 40 ns

Trddt –RD High to –DTACK high 40 ns

Twrdt –WR High to –DTACK High 40 ns

Power on reset

L6245

V

CCHL

V

CCHL

T

PLH

R

T

Notes:

1) The minimum voltage available from thebrushless DC motor after power has beenremoved is 2.7V

2) The voltage available for actuator etraction shall be greater than 0.7V.

3) Sum of I

4) Minimum output voltage is set to V

5) The VCM DAC shallbe monotonic over its full range.

6) The coding of thedigital input shall be 2’s complement.

7) The voltage available for solenoid operation shall be greater than 1.9V.

8) The Spin DAC shall be monotonicover its full range.

9) The coding of thedigital input shall be uniplar (unsigned binary).

10) SYNTH_HALL, MC_ERR, DTACKand POR shall have open drain (collector) outputs and internal pull-up resistors. The minimum value of
these pull-up resistors shall be 20KΩ..

FUNCTIONAL DESCRIPTION

Inside the systemis the sensorlessSpindle driver
(Spin), the Voice Coil Motor driver (VCM), the
Head load/unload predrivers, power sequencing,
actuator over-velocity detection, actuator retrac­tion and dynamicbraking. The architecture of the
system is configured to interface directly to an 8
bit, parallel, microprocessorbus.

During the application of power to the system
(power-on),the outputdriversareheldin a disabled
state until the appliedvoltage reaches the Voltage
Good Threshold (VGT). During this period of time
the output driversare disabled,the internalregister
are set to predeterminedstates,and the Power On

VCCGood, HL VCCfalling 4.2 4.4 V
VCCGood, LH VCCrising 4.26 4.5 V
Rise Time C

= 100pF 200 ns

Load

Response Time 50 µs

/internal resistor + power leakage).

bias+(Vref

bya resistor network.

ref

Reset(POR) signal is held low. The PORsignal is
held low from the time the applied voltage
reaches 0.7V and the VGT. The POR delay is
programmable changing the value of a capacitor.

The VCM driver is drivenvia a D/Aand it can be
enabled through the VCM driver register. The
VCM driver has a gain capability too. This func­tion is to be accomplishedby switchingthe sense
resistor used such that the current sensing feed­back in the VCMdriver has more information and
therefore results in lower deadband, offset cur­rent, and gain error. An actuator over velocity
sensing circuit is incorporated in the system,
which is accomplished by measuring BEMF volt­age and comparingto a threshold.

9/15

L6245

The head load /unload mechanisms are just buff­ers for driving external power transistors. Control­led internally by Bit 3 andBit 4 of the VCM Driver
Register,each output has a current surcing capa­bility of 10mA.

The Sensorless Spindle Driver function can be
accessed from the microprocessor over the data
bus to the Spin Register and Spin D/A. The Spin
D/A is in Binary format.The operationof the Spin­dle system is controlled entirely by the microproc­essor from start-up to speed regulaton. The spin
systemis accessibleby selecting the Spin Control
Register with the address 011 on the 3 bit ad­dressbus andhas thefollowing functions:

1)Enable(Bit 0): high to enable the spin sys­tem, while a low asserts braking of the
spindle motor (if VCRenable is low.)

2)Sense amplifier gain (Bit 1): high implies
high current mode which is equivalentto
low sense amp gain, while a low selects
low current mode or high sense amp
gain.

3)Unipolar/Bipolar (Bit 2): High selects the
Unipolardriving mode.

4)Run/Search Mode (Bit 3): high selects the
run mode whereby the Hall synthesizer
output gives speed information while a low
asserts the search mode whereby the se­quencer is under µP control (stepper func­tion).

5)Reset State (Bit 4): a low level resets the
commutationstate sequencer.

6)Incrementalstate (Bit 5): toggling of the bit
increments the sequencer to drive the
output stage when search mode is se­lected.

7)Linear/PWM (Bit 6): high selects linear
mode of driving for current (speed) regu­lation while a low sets to PWM mode used
during start-up.

Start-up current limiting is accomplished by the
output of the microprocessor commanded D/A
value. Jammed or stuck rotor detection is also
done as part of the microprocessor algorithm. In­tegrated diode are present in the power bridge for
BEMF rectification. This rectified voltage is used
to retract the actuator and unload or latch the
head assembly.

A conventional Bandgap is used to generate in­ternal biasing for the device as well as the refer­encevoltage for theD/A converters.

A Step-up Converter is used to generate a 15V
internal supply to drive the upper DMOSs and a
regulated 11.6V internal supply to power internal
circuits which have voltage head room problem,
aswell as to drive the lowerDMOSs.

A Low Voltage Detector (LVD) is incorporated to
sense a severely low value of applied voltage so
as to shunt-down the VCM and Spindle drivers.
The LVD is activated when the applied voltage
drops below 4.3V (+/-0.1V). When a voltage drop
issensed, the LVD:

1.assertsPOR,whichresetstheinternalregister;

2. retractsthe actuator;

3.applies thedynamic brake.
When a severe low value of applied voltage is

sensed, the motor control system goes into reset
mode and also asserts the POR line to reset
other circuits. The sub-circuit which get affected
bythe reset mode in the motor control system are
the Spin Control Register, the VCM Driver Regis­ter, the Spindle D/A and the VCM D/A. This effec­tively disables the spin driver, VCM driver, head
load/unloaddriver and initializes the D/A’s at zero
output command value.

An Over Velocity Detector circuit is integrated to
sense when head arms are moving at a speed
which could cause a damaging condition. When
an over velocity condition is detected sensing the
actuatorBEMF, the actuator driver is shut off and
held off until the microprocessorhas detectedthis
conditionand then resets the error and retries the
access.

The microprocessor has the possibility to put the
device in sleep mode, which is asserted when
both the VCM and Spindle drivers are disabled
through the internal registers (Enable VCM and
Enable Spindle). Under this condition, only the
POR circuit is kept ”alive”, thus power consump­tion is kept at minimal. Before sleepmode is acti­vated, the microprocessor must move the actua­tor to the unload zone, unload the recording
heads, andapply dynamicbraking.

All bits of all the registersare readable by the mi­croprocessorinterface. Also there are certainbits
of the internal registers which are writable as de­fined in the Register Definition Tables (Tables 1 -

7).
An internal register monitors the internal work of

the system and latchescertain error condition that
aredetected.

10/15

L6245

REGISTERDEFINITIONand3bit AddressCode
Table 1: Status Register (A.C.001)

Bit Name

NC

7

NC

6

NC

5

NC

4

REVERSE SPIN

3

OVER TEMP.

2

SPIN SENSE

1

OVER VEL SET

0

POR Initial

Value

1
1
0
1

Table 2: VCMDriver Register(A.C. 010)

Bit Name

NC

7

NC

6

NC

5

UNLOAD HD

4

LOAD HD

3

ENABLE ISENSE

2

HIGH GAIN VCM

1

ENABLE VCM

0

POR Initial

Value

0
0
0
0
0

Table 5: Spin D/ARegister (A.C. 101)

Bit Name

Most SignificantBit

7
6
5
4
3
2
1
0

Least Significant Bit

POR Initial

Value

0
0
0
0
0
0
0
0

Table 6: InterruptMask Register(A.C. 110)

Bit Name

NC

7

NC

6

NC

5

NC

4

NC

3

MASK REVSpin

2

MASKOVERTEMPERROR

1

MASK OVERVEL ERROR

0

POR Initial

Value

0
0
0

Table 3: Spin Control Register (A.C. 011)

Bit Name

NC

7

LINEAR/PWM

6

INCREMENT STATE

5

RESET STATE

4

RUN/SEARCH

3

UNI/BI

2

HIGH GAIN SPIN

1

ENABLE Spin

0

POR Initial

Value

Table 4: VCM D/A Register (A.C.100)

Bit Name

Most Significant Bit

7
6
5
4
3
2
1
0

Least Significant Bit

POR Initial

Value

Table 7: PhaseDelay Register (A.C. 111)

Bit Name

NC

7

NC

0
0
0
0
0
0
0
0

6

NC

5

NC

4

Most SignificantBit

3
2
1

Least Significant Bit

0

POR Initial

Value

0
0
0
0

SYSTEMBUS DESCRIPTION

The system bus is designed as a data acknow­ledge handshanking bus. At the beginning of the
bus cycle the address and chip select are de­coded transparently and qualified with read or
write going low. On a read operation, data must

0
0
0
0
0
0
0
0

not be driven for 5nsec after read goes low to al­low the bus to clear. Once datais driven,data ac­knowledge is driven low to notify the processor
that data is on the bus and ready to be read. The
processorreads thedata and respondsby raising
read. This is an indication that the processor has
compleated the read and cycle is complete. Data
acknowledge and data must go to high im­pedence within 20ns to clear the bus for the next

11/15

L6245

cycle. On a write operation, following write going
low and whatever setup time required to latch
data, data acknwledgeis driven low. This notifies
the processorthat thecycle canend. Thisproces­sor responds by raising write, indicating the end
of the cycle. Data acknowledge must go to high
impedance within 20nsec to clear the bus for the
next cycle.

This handshaking design allows a peripheral to
controlthe lengthof the buscycle. The peripheral

Figure1: SystemBus Timing(see Table 8)

can take as much time as it needs to drive data
onto the bus, then drive DTACK low. Likewise,
the peripheral can wait as long as it needs to set
up data and latch it (or set up data if WRis used
to latch), then drive DTACK low. However, per­formance is an issue, so even though this control
has been given to the peripheral, it must not be
abused. All delays are minimized to assure opti­mum system speed, infact the bus can be driven
synchronously(E.G. has regarding DTACK) when
procesorclocks below 12MHz are used.

Table 8: System Bus Timing

Symbol Description

TAS Address SetupTime (nonMUX bus; (MUX bus)

TCS System Selectto Address Strobe

TASW Address StrobeWidth
TASRD Address Strobeto RD
TRDDV RD to Data Driven

TRDDH Read Data Hold

TRDCS RD High to CS High
TDVDT Data Valid toDTACK
TDTRD DTACK to RD High
TRDDT RD Highto DTACH High

TASWR Address Strobeto WR

TDVWR Write Data Validto WR

TWRDTL WR to DTACK

TDTWR DTACK toWR High

TWRCS WR High to CS High

TWRDT WR Highto DTACKHigh

TWRDH Write Data Hold

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L6245

THERMAL CHARACTERISTICS

On the application, the L6245 must be soldered
on a PCB system. The Traks Area, dependingon
the lenght and the width of each track, must be
between 2 to 10 square mm. An area of 10 mm
can give a typ. Thermal Resistance Junction-to­Ambient value of 85°C/W (See Fig. 2): this value
refer3 to a Total Power Dissipated Power of 1W.

Figure2: TypicalR

vs. Tracks Area on PCB

th j-amb

Fig. 9 shows the increase of the Rth j-amb when
the Dissipated Power decreases.
Practically, very useful information is the change
of the thermal resistance (Thermal Impedance)

2

versusa singlepulse of powerwidth or versusthe
time the dissipationbegins.
Fig.4 showsthis Thermal Impedancetrend.

Figure3: TypicalJunction-to-AmbientThermal

Resistancevs. Total Dissipated
Power.(L6245 mounted on atypical
PCB)

Figure4: TypicalTransientThermal Impedance

vs. Time orPulse Width.(L6245
mountedon a typical PCB)

13/15

L6245

PQFP64PACKAGE MECHANICAL DATA

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 3.40 0.134
A1 0.25 0.010
A2 2.55 2.80 3.05 0.100 0.110 0.120

B 0.30 0.45 0.0118 0.0177

C 0.13 0.23 0.005 0.009

D 16.95 17.20 17.45 0.667 0.677 0.687
D1 13.90 14.00 14.10 0.547 0.551 0.555
D3 12.00 0.472

e 0.80 0.0315

E 16.95 17.20 17.45 0.667 0.677 0.687
E1 13.90 14.00 14.10 0.547 0.551 0.555
E3 12.00 0.472

K 0°(min.), 7°(max.)

L 0.65 0.80 0.95 0.026 0.0315 0.0374

L1 1.60 0.063

D

D1

PQFP64

3348

32

E3D3E1

17

16

E

L1

L

K

0.10mm

Seating Plane

49

B

64

1

e

A1

A

A2

B

C

14/15

L6245

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor forany infringement of patents or otherrights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men­tioned in this publication are subject to change withoutnotice. This publication supersedes and replaces all informationpreviously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex­press written approval of SGS-THOMSON Microelectronics.

 1994 SGS-THOMSON Microelectronics - All RightsReserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

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