SGS Thomson Microelectronics L6238SQT, L6238SQA, L6238S Datasheet

12V SENSORLESS SPINDLE MOTOR CONTROLLER

12V OPERATION 3A,THREE-PHASEDMOS OUTPUT

(TOTALR NOHALLSENSORSREQUIRED DIGITALBEMFPROCESSING LINEAROR PWM CONTROL STANDALONE OR EXT. DRIVER SHOOT-THROUGHPROTECTION THERMALSHUTDOWN

dson

0.52Ω)

L6238S

PRODUCT PREVIEW

PLCC44

PQFP44

DESCRIPTION

The L6238S is a Three-Phase, D.C. Brushless Spindle MotorDriver system. This device features boththe Powerand SequenceSections.

Higher Power Applications can be activied with the additionof an external Linear Driver,or by operatingthe InternalDrivers in PWM.

Motor Start-Up, without the use of Hall Sensors, can be achieved either by an internal start-up algorithm or by manually sequencing the Output Drivers, using a variety of User-Defined Start-UP Algorithms.

BLOCKDIAGRAM

VANALOG

SYS CLOCK

SEQ INCR

MONO/SEQ

CTRL

TDLY(0) TDLY(1) TDLY(2)

MASK DLY

BIAS

SYSTEM

CLOCK

DIGITAL

DELAY

FALIGN

MONO

DET

OUTPUT ENABLE

ALIGN + GO

START-UP

RUN/

BRAKE

SEQUENCER

ZERO CROSSING DETECTOR

TQFP64

ORDERING NUMBERS: L6238S (PLCC44)

L6238SQA (PQFP44) L6238SQT (TQFP64)

Protection features include Stuck Rotor\Backward Rotation Detection and Automatic Thermal Shutdown.

PWM

LIN

BEMF

SENSE

PWM

COMP

+ + +

TIM

CHARGE

POWER

STAGE

PUMP

CPUMP1 CPUMP2 CPUMP3

VPOWER

BRAKE DELAY

OUT A OUT B OUT C

CTR TAP

PWM/ SLEW

ONE-SHOT

SLEW-CTRL

RSENSE1 RSENSE2

GND

CSA INPUT

1/31

OT-WARN

October 1995

SPIN

SENSE

TOGGLE

THERMAL

SHUTDOWM

DIVIDE

BY N

FMTRSEL POL

VCTRL

DRV

CNTL

GATE DRIVEGM COMP

AV=4V/V

CSA

D95IN232

This isadvanced information on a new product now in development or undergoing evaluation. Details are subject to changewithout notice.

L6238S

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

dss

Power

Logic

Analog

storage

mdc

mpk

tot

Ts Storage and Junction Temperature -40 to 150 °C

THERMALDATA

Symbol Parameter PLCC44 PQFP44 TQFP64 Unit

th (j-amb)

Those Thermal Data arevalid if the package is mounted on Mlayer board in stillair

Output Brakdown Voltage 17 V Motor Supply Voltage 15 V Logic Supply Voltage 7 V Analog Supply Voltage 15 V Input Voltage -0.3 to 7 V Charge Pump Storage Capacitor 4.7 µF Motor Current (DC) (TQFP64 only)

(PLCC44 and PQFP44)

2.5 Peak Motor Current (Pulsed: Ton= 5ms, d.c. = 10%) 5 A Power Dissipation at Tamb = 50 °C(PLCC44)

(TQFP64) (PQFP44)

2.3

1.7

1.3

Thermal Resistance Junction-Ambient 34 45 45 °C/W

A A

W W W

PIN CONNECTION PLCC44 (Topview)

GND

N.C.

GND

8 9 10 11 12 13 14 15 16 17

CHARGE PUMP 1 CHARGE PUMP 3

OUTPUT A

VPOWER

VANALOG

TDLY(0) TDLY(1) TDLY(2)

CHARGE PUMP 2

GND

OTWARN

SELECT POLE

BRAKE DELAY

RSENSE 1

PWM/LINEAR

PWM LIMIT TMR

OUTPUT B

SPIN SENSE

123564

2322211918 20 28272624 25

RUN/BRAKE

OUTPUT ENABLE

VPOWER

PWM/SLEW

CENTER TAP

SYSTEM CLOCK

SEQ. INCREMENT

MONO/SEQINC CTRL

GND

MASK DELAY

40414244 43

FALIGN

PWM COMP

39 38 37 36 35 34 33 32 31 30 29

GND GATE DRIVE GM COMP OUTPUT C RSENSE 2 CSA INPUT VCONTROL N.C. FMOTOR VLOGIC GND

D95IN245

2/31

PIN CONNECTION PQFP44 (10x10)(Top view)

TDLY(2)

GND

TDLY(1)

OTWARN

SELECT POLE

PWM LIMIT TIMER

PWM/LINEAR

OUTPUT ENABLE

RUN/BRAKE

SEQ. INCREMENT

SYSTEM CLOCK

MONO/SEQINC CTRL

FALING

PWM COMP.

12 13 14 15 16

18 19 20 21 22

GND

VLOGIC

FMOTOR

N.C.

TDLY(0)

N.C.

VCONTROL

VANALOG

VPOWER

2827262423 25 33323129 30

RSENSE 2

CSA INPUT

OUTPUT A

OUTPUT C

CHARGE PUMP 1

CHARGE PUMP 3

GM COMP

GATE DRIVE

GND

123564789101711

44 43 42 41 40 39 38 37 36 35 34

GND

L6238S

GND CHARGE PUMP2 RSENSE 1 BRAKE DELAY SPIN SENSE OUTPUT B PWM/SLEW CENTER TAP VPOWER MASK/DELAY GND

D95IN243

PIN CONNECTION TQFP64 (Topview)

GND

N.C.

GND

19 20 21 22 23

25 26 27 28 29 30 31 32

GND

OTWARN

SELECT POLE

PWM LIMIT TMR

PWM/LINEAR

OUTPUT ENABLE

RUN/BRAKE

SEQ. INCREMENT

SYSTEM CLOCK

MONO/SEQINC CTRL

FALIGN

PWM COMP

GND

TDLY(1)

TDLY(2)

VLOGIC

FMOTOR

VANALOG

TDLY(0)

1213141516

37363433 35

CSA INPUT

VCONTROL

VPOWER

RSENSE 2

N.C.

OUTPUT A

4342413938 40 48474644 45

OUTPUT C

CHARGE PUMP 3

GM COMP

CHARGE PUMP 1

GATE DRIVE

GND

123564789102411

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

GND

GND GND CHARGE PUMP 2 RSENSE 1 RSENSE 1 BRAKE DELAY SPIN SENSE OUTPUT B OUTPUT B PWM/SLEW CENTER TAP VPOWER VPOWER MASK DELAY GND GND

D95IN244

3/31

L6238S

PIN FUNCTIONS

PLCC44 PQFP44 TQFP64 Name I/O Function

1 39 56, 57 OUTPUT B I/O DMOS Half Bridge Output and Input B for Bemf sensing. 2 40 58 SPIN SENSE O Toggless at each Zero Crossing of the Bemf. 3 41 59 BRAKE DELAY I Energy Recovery time constant, definedby external R-C to ground. 4 42 60, 61 R

sense 1

5 43 62 CHARGE

PUMP 2

6, 7,

17, 29,

39, 40

1, 11,

23, 33,

34, 44

* GROUND S Ground terminals.

8 2 4 CHARGEPUMP1 I Positive terminal of Pump Capacitor. 9 3 5 CHARGEPUMP3 O Positive terminal of Storage Capacitor.

10 4 6, 7 OUTPUT A I/O DMOS Half BridgeOutput and Input A for Bemf sensing.

11, 42 5, 36 9, 10,

power

52, 53

12 6 11 V

13, 32 7, 26 8, 18,

analog

N.C N.C Open Terminal

19, 31,

41 14 8 12 Tdly(0) I Three bits that set theDelay between the detection of the Bemf 15 9 13 Tdly(1) I 16 10 14 Tdly(2) I 18 12 20 OTWARN O Overtemperature Warning Output 19 13 21 SELECT POLE I Selects # of Motor Poles. A zero selects 8, while a one selects 4

20 14 22 PWM TIMER I Capacitor connected to this pin sets the maximum time allowed

21 15 23 PWM/LINEAR I Selects PWM or Linear Output Current Control 22 16 24 OUTPUT

ENABLE

23 17 25 SEQUENCE I Rising edge will initiate start-up. A Brakingrountine is started

24 18 26 SEQ

INCREMENT 25 19 27 SYSTEM CLK I Clock Frequency for the system timer/counters. 26 20 28 MONO/SEQ.

INC. CONTROL

27 21 29 Falign I Reference Frequency for the opt. Auto-Start Algorithm. If int.

28 22 30 PWM COMP O Output of the PWM Comparator 30 24 35 Vlogic S 5V Logic Supply Voltage. 31 25 36 Fmotor O Motor Once-per-Revolution signal. 33 27 37 Vcontrol I Voltage at this input controlshe Motor Current 34 28 38 CSA INPUT I Input to the Current Sense Amplifier. 35 29 39, 40 Rsense 2 O Output C connection forthe Motor Current SenseResistor to

36 30 42, 43 OUTPUT C I/O DMOS Half Bridge Output and Input C for Bemf sensing.

37 31 44 gm COMP I A series RC network to ground that defines the compensation of

O Outputs A+B connections for the Motor Current Sense Resistor

to ground

I Negative Terminal of Pump Capacitor.

S Power Section Supply Terminal.

S 12V supply.

zero crossing, and the commutation of the next Phase.

poles.

for 100% duty cycle during PWM operation

I Tristates Power Output Stage when a logic zero.

when this input is brought low.

I A lowto high transition on thispin increments the Output State

Sequencer.

I A logicone will disable the Monotonicity Detectorand Sequence

Increment functions.

start up is not used, this pin must be connected to the System Clock.

ground.

the Transconductance Loop.

4/31

PIN FUNCTIONS

PLCC44 PQFP44 TQFP64 Name I/O Function

38 32 45 GATE DRIVER I/O Drivers the Ext. PFET Gate Driver for Higher Power applications.

This pin must be grounded if anexternal driver is not used. 41 35 51 MASK/DELAY O Internal Logic Signals used forproduction Testing 43 37 54 CENTER TAP I Motor Center Tap used for differentialBEMF sensing. 44 38 55 PWM/SLEW I R/C at this input set the LinearSlew Rate and PWM OFF-Time

L6238S

Figure1: BrakeDelay TimeoutvsC

(s)

3.0

1.0

0.3

0.0

0.0 0.3 1.0 3.0 Cb(µF)

Figure3: PWM Off - Time vs R

brake

=1Meg)

slew/Coff

brake

D95IN274

Figure 2: LinearSlew Rate vs R

slew

(V/µs)

3.0

1.0

0.3

0.0 10 30 100 300 Rs(KΩ)

Figure 4: PWMLimit Time - Out vsC

D95IN275

timer

PWM

(µs)

D95IN276

100 300 Coff(pF)

PWM

(µs)

100 300 Ctimer(pF)

D95IN277

5/31

L6238S

ELECTRICAL CHARACTERISTICS (T

=0to70°C; VA=V

amb

Pwr

= 12V; V

= 5V; unless otherwise

logic

specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

GENERAL

analog

logic

Analog Supply Voltage 10.5 13.5 V Analog Supply Current Run Mode VA= 13.5V 1.5 2.7 4.5 mA

Brake Mode V

= 13.5V 280 800 µA

Logic Supply Voltage 4.5 5.0 5.5 V Logic Supply Current Run Mode V

= 5.5V 1 2 3.2 mA

logic

Brake Mode 100 500 1000 µA

THERMAL SHUTDOWN

hys

Shut Down Temperature 150 180 °C Recovery Temperature

30 °C

Hysteresis Early Warning Temperature Tsd-25 °C

POWERSTAGE

DS(on)

o(leak)

dVo/dt Output Slew Rate (Linear) R

Gate-Drive

Ctrl-Range

in(VCtrl)

PWM OFF-TIME CONTROLLER (R

off

chrg

trip

Output ON Resistance per FET Tj=25°C; VA= 10.5V

= 125°C; VA= 10.5V

Output Leakage Current V

= 15V 1 mA

pwr

0.20 0.26

0.40

Body Diode Forward Drop Im= 2.0A 1.5 V

= 100KΩ 0.15 0.30 0.45 V/µs

slew

Output Slew Rate (PWM) 10 150 V/µs Gate Drive for Ext. Power

DMOS

V V

control A

= 1V; V

= 10.5V

sns

= 0V;

4.5 mA

Ext Driver Disable Voltage 0.7 V Voltage Control Input Range 0 5.0 V Voltage Control Input Current 10 µA

= 100KΩ,C

slew

= 120pF)

off

OFF Time 9 11 14 µs Capacitor Charge Voltage VA= 10.5V 2.31 2.65 3.1 V Lower Trip Threshold 1.25 V

Ω Ω

PWM LIMITTIMER

chrg

trip

Capacitor Charge Current V

PWM Timer

= 0V; VA= 10.5V 10.0 20.0 30 µA Capacitor Charge Voltage VA= 10.5V 3.0 3.5 4.0 mV Lower Trip Threshold 100 400 V

BEMF AMPLIFIER

inCT

Bemf

Center Tap Imput Impedance 20 30 40 KΩ Minimum Bemf (Pk-Pk) 60 mV

CURRENT SENSE AMPLIFIER

snsin

SR Slew Rate 0.33 0.8 V/µs

6/31

Input Bias Current VA= 13.5V 10 µA Voltage Gain 3.8 4.0 4.2 V/V

ELECTRICALCHARACTERISTICS (Continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

BRAKEDELAY

chrg

out3

Thres

Capacitor Charge Voltage RT= 50K 8.8 9.6 10.5 V Input Current Vin= 5.0V 500 nA Source Current VA= 10.5V 0.5 mA Delay Timer Low TripThreshold 1.2 1.8 2.8 V

CHARGEPUMP

out

brkdly

brake

Storage Capacitor Output

VA= 10.5V; I

= 500µA17 V

out

Voltage Charge Pump Frequency 140 450 KHz Vstorage Input Current (Run

storage

= 12V; VA=V

=0 25 µA

logic

Mode) Vstorage Leakage Current

storage

= 12V; VA=V

= 0 0.4 1 µA

logic

(Brake Delay Mode) Vstorage Leakage Current

storage

= 12V; VA=V

= 0 0.1 1 µA

logic

(Brake Mode)

SEQUENCEINCREMENT

seq

Time Between Rising Edges 1 µs

OUTPUT TRANSCONDUCTANCE AMPLIFIER Note:Measure at OTA Comp. pin.

outL

source

sink

Voltage Output High VA= 10.5V 10 V Output Voltage 2.0 V Output Voltage 40.0 0.5 V Output Sink Current 40.0 µA

L6238S

LOGICSECTION

inH

inL

inH

inL

inH

inL

outL

inL

sys

off/ton

Input Voltage (All Inputs

Except Run/Brake Run/Brake Input Voltage V

Input Current

Output Voltage Vsink = 2.0mA

V System Clock Frequency 8.0 12.0 MHz Clock ON/OFF Time 20 ns

Phase DelayTruth Table

Tdelay (2) Tdelay (1) Tdelay (0)

1 0 1 2.0 1 0 0 9.4 1 1 1 18.80 1 1 0 20.68 0 0 1 22.56 0 0 0 24,44 (*) 0 1 1 26.32 0 1 0 28.20

(*) Input Default

= 4.5 to 5.5V 3.5

logic

= 4.5 to 5.5V 2.0

logic

= 2.0mA 4.5

source

1.5

1.0

1.0 µA

-1.0

0.5 V

Commutation Phase Delay,

in Electrical Degrees

V V

7/31

L6238S

FUNCTIONAL DESCRIPTION

1.0 INTRODUCTION

1.1 Typical Application

In a typical application,the L6238Swill operatein conjunction with the L6244 Voice Coil Driver as

Figure1-1

27K

10K

0.1µF

3.6K

SENSE V

Vpower

GATE

POR

VCM

SENSE +INPUT

SENSE -INPUT

OUT A

458

44 9 37

DRIVE

43 35

LOGIC

data(0)20data(1)21data(2)22data(3)23data(4)24data(5)25data(6)26data(7)

shown in Fig. 1-1. This configurationrequires a minimum amount of external components.

1.2 Input Default States

Figure 1-2 depicts the two possible input structures for the logic inputs. If a particular pin is not

360K

10K

GAIN1-IN

ERROR

AMP OUTPUT

36WR28A027A118

100K

GAIN2-IN

DA0Out

314 31 33

6,7,17,29,39,40

GND

POR DLY

CC/2

PROG

CP2CP1

PUMP

D95IN278

Rprogram

0.01µF

1µF

0.068µF

360K

Rs 0.4

OUT

DA2

SENSE OUT

OUT B

L6244

VOICE COIL DRIVER

8/31

12V

60-90Hz

Note: If the internal Start-up

Algorithm is not used,

VLOGIC(5V)

connect this pinto SYS_CLK

MONO

GATE

22µF

LOGIC

SEQ.

DRV

ANLG

PWR

ALIGN

OUT ENA

38 26

12 39

27 11,42

OUT A

CTRL

RUN/BRK

CTR TAP

SEQ INC

OUT B

MTR

OUT C

OT WARM

L6238S

CONTROLLER

DLY(0)TDLY(1)TDLY(2)

SPINDLE MOTOR DRIVER

4.35

346.33

CSA

RSENSE

CHRG PUMP 2

10nF

PWM

TMR

6,7,17,

CHRG PUMP 1

29,39,40

GND

BRK

PWM

CHRG

25 9

SYS CLK

DLY

COMP

SLEW

PUMP 3

10K

4.7µF

220pF

0.1µF

0.068µF

100K

400pF

8.12MHz

L6238S

Figure1-2

LOGIC

10µA

330

PULL-UP PULL-DOWN

D95IN279

LOGIC

330

10µA

used in an application, it may either be connected to ground or VLOGICas required, It may also be simplyleft unconnected.

If no connection is made, the pin is either pulled high or low by internal constant current generatorsas shownabove.

A listing of the logic and clock inputs is shown in Table1 with the correspondingdefault state.

Table 1

Pin Function Configuration

Tdly (0,1,2) Pull-Down Select Pole Pull-Down

PWM/Linear Pull-Down

Output Enable Pull-Down

Run/Brake Pull-Up

Sequence Increment Pull-Down

System Clock Pull-Up

Faling Pull-Up

1.3 Modes ofOperation

Thereare 5 basicmodes of operation.

1) Tristate When Output Enable is low, the output power

driversare tristated.

2) Start-Up With Output Enable high, bringing Run/Brake

from a low to a high will energize the motor and the system will be driven by the Fully-Integrated StartUpAlgorithm. A user-defined Start-Up Algorithm, under control of a MicroProcessor,can also be achieved via the sequenceincrementinput.

3) Run Run mode is achieved when the motor speed

(controlled by the external microprocessor)

reaches the nominalspeed.

4) Park When Run/Brake is brought low, energy to park

the heads may be derivedfrom the rectified Bemf. The energy recovery time is a function of the Brake Delay Time Constant. In this state, the quiescent current of the device is minimized (sleep mode).

5) Brake After the Energy Recovery Time-Out, the device

is in Brake, with all lower Drivers in full conduction.

There are two mutually exclusive conditions which may be present during the Tristate Mode (wake up):

a)the spindleis stopped. b)the system is still running at a speed that

allows for resynchronization.

In order to minimize the ramp up time, the microcontrollerhas thepossibility to:

check the SPIN SENSE pin, (which toggles at the Bemf zerocrossing frequency)

enable the power to the motor based on the previous information.Otherwise the µP may issue a Brake command, followed by the startup procedureafter the motorhas stoppedspinning.

2.0 STATEDIAGRAMS

2.1 StateDiagram

Figure 2-1 is a complete State Diagram of the controllerdepicting the operationalflow asa function of the control pins and motor status. The flow can be separatedinto fourdistinct operations.

2.2 Align + Go

Figure 2-2 represent the normal flow that will achieve a spin-up of the spindle motor using the internallygenerated start up algorithm.

Upon power up, or from any state with Run/Brake low the controller first sets the state machine for State=1with the Outputs Tristated.

The period counter that monitors the time between zero crossing is stopped, analog with the phase and maskdelay counters.

When Run/Brake is brought high, the motor is in the firstpart of the align mode at State 2 (Output A high and Output C low). If Output Enable is high, thecontrollerfirst checks to determine if the motor is still spinning for a time of 21Ω (with Sys_Clk = 10MHz). The drivers are now enabled and after the align time-out, (64/Falign), the sequencer double increments the outputsto State 4 (Output B high and Output A low). The first part of this align mode is used to reduce the effectsof stiction

9/31

L6238S

Figure2-1

RUN/BRK=0

DRIVERS OFF

OUTENA=1

DRIVERS OFF STATE=STATE+1 MIN CLOCK DELAY LOAD MIN DELAY LOAD MAX MASK DELAY COUNT STATE=STATE+1 MASK COUNT

DRIVERS OFF MIN CLOCK DELAY PERIOD STOP

OUTENA=0

SYS_CLK

OUTENA=0

RUN/BRAKE=0 FROM ANY STATE

STATE=STATE+2

DRIVERS ON PERIOD STOP DELAY STOP MASK STOP

STATE=STATE+2

STATE=STATE+1 LOAD DELAY=MIN LOAD MASK=MAX PERIOD COUNT DELAY COUNT STATE=STATE+1 MASK COUNT

SYS_CLK

64/FALIGN

192/FALIGN

POR=0 FROM ANY STATE (FOR IS GENERATED INTERNALLY BY MONITORING VLOGIC)

STATE= 1 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP DELAY STOP MASK STOP

RUN/BRAKE=1

DRIVERS OFF MIN CLOCK DELAY LOAD MIN MASK*** PERIOD STOP DELAY COUNT STATE=STATE+1 MASK COUNT

OUTENA=1

CHECK FOR ZcBEMF

SYS_CLK

RUN/BRK=0

DRIVERS OFF

BEMF

SEQLNC=1 & OUTENA=0 RUN/BRK=X

OUTENA=1

BEMF

RUN

MODE

BEMF

LOAD DELAY=MIN LOAD MASK=MIN RESET PERIOD PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT

MONO=0**

DRIVERS ON LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT

INT. START-UP DISABLED MIN. CLOCK DELAY LOAD MIN. DELAY LOAD MIN. MASK***

BEMF

LOAD MIN. DELAY LOAD MIN. MASK*** DELAY COUNT STATE=STATE+1 MASK COUNT

BEMF

RUN/BRK=1 & OUTENA=1

STATE=STATE+1* MASK COUNT

SEQINC=1

FROM ANY STATE WITH SEQ_INC=0

OUTENA=1

OUTENA=0

DRIVERS ON PERIOD COUNT DELAY COUNT

SEQINC=0 SEQINC=1

BEMF BEMFSEQINC=0 SEQINC=1

LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT**

STATE=STATE+1

* VALID IF SEQINC=0, AND DELAY TIMES OUT ** CLOCK DELAY=F(TDLY_[2:0])

WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED >12.7Hz FOR 8 POLES)

BEMFOUTENA=1

DRIVERS OFF MIN CLOCK DELAY PERIOD STOP

MASK COUNT

RETURN TO

PREVIOUS STATE

(CHANGING SEQINC=1)

ALIGN & GO MODE

* CLOCK DELAY=F(TDLY [2:0] WHENBEMF PERIOD <3.3ms@ 10MHz (SPEED>12.7Hz FOR 8 POLES) BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0 BEMF1: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1 **MONO=0 WHEN FREQ(BEMF)=2*FREQ(PHASE) ***MIN MASK=192/SYS_CLK(I.E. WITH SYS_CLK=10MHz,MIN MASK=19.2µs)

BEMF

After the next align time-out 192/Falign), the controller enters the Go mode, were the sequencer again double increments the output phase upon detectionof themotor’s Bemf.

The align time-outmay be optimized for the application by changing the Faling reference frequency.

A Watch-Dog Timer protection feature is built into the control logic to monitor the Falign pin for a clockingsignal. This circuitry, shown in Figure2-3 will prevent start up the device if the Falign clock isnot present.

10/31

RESYNCHRONIZATION MODE

D95IN280

Without this feature, the output would remain in the first phase under high current conditions, if the clockwere not present. If the external sequencer is used to provide start up, thesystem clock may be tied to the Falign pin to satisfy the requirements of the Watch-Dog Timer.

2.3 Resynchronization

If power is momentarily lost, the sequencer can automatically resynchronize to the monitored

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