SGS Thomson Microelectronics L6000 Datasheet

SINGLECHIP READ & WRITE CHA NNEL

SUPPORTS 9-32Mbit/s DATA RATE OPERA­TION INRLL [1,7] CONSTRAINT

- Data Rate is Programmable
SUPPORTS ZONED BIT RECORDING AP-

PLICATIONS
LOW POWER OPERATION (500mW TYPI-

CAL @ 5V @ 32Mbits/Sec
PROVIDES PROGRAMMABILITY THROUGH

SERIAL MICROPROCESSOR INTERFACE
ANDINTERNALREGISTERS

- Bi-directional access to internal registersof
pulse detector, filter, servo demodulator,
frequencysynthesizerand data separator.

PROGRAMMABLEPOWER DOWN MODES
Fullpower-downmode (5mWmax.)

POWER SUPPLYRANGE 4.3 to 5.5V

DESCRIPTION

The L6000 is a 5V single chip read channel IC. It
contains all the functions needed to implement a
high performance read channel including the

L6000

ADVANCE DATA

TQFP64

(10 x 10)

ORDERING NUMBER: L6000

OPERATING TEMPERATURE: 0°Cto70°C

pulse detector, programmable active filter, servo
demodulator, frequency sinthesizer, and data
separator, at data rates up to 32 Mbit/s. A single
external resistor sets the reference current for the
internalDAC which, in turn, fixes thedata rate.

This device is programmed through a serial port
and banks of internal registers. It is fully compat­ible with zoned bit recording applications. Exter­nal componentsdo not need to be changed when
switching between zones. The L6000 is manufac­turedusing an advancedBiCMOS technology.

PIN CONNECTION (Top view)

LEVEL R EF V
CLOCK PATH
CLOCK PATH

DATA PATH

FILT NORM OUT
FILT NORM OUT

FILT DIFF OUT
FILT DIFF OUT

FILTER IN
FILTER IN

PTAT R

AGC O UT

SERVO BYP

SERVO REF V

48 47 46 45 44

49
50
51

52
53
54
55
56
57
58
59
60
61
62
63
64

12345

AGC IN

AGC IN

POSITION OUT

DATA BYP

HOLD CAP A

HOLD DATA AGC

DATA TC RES

SERVO TC RES

DAC TP OUT

HOLD CAP B

43 42 41 40 39

678910

PWRDN MODE

VCC CORE DIG

GND PULSE DET

SERIAL DATA I/O

GND CORE DIG

SERVO GATE

38 37 36 35 34

11 12 13 14 15

SERIAL ENABLE

SERIAL CLOCK +

HOLD SRV AGC

REFERENCE FIN

LATCH CAP A

GND FREO SYN

LATCH CAP B

RESET CAP A/B

GND DATA SEP

DS IREFFREQ SYN FLT

33

32LEVEL

DATA SEP FLT

31

DATA SEP FLT

30

VCC DATA SEP

29

READ DATA I/O

28

ADDR MARK DET

27DATA PATH

READ REF CLOCK

26

WRITE CLOCK

25

MULT TP1

24

MULT TP2

23

GND I /O

22VCC PULSE DET

WRITE DATA NR2 IN

21

READ NR 2 OUTPUT

20

WRITE DATA

19

VCC I/O

18

WRITE GATE

17AGC O UT READ GA TE

16

M92L6000-01

FREQ OUT TP

FREQ SYN FLT

VCC FREQ SYN

August 1993

1/24

This isadvanced information on a new product now in development orundergoing evaluation. Details are subject to change without notice.

L6000

Figure1a: Block Diagram (1 of 2)

2/24

Figure1b: BlockDiagram(2 of 2)

L6000

ABSOLUTE MAXIMUMRATINGS

Symbol Parameter Value Unit

Vcc Positive Supply Voltage – 0.5 to 7 V

VoltageApplied to Logic Inputs –0.5 to Vccs + 0.5 V
VoltageApplied to All Other Pins – 0.5 to Vccs +0.5 V

Tstg Storage Temperature – 65 to +150

Tj JunctionTemperature 130

o
o

C
C

3/24

L6000

PIN DESCRIPTION

Pin # Symbol Type Description

POWER SUPPLY

30 Vcc DATA SEP - DATA SEPARATOR: PLL analog 5V supply.
14 Vcc FREQ. SYNTH - FREQUENCY SYNTHESIZER: PLL analog 5V supply.

7 Vcc CORE DIG - Internal ECL, CMOS logic digital supply.
19 Vcc I/O TTL BUFFER I/O5V SUPPLY.
59 Vcc PULSE DET - Pulse Detector/Servo Demodulator/Filter analog5V supply.
34 GND DATA SEP - DATA SEPARATOR: PLL analog5V ground.
12 GND FREQ SYN - FREQUENCY SYNTHESIZERl: PLL analog 5Vground.
40 GND CORE DIG - Internal ECL, CMOS logic digital ground.
23 GND I/O - TTL Buffer I/O digital ground.

5 GND PULSE DET - Pulse Detector/Servo Demodulator/Filter analog circuit ground.

INPUT

2, 1 AGC IN,

AGCIN

53, 54 DATA PATH,

DATA PATH

51, 52 CLOCK PATH,

CLOCK PATH

6 PWRDN MODE I PWRDN MODE CONTROL: TTL compatible power control pin. Assertion shuts

4 HOLD DATA AGC I HOLD DATA AGC CONTROL INPUT: TTL compatible power control pin.

38 HOLD SRVAGC I HOLD DATA AGC CONTROL INPUT: TTL compatible control pin.Assertion

47 SERVO REF V I SERVO REFERENCE .VOLTAGE INPUT: This voltage is set to half of the Vcc

37 LATCH CAP A I LATCH CONTROL INPUT: TTL compatible input. Switcheschannel A into

36 LATCH CAP B I LATCH CONTROL INPUT: TTL compatible input. Switcheschannel B into

35 RESET CAP A/B I RESET CONTROL INPUT: TTL compatible input. Enables the discharge of

60, 61 FILTER IN,

FILTER IN

11 REFERENCE FIN I REFERENCE FREQUENCY INPUT: TTL input. Pin REFERENCE FIN has an

22 WRT DATANRZ

IN

17 READ GATE I READ GATE : See clocks and Modes.
26 WRITE CLOCK I WRITE CLOCK: TTL input Write mode clock. Must be synchronous with the

18 WRITE GATE I WRITE GATE: TTLinput. Enables the write mode. See Clocks and Modes.
39 SERVO GATE I SERVO GATE: TTL input. Enables the servo read mode. Active low.

| AGC AMPLIFIER INPUTS: Differential AGC amplifier input pins.

I ANALOG INPUTS FOR DATA PATH: Differentialanalog inputs to data

comparators, full-wave rectifier, and servo demodulator.

I ANALOG INPUTS FOR CLOCK PATH: Differential analog inputsto the clock

comparator.

down all circuitry, except the serialport. Deassertion and the appropriate bit set
in PD register shuts down the selected circuitry. Active low.

Assertion disables the AGC charge pump and holds the input AGC amplifier
gain. Active low.

disables the SERVO charge pump. Active low.

PULSE DET voltage

peak acquisitionmode when low. Cap voltage doesn’t change when high.

peak acquisitionmode when low. Cap voltage doesn’t change when high.

channel A & B hold capacitors when asserted. Active low.

I FILTER SIGNAL INPUTS: Self biased differential input signals to activefilter.

internal pull up resistor. In the test mode, when frequency synthesizer is
bypassed, the REFERENCE FIN frequency requiredis 3 times the data rate.
REFERENCE FIN may be driven by a direct coupled TTL signal.

I WRITE DATA NRZ INPUT. TTL input. Connected to the READ NRZ OUTPUT

pin toform a bidirectional data port. Pin WRT DATA NRZ IN has an internal
pull up resistor.

Write Data NRZ input. For short cable delays, WRITE CLOCK may be
connected directly to pin READ REF CLOCK. For long cable delays,WRITE
CLOCK should be connected to a READ REF CLOCK return line matched to
the NRZ data bus line delay.

4/24

PIN DESCRIPTION(continued)

Pin # Symbol Type Description

OUTPUT

64, 63 AGC OUT,

AGC OUT

29 READ DATA I/O I/O READ DATA I/O: Bi-directional TTL pin. Output is active in the servo mode or

46 POSITION OUT O POSITION ERROR SIGNAL: A Position errorsignal of A minus B output which

56, 55 FILT NORM OUT,

FILT NORM OUT

58, 57 FILT DIFF OUT,

FILT DIFF OUT

28 ADDR MARK DET O ADDRESS MARK DETECT: Tristate output pin with TTL output levels. It is in

25 MULT TP1 O MULTIPLEXED TEST POINTOUTPUT:An open emitterECLoutputtest point.

21 READ NRZ

OUTPUT

27 READ REF CLOCK 0 READ REFERENCE CLOCK: TTL output. A multiplexed clock source used by

24 MULT TP2 O MULTIPLEXED TEST POINT OUTPUT: An open emitter ECL output test point.

20 WRITE DATA O WRITE DATA: TTL output. Encoded write data output. The data is

13 FREQ OUT TP O REFERENCE FREQUENCY OUTPUT: An open emitter ECL output test point.

O AGC AMPLIFIER OUTPUT: DifferentialAGC amplifier output pins.

when both READ GATE andWRITE GATE aredeasserted. In test mode, this
is a TTL input used to drive the data separator. The TTL input is enabled by
setting RDI in the control register CB.

is referenced to SERVO REF V.

O FILTER DIFFERENTIAL NORMAL OUTPUTS: Low pass & boosted filter

output signals.Must be AC coupled to the next stage nominally DATA PATH.

O FILTER DIFFERENTIAL DIFFERENTIADED OUTPUTS: Differentiated filter

outputs should be AC coupled to the next stagenominally CLOCK PATH.

its high impedance state when WRITE GATE is asserted. When READ GATE
is asserted and the register bit is set for soft sector,an address mark search is
initiated in the soft sector operation. This output is latched low (true) when an
address mark hasbeen detected. Deasserting pin READ GATE deasserts pin
ADDR MARK DET.

The testpoint output is enabled by Setting ED inthe control registerCB. The
controllingsignal is PD_TEST in thecontrol register CA. WhenPD_TEST is low ,
thetestpointoutput is the delayed read dataDRD. Theposistive edges of this
signalindicate thedata bit position. The positive edges of theDRD and VCOREF
outputs can be used to estimatewindow centering. The time jitterof DRD’s
positive edge is an indication of media bit jitter.When PD_TESTishigh the test
pointout is the comparator of the pulse qualifier. The positive edge indicatesthat
theinput signal hasexceeded thepositive threshold while a negative edge
indicates that the input signal has gone belowthenegative threshold. Two external
resistors are required to use thispin. Theyshould be removed during normal
operation toreduce power dissipation.

O NRZ OUTPUT DATA: Tristate ouput pin with TTL output levels. It is in its high

impedance state when READ GATE is deasserted. Readdata output when
READ GATE is asserted.

the controller, see Clocksand Modes. During a modechange, no glitchesare
generated and no more than one lost clock pulse will occur. READ REF
CLOCK remains Fout/3 after READ GATE is asserted, until after synchronized
bits are detected.

This test point output is enabled by using the same control bit enabling the
MULT TP1 output. When the controlling signal, PD_TEST is desserted, the test
point output is the VCO reference input (VCOREF) to the phase detector.The
positive edges are phase locked to Delayed Read Data (DRD). The negative
edges of this open emitter output signal indicate the edges of the decode
window. When PD_TEST is high, the test point output represents the state of
the clock comparator in thepulse qualifier. The signal transitions indicate zero
crossing of the differentiated signal from the electronic filter. Two external
resistor are required to use this pin. They should be removed during normal
operation to reduce power dissipation.

automatically resynchronized (independent of the delay between READ REF
CLOCK and WRITE CLOCK) to the reference clock FSout. Falling edge of the
WRITE DATA is the data edge.

The frequency is the frequency synthesizer output frequency. This output is
enabled by control register CA. Two external resistors are required to use this
pin. They should be removed during normal operation to reduce power
dissipation.

L6000

5/24

L6000

PIN DESCRIPTION(continued)

Pin # Symbol Type Description

ANALOG

50 LEVEL REF V O REFERENCE VOLTAGE: Reference voltage output for LEVEL. LEVEL REF V

62 EF IREF I REFERENCE RESISTOR INPUT: An external 1% resistor (RX) is connected

3 DATA BYP – AGC INTEGRATING CAPACITOR: Connected between DATA BYP and Vcc

48 SERVO BYP – AGC INTEGRATING CAPACITOR FOR SERVO: Connected betweenSERVO

45 HOLD CAP A – PEAK HOLDING CAPACITOR A: Tied from this pin to GND PULSE DET.
44 HOLD CAP B – PEAK HOLDING CAPACITOR B: Tied from this pin to GND PULSE DET.
49 LEVEL O HYSTERESIS LEVEL: An NPN emitter output that provides a full-wave

33 DS IREF I REFERENCE RESISTOR INPUT: An external 1% resistor (RR) is connected

42 SERVO TC RES I SERVO TIME CONSTANT RESISTOR INPUT: An external resistor is

15, 16 FREQ SYN FLT,

FREQ SYN FLT

32, 31 DATA SEP FLT,

DATA SEPFLT

41 DAC TP OUT O DAC OUTPUT: A testpoint for some of the on-chip DACs. The output of an

SERIAL PORT

10 SERIAL ENABLE I SERIAL DATA ENABLE: Active high input pin to enablethe serial port CMOS

8 SERIAL DATA I/O I/O SERIAL DATA: Input/Output pin for serial data; 8 instruction/address bits are

9 SERIAL CLOCK+ I SERIAL DATA CLOCK: Positive edgetriggered clock input for the serial data

is derived by referencing VRG (an internal signal) to Vcc PULSE DET.

from this pin to ground to establish a precise reference current for the filter.

PULSE DET. This pin is used when data read mode.

BYP and Vcc PULSE DET. This pin is used whenin servo read mode

rectified signal from LEVEL to LEVEL REF V toset the hysteresis threshold
time constant in conjunction with SERVO TC RES and DATA TC RES. This
level used in VTHRESHOLD DAC.

to this pin to establish a precise internalreference current for the data
separator and Frequency Synthesizer.

connected from this pin to LEVEL to establish the hysteresis threshold time
constant when not in Servo mode.

– PLL FILTER: The two connection points for the frequency synthesizer PLL

differential filter components.

– PLL FILTER: THE Two connectionpoints for the data separatorPLL differential

filter components.

internal DAC is selected bythe values of TDAC1 (MSB) and TDACO (LSB) in
the WS register. The selected DAc output and its corresponding select bits are
as follows: FC_DAC (00), VTH_DAC (0 1), WS_DAC (1 0), andWP_DAC (1

1). When not using the DAC TP OUT pin, the preferred setting is to select the
FC_DAC.

input levels.

sent first followed by 8 data bits. CMOS Input/Output levels.

CMOS input levels. The pin has an internal pull-up resistor.

6/24

L6000

SYSTEM DESCRIPTION
PulseDetector Section

Fast attack/decaymodes for rapid AGC recovery.
Dual rate chargepump for fasttransient recovery.
Low Drift AGC hold circuitry supportsprogramma­ble gain, non-AGC operation. Temperature com­pensated,exponential control AGC. Shorted input
switch for transient recovery, during Power down
& Write to read & Idle mode transitions. Wide
Bandwidth, high precision full-wave rectifier. Dual
mode pulse qualification circuitry allows either in­dependent positive and negativethreshold qualifi­cation to suppresserror propagation or hysteresis
comparison wich implements alternating polari­ties. Differential qualifier comparator. TTL READ
DATA I/O signal output available during servo
and idle modes. Timing for shorted inputs and
fast decay functions set internally. 0.5 ns max.
pulse pairing with sine wave input.

Embedded ServoDemodulatorSection

Dual servo burst (A/B) capturewith PositionError
Signal Output. ServoAGCmode which holds sum
of A and B bursts constant. Provision for on-chip
switching of the hysteresis threshold time con­stant.

Programmable Filter Section

Programmable filter cutoff frequency (fc = 6 to 18
MHz). Programmablepulse slimming equalization
(0 to 9 dB Boost at the filter cutoff frequency).
Matched path timing normal and differential low­pass outputs. Differential filter input and outputs
for noise rejection ±10% cutoff frequency accu­racy. ±2% maximum group delay variation in the
passband maintained over the cutoff frequency
tuning range ( fc=6 to 18 MHz ). Total harmonic
distortion less than 1.5 %. No external filter com­ponents required. Shorted input switch for tran­sient recovery, during Power down & Write to
Read & Idle mode transitions.

Frequency Synthesizer and Data Separator
Section

1% frequency resolution. Data synchronizer and

1.7 RLL ENDEC. Fast acquisition phase lock loop
with zero phase restart both to data and synthe­sizer. Fully integrated data separator. No external
delaylines or activedevices required. No external
active PLL components required. Active window
centering symmetry control via serial port. Win­dow shift control ±30%. Includes delayed read
data and VCO clock monitor tests points. Pro­grammablewrite precompensation.Hard and soft
sectoroperation.

THERMAL DATA

Symbol Parameter Value Unit

Rth

R

th j-case

j-amb

Thermal Resistance Junction-Ambient 100 °C/W
Thermal Resistance Junction-Case 20 °C/W

RECOMMENDED OPERATINGCONDITIONS

Vccn SupplyVoltage 4.3 to 5.5 V

T

amb

T

j

Operating Ambient temperature 0 to 70 °C
JunctionTemperature 25 to 125 °C

7/24

L6000

ELECTRICAL CHARACTERISTICS: V

= 5V + 10% - 14%, T

CCn

= 0 to 70 °C, Tj= 25 to 125°C, un-

amb

less otherwisespecified.

Symbol Parameter Test Condition Min. Typ. Max. Unit

POWER SUPPLY CURRENT AND POWER DISSIPATION

Icc Power Supply Current Outputsandtestpoint pins open;
Pd Power Dissipation – 500 660 mW

Tamb= 27°C, 32Mbits/sec

– 100 120 mA

DIGITAL INPUTS AND OUTPUTS

V

IL

V

IH

Low Level Input Voltage – 0.3 0.8 V
High Level Input Voltage 2.0 V

CC

I/O+0.3

I

IL

I

IH

V

OL

V

OH

Low Level Input Current VIL= 0.4V – – 0.4 mA
Low Level Input Current VIH= 2.4V – 100 µA
Low Level Output Voltage IOL= 4.0mA – 0.5 V
High Level Output Voltage IOH= –400µA 2.4 – V

CMOS INPUTS: SERIAL ENABLE, SERIAL DATA AND SERIAL CLOCK

V

IL

V

IH

t

r

t

f

Low level Input Voltage 5V and 25°C – 0.5 V
High Level Input Voltage 4.5 – V
Rise Time 4.3V, 70°C and C = 5pF – 5.0 ns
Fall Time – 4.5 ns

CMOS OUTPUTS: SERIAL DATA I/O

V

OL

V

OH

t

r

t

f

Low Level Output Voltage 5V and 25°C; IOL= 4.07mA – 0.5 V
High Level Output Voltage 5V and 25°C; IOH= +4.83mA 4.5 – V
Rise Time 4.3V, 70°C and C = 15pF – 5.5 ns
Fall Time – 5.0 ns

TEST POINT OUTPUT LEVELS

V

IL

Test Point High Level Output

261Ω to Vcc DATA SEP

Vcc

–V

DATA

SEP-

1.02
– Vcc

V

IH

(MTP1, MTP2, FOUT)

Test Point Low Level Output

402Ω to GND DATA SEP, Vcc
DATA SEP = 5V

261Ω to Vcc DATA SEP

DATA

(MTP1, MTP2, FOUT)

402Ω to GND DATA SEP, Vcc
DATA SEP = 5V

SEP-

1.62

PULSEDETECTOR AND SERVO DEMODULATOR CHARACTERISTICS

V

V

Symbol Parameter Test Condition Min. Typ. Max. Unit

AGC Amplifier Section

The input signals are AC coupled to AGC IN and AGC IN. AGC OUT and AGC OUTare AC coupled to FILTER IN
and FILTER IN.FILT NORM OUT and FILT NORM OUT are AC coupled to DATA PATH and DATA PATH.
IntegratingcapacitorCa = 1000pF is connected between DATABYP andVcc PULSE DET. Unless otherwise specified,
theoutput is measured differentially at AGC OUTand AGC OUT,Fin =4MHz,andthe filter boostat FB = 0dB.

Input range Filter Boost at FC = 0dB

22 – 240 mVpp
(bench testcondition = 2.2 to
18MHz)

Input range Filter Boost at FB = 9dB

14 – 100 mVpp
Fin = FC = 18MHz
(bench test condition = 6 to
18MHz)

DATAPATH/

Voltage AGC IN-AGC IN= 0.1Vpp 0.945 1.05 1.155 Vpp

DATAPATH

Voltage Variation 22mV < AGC IN = AGC IN <

–8.0 – +8.0 %

240mV

Gain Range 1.9 – 22 V/V

8/24