SGS Thomson Microelectronics L4992 Datasheet

TRIPLE OUTP U T POWE R S UPP LY CO NTR O LL ER

DUAL PWM BUCK CONTROLLERS (3.3V and 5.1V)

12V/120mA LINEAR REGULATOR DUAL SYNCH RECTIFIERS DRIVERS 96% EFFICIENCY ACHIEVABLE 50µA (@ 12V) STAND BY CONSUMPTION

5.5V TO 25V SUPPLY VOLTAGE EXCELLENT LOAD TRANSIENT RESPONSE DISABLE PULSE SKIPPING FUNCTION POWER MANAGEMENT:

- UNDER AND OVERVOLTAGE OUTPU T DETECTION

- POWER GOOD SIGNAL

- SEPARATED DISABLE THERMAL SHUTDOWN PACKAGE: TQFP32

APPLICATION

NOTEBOOK AND SUBNOTEBOOK COMPUTERS

PEN TOP AND PO RTABLE EQUIPMENT COMMUNICATING COMPUTE RS

DESCRIPTION

The L4992 is a sophisticated dual PWM stepdown controller and power monitor intended for Notebook computer and/or battery powered equipment. The device produces regulated +3.3V, +5.1V and 12V supplies for use in portable

L4992

TQFP32

ORDERING NUMBER: L4992

and PCMCIA applications. The internal architecture allows to operate with minimum external components count. A very high switching frequency (200/300 KHz or externally synchronizable) optimizes their physical dimensions. Synchronous rectification and pulse skipping mode for the buck sections optimise the overall efficiency over a wide load current range (96% efficiency @1A/5.1V and 93% efficiency @

0.05A/5.1V. The two high performance PWM controllers for +3.3V and +5.1V lines are monitored for overvoltage, undervoltage and overcurrent conditions. On detection of a fault, a POWER GOOD signal is generated and a specific shutdown procedure takes place to prevent physical damage and data corruption. A disable function allows to manage the output power sections separately, optimising the quiescent consumption of the IC in stand-by conditions.

SYSTEM BLOCK DIAGRAM

5.5V to

25V

SYNC

POWER

MANAGEMENT

& SYSTEM

SUPERVISOR

D96IN429A

June 2000

L4992

POWER

SECTION

3.3V

5.1V

12V LDO

5.1V LDO

3.39V REF

POWER GOOD

µP

MEMORY

PERIPHERALS

1/26

L4992

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

OUT

THERMAL DATA

Symbol Parameter Value Unit

TH J-amb

Power Supply Voltage on V

0 to 25 V Maximum Pin Voltage to Pins 1, 24, 25, 32 -0.5 to (VIN +5) V Input Current Except V13IN and V

-1 to +1 mA Output Current Digital Output -15 to +15 mA Junction Temperature -55 to 150 °C

Thermal Resistance Junction -Ambient 60 °C/W

PIN CONNECTION

BLOCK DIAGRAM

I5SNS

V5SNS

COMP5

H5STRAP

H5GATE

H5SRC

R5GATE

PGND5

REG5

W5SW

VIN

12VREF

SGND

(Top view)

H5GATE

R5GATE

H5SRC

PGND5

PGND3

R3GATE

H3SRC

H3GATE

32 3031 29 28 27 26 25

H5STRAP

(*)TO BE CONNECTED TO PIN13

SLOPE

VREF

Hside

REG5 REG5

Lside

COMPARATOR

VREF BUFFER

CONTROL

SWITCH

ERROR SUMMING

∑

LOGIC

LINEAR

REGULATOR

OVER CURRENT

COMPARATOR

ZERO CROSSING

COMPARATOR

PULSE SKIPPING

COMPARATOR

V5SNS

VREF

1 2

VIN

REG5

V5SW

V5SNS

I5SNS

COMP5

SOFT5

910

11 12 13 14 15 16

VREF

CRST

RUN5

PWROK

SOFT5 8

SOFT

I5SNS V5SNS

OVERVOLT

COMPARATOR

4.7V

RUN3 RUN5 PWROK NOSKIP CRST

POWER MANAGEMENT

SYSTEM SUPERVISOR

16 11 10 14 9

SGND

COMPARATOR

OSC

NOSKIP

SOFT3

SOFT

I3SNSV3SNS

UNDERVOLT

H3STRAP

(*)

REG12

V13IN

V3SNS

I3SNS

COMP3

SOFT3

D96IN377

RUN3

OVER CURRENT

COMPARATOR

ZERO CROSSING

COMPARATOR

PULSE SKIPPING

COMPARATOR

ERROR SUMMING

VREF

∑

VREF

CONTROL

LOGIC

13V UV Comp

OSCILLATOR &

SYNCHRONIZATION

13V

Hside

Lside

SLOPE

D96IN375

REG12

LDO

I3SNS

V3SNS

COMP3

H3STRAP

H3GATE

H3SRC

R3GATE

PGND3

V13IN

REG12

OSC

2/26

PIN FUNCTIONS

N. Name Description

1 H5STRAP +5.1V section bootstrap capacitor connection 2V

3 REG5 +5V regulator supply. Used mainly for bootstrap capacitors. It should be bypassed to ground. 4 V5SW Alternative device supply voltage. When the +5.1V section is operating, the device is no

5 V5SNS This pin connects to the (-) input of the +5.1V internal current sense comparator 6 I5SNS This pin connects to the (+) input of the +5.1V internal current sense comparator 7 COMP5 Feedback input for the +5.1V section. 8 SOFT5 Soft-start input of the +5.1V section. The soft-start time is programmed by an external

9 CRST Input used for start-up and shut-down timing. A capacitor defines a time of 2ms/nF.

10 PWROK Power-good diagnostic signal. This output is driven high when both switching sections are

11 RUN5 Control input to enable/disable the 5.1V section. A high level (>2.4V) enables this section, a

12 VREF Internal +3.39V high accuracy voltage generator. It can source 5mA to external load. Bypass

13 SGND Signal ground. Reference for internal logic circuitry. It must be routed separately from high

14 NOSKIP Pulse skipping mode control. A high level (>2.4V) disables pulse skipping at low load current,

15 OSC Oscillator frequency control: connect to 2.5V to select 300KHz operation, to ground or to 5V

16 RUN3 Control input to enable/disable the +3.3V section. A high level (>2.4V) enables this section, a

17 SOFT3 Soft-start input for the 3.3V section. The soft-start time is programmed by an external

18 COMP3 Feedback input for the +3.3V section 19 I3SNS This pin connects to the (+) input of the +3.3V internal current sense comparator 20 V3SNS This pin connects to the (-) input of the +3.3V internal current sense comparator 21 V13IN 12V regulator input supply voltage, included between 13 and 20V. This voltage can be

22 REG12 12V regulator output voltage. It can source up to 150mA to an external load 23 SGND To be connected to pin 13 24 H3STRAP +3.3V section bootstrap capacitor connection 25 H3GATE Gate- driver output for the +3.3V high-side N-MOS 26 H3SRC +3.3V high-side N-MOS source connection 27 R3GATE Gate- driver output for the +3.3V low- side N-MOS (synchronous rectifier). 28 PGND3 Current return for +3.3V section drivers 29 PGND5 Current return for +5.1V section drivers 30 R5GATE Gate-driver output for the +5.1V low-side N-MOS (synchronous rectifier). 31 H5SRC +5.1V high-side N-MOS source connection 32 H5GATE Gate-driver output for the +5.1V high-side N-MOS

Device supply voltage. From 5.5 to 25V

longer powered through V

but through this pin.

capacitor connected between this pin and SGND. Approximately, 1ms/nF @ full load.

enabled and running properly, after a delay defined by the CRST capacitor.

low level (<0.8V) shuts it down

to ground with a 4.7µF capacitor to reduce noise.

current returns.

a low level (<0.8V) enables it.

for 200KHz operation. A proper external signal can synchronize the oscillator

low level (>0.8V) shuts it down.

capacitor connected between this pin and GND. Approximately, 1ms/nF @full load.

supplied by a flyback winding on +3.3V inductor

L4992

3/26

L4992

ELECTRICAL CHARACTERISTICS

= 12V; TJ = 25°C; V

OSC

= GND; unless otherwise specified.)

Symbol Parameter Test Condition Min. Typ. Max. Unit

DC CHARACTERISTICS

+5.1V PWM CONTROLLER SECTION

5OUT

- V

V6 - V

Input Supply Voltage 5.5 25 V Operating Quiescent Current R5GATE = R3GATE = OPEN

H5GATE = H3GATE = OPEN RUN3 = RUN5 = REG5 (DRIVERS OFF)

Stand-By Current RUN3 = RUN5 = GND

V V

= 12V

= 20V

50 60

(*) V5SNS Feedback Voltage VIN = 5.5 to 20V;

- V

I5SNS

Over-Current Threshold Voltage VSOFT5 = 4V 80 100 120 mV

Pulse Skipping Mode

Thereshold Voltage

VIN > 6.8V 14 26 38 mV

< 5.8V 7 13 19 mV

= 0 to 70mV

V5SNS

Over Voltage Threshold ON V5SNS

Under Voltage Threshold ON V5SNS

4.85 5.13 5.25 V

5.35 5.55 5.77 V

4.54 4.69 4.87 V

1.35 mA

100 120

+3.3V PWM CONTROLLER SECTION

(*) V3SNS Feedback Voltage VIN = 5.5 to 20V;

3OUT

V19 - V

- V

Over Current Threshold Voltage VSOFT3 = 4V 80 100 120 mV

Pulse Skipping Mode Threshold

I3SNS

VIN = 5.5 to 20V; 14 26 38 mV

Voltage

Over Voltage Threshold ON V3SNS

Under Voltage Threshold ON V3SNS

- V

= 0 to 70mV

V3SNS

3.285 3.39 3.495 V

3.55 3.7 3.85 V

3.02 3.14 3.27 V

µA

PWM CONTROLLERS CHARACTERISTICS (BOTH SECTIONS)

OSC

OFF

, I

, V

(*) Guaranteed by design, not tested in production

4/26

Switching Frequency Accuracy OSC = REG5/2 255 300 345 kHz

OSC = 0 or REG5 170 200 230 kHz

Voltage Range for 300kHz Operation

Dead Time 300 375 450 ns Overvoltage Propagation Time V5SNS to PWROK or

V3SNS to PWROK

Undervoltage Propagation Time V5SNS to PWROK or

V3SNS to PWROK

Soft Start Charge Current 3.2 4 4.8 µA

Soft Start Clamp Voltage 4 V

2.4 2.6 V

1.25 µs

1.5 µs

L4992

ELECTRICAL CHARACTERISTICS

(Continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

HIGH AND LOW SIDE GATE DRIVER (BOTH SECTIONS)

I25, I

I32, I

R R

H L

Source Output Peak Current C

27,

Sink Output Peak Current C R

Resistance (or Impeda nce ) Driver OUT HIGH 7 Ω

DSON

resistance (or Impedance) Driver OUT LOW 5 Ω

DSON

Output High Voltage HSTRAP = REG5

= 1nF 0.2 0.5 A

LOAD

= 1nF 0.2 0.5 A

LOAD

4.40 5.3 5.61 V

= 10mA; HSRC = GND

SOURCE

Output Low Voltage HSTRAP = REG5

= 10mA HSRC = GND

SINK

Cross-Conduction Delay 30 75 130 ns

0.5 V

12V LINEAR REGULATOR SECTION

Input Voltage Range 13 20 V Output Voltage I22 = 0 to 120mA 11.54 12.0 12.48 V Current Limiting V Short Circuit Current V Input Voltage Clamp I "One Shot" Activation Threshold V

= 12V 120 mA

REG12

= 0V 150 mA

REG12

= 100µA16 V

CLAMP

Falling 12.88 13.7 14.52 V

13IN

"One Shot" Pulse 1.5 µs

INTERNAL REGULATOR (VREG 5) AND REFERENCE VOLTAGE

VREG5 Output Voltage VIN = 5.5 to 20V

= 0 to 5mA

LOAD

Total Current Capability VREG5 = 5.3V

= 6V

REG5

4.5 5.3 5.61 V

70 Switch-Over Threshold Voltage 4.3 4.53 4.7 V Reference Voltage 3.35 3.39 3.43 V

Source Current at Reference

= 5.5 to 20V

= 1 to 5mA

LOAD

3.32 3.39 3.46 V

5mA

Voltage

POWER GOOD AND ENABLE FUNCTION

V16, V

, V

, T

SYNCHRONIZATION

RUN3, RUN5, Enable Voltage HIGH LEVEL 2.4 V

RUN3, RUN5, Disable Voltage LOW LEVEL 0.8 V

Power Good Delay C Shutdown Delay Time before

Low Side Activation (Except Over-Voltage Fault)

CRST Timing Rate 2 ms/nF Power Good High Level I Power Good LowLevel I

Synchronisation Pulse Width 400 ns Synchronisation Input Voltage

(Falling Edge Transition)

= 100nF 160 200 240 ms

CRST

= 100nF, 160 200 240 ms

CRST

= 40µA 4.1 V

PWROK

= 320µA 0.4 V

PWROK

5/26

L4992

DETAILED FUNCTIONAL DESCRIPTION

In the L4992 block diagram six fundamental functional blocks can be identified:

3.3V step-down PWM switching regulator (pins 17 to 20, 24 to 27).

5.1V step-down PWM switching regulator (pins 1, 4 to 8, 30 to 32). 12V low drop-out linear regulator (pins 21,22). 5V low drop-out linear regulator (pin 3).

3.3V reference voltage generator (pin 12). Power Management section (pins 9 to 11, 14,16).

The chip is supplied through pin VIN (2), typically by a battery pack or the output of an AC-DC adapter, with a voltage that can range from 5.5 to 25V. The return of the bias current of the device is the signal ground pin SGND (13), which references the internal logic circuitry.

The drivers of the external M OSFET’s have their separate current return for each section, namely the power ground pins PGND3 (28) and PGND5 (29). Take care of keeping separate the routes of signal ground and the two power ground pins when laying out the PCB (see "Layout and grounding" section).

The two PWM regulators shar e the internal oscillator, pr ogr ammable or s yn chronizable through pin OSC (15).

+3.3V AND +5.1V PWM REGULATORS Each PWM regulator includes control circuitry as well as gate-drive circuits for a step-down DC-DC con-

verter in buck topology using synchronous rectification and current mode control. The two regulators are independent and almost identical. As one can see in the Block Diagram, they

share only the oscillator and the internal supply and differ f or the pre- set output v oltages and f or t he c ontrol circuit that links the +3.3V section to the operation of the 12V linear regulator (see the relevant section).

Each converter can be turned on and off independently: RUN3 and RUN5 are control inputs which disable the relevant section when a low logic level (below 0.8 V) is applied and enable its operation with a high logic level (above 2.4 V). When both input s are low the device is in stand- by condition and its current consumption is extremely reduced (less than 120µA over the entire input voltage range).

Oscillator

The oscillator, which does not require any external timing component, controls the PWM switching frequency. This can be either 200 or 300 kHz, depending on the logic s tate of the control pin OSC, or else can be synchronized by an external oscillator.

If OSC is grounded or connected to pin REG5 (5V) the oscillator works at 200kHz. By connecting OSC to a 2.5 V voltage, 300 kHz operation will be selected. I nstead, if pin OSC is fed with an ex ternal signal like the one shown in fig. 1, the oscillator will be synchronized by its falling edges.

Considering the spread of the oscillator, synchronization can be guaranteed for frequencies above 230kHz. Even though a maximum frequency value is in pr actice imposed by efficiency considerations it should be noticed t hat increasing frequency too much arises problem s (noise, subharmonic oscillation, etc.) without significant benefits in terms of external component size reduction and better dynamic performance.

The oscillator imposes a time interval (300 ns min.), during which the high-side MOSFET is definitely OFF, to recharge the bootstrap capacitor ( see "MOSFET’s Drivers" section). This, implies a limit on the maximum duty cycle (88.5% @ fsw = 300kHz, 92.6% @ fsw = 200kHz, worst case) which, in turn, imposes a limit on the minimum operating input voltage.

PWM regulati on

The control loop does not employ a tradit ional error amplifier in favour of an error summing comparator which sums the reference voltage, the feedback signal, the voltage drop across an external sense resistor and a slope compensation ramp (to avoid subharmonic oscillation with duty cycles greater then 50%) with the appropriate signs.

The output latch of both controllers is set by every pulse coming from the oscillator. That turns off the low-side MOSFET (synchronous rectifier) and, after a short delay (typ. 75 ns) to prevent cross-conduction, turns on the high-side one, thus allowing energy to be drawn from the input source and stored in the inductor.

6/26

L4992

DETAILED FUNCTIONAL DESCRIPTION Figure 1:

Figure 2:

Synchronization signal and operation.

OSC

H5GATE

H3GATE

L4992 Control Loop.

CLOCK

SRQ

E.S.

(continued)

HSTRAP

REG5

SLOPE COMP.

VREF

400ns min.

VIN

D97IN574

Rsense

ESR

The error summing, by comparing the above mentioned signals, determines the moment in which the output latch is to be reset. The high-side MOSFET is then turned off and the synchronous rectifier is turned on after the appropriate delay (typ. 75 ns), thus making the inductor current recirculate. This state is maintained until the next oscillator pulse.

With reference to the schematic of fig. 2, the open-loop transfer function of such a kind of control system, under the assumption of an ideal slope compensation, is:

F(s) = A⋅

sense

⋅

(1 +

1 + s ⋅ ESR ⋅ C

s ⋅ R

O CO

) ⋅ (1 +

s ⋅ R

F CF

)

where A is the gain of the error summing comparator, which is 2 by design. The system is inherently very fast since it tends to correct output voltage deviations nearly on a cycle-by-

cycle basis. Actually, in case of line or load changes, few switching cycles can be sufficient for the transient to expire.

The operation above illustrated is modified during particular or anomalous conditions. Leaving out other circumstances (described in "Protections" section) for the moment, consider when the load current is low enough or during the first switching cycles at start-up: the inductor current may become discontinuous, that is it is zero during the last part of each cycle. In such a case, a "zero current comparator" detects the event and turns off the synchronous rectifier, avoiding inductor current reversal and reproducing the natural turn-off of a diode when reverse biased. Both MOSFET’s stay in off state until the next oscillator pulse.

7/26

L4992

DETAILED FUNCTIONAL DESCRIPTION

(continued)

Synchronous rectification.

Very high efficiency is achieved at high load current with the synchronous rectification technique, which is particularly advantageous because of the low output voltage. The low-side MOSFET, that is the synchronous rectifier, is selected with a very low on -resistance, so that the paralleled Schottky diode is not turned on, except for the small time in which neither MOSFET is conducting. The effect is a considerable reduction of power loss during the recirculation period.

Although the Schottky might appear to be redundant, it is not in a system where a very high efficiency is required. In fact, it s lower threshold prevent s the lossy body-diode of the synchronous rectifier MOSFET from turning on during the above mentioned dead-time. Both conduction and reverse recovery losses are cut down and efficiency can improve of 1-2% in some cases. Besides a small diode is sufficient since it conducts for a very short time.

As for the 3.3V section only, the synchronous rectifier is also involved in the 12 V linear regulator operation (see the relevant section). See also the "Power Management" to see how both synchronous rectifiers are used to ensure zero voltage output in stand-by conditions or in case of overvoltage.

Pulse-skippi ng operation.

To achieve high efficiency at light load current as well, under this condition the regulators change their operation (unless this feature is disabled): they abandon PWM and enter the so-called pulse-skipping mode, in which a single switching cycle takes place every many oscillator periods.

The "light load condition" is det ected when the v oltage across the external sense resistor (V

Rsense

) does not exceed 26mV while the high-side MOSFET is conducting. When the reset s ignal of the output latch comes from the error summing comparator while V reset is driven as soon as V

reaches 26mV. This gives some extra energy that maintains the output

Rsense

is below this value, it is ignored and the actual

Rsense

voltage above its nominal value for a while. The oscillator pulses now set the output latch only when the feedback signal indicates that the output voltage has fallen below its nominal value. In this way, most of oscillator pulses is skipped and the r esulting s witching frequency is much lower, as expressed by the following relationship:

K ⋅

sense

⋅ I

where K = 3.2 ⋅ 10

and fps is in Hz. As a result,

the losses due to switching and to gate-drive,

⋅ V

out

Figure 3:

out

⋅



 



out

−





Pulse-skipping threshold vs. input

voltage (+5.1V section only).

which mostly account for power dissipat ion at low output power, are considerably reduced.

The +5.1V section can work with the input voltage very close to the output one, where the current waveform may be so flat to prevent pulse-skipping from being activated. To avoid this, the pulse-skip-

Vth

26 mV

ping threshold (of the +5.1V section only) is roughly halved at low input voltages, as shown in fig. 3. Under this condition, in the above formula the constant K becomes 12.8 ⋅ 10

13 mV

When in pulse-skipping, the output voltage is some ten mV higher than in PWM mode, just be-

5.5V 5.8V 6.3V 20V

Vin

cause of its mode of operation. If this "load regulation" effect is undesirable for any reason, the pulse skipping feature can be disabled (see "Power Management" section) to the detriment of efficiency at light load.

MOSFET’s drivers

To get the gate-drive voltage for the high-side N-channel MOSFET a bootstrap technique is employed. A capacitor is alternately charged through a diode from the 5V REG5 line when the high-side MOSFET is OFF and then connected to its gate-source leads by the internal floating driver to turn the MOSFET on. The REG5 line is used to drive the synchronous rectifier as well, and therefore the use of low-threshold

8/26

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