TION WITH RE-START DELAY
PWMUVLO WITH HYSTERESIS
IN/OUTSYNCHRONIZATION
DISABLELATCHED
INTERNAL 100ns LEADING EDGE BLANK-
ING OF CURRENT SENSE
PACKAGE:DIP16ANDSO16W
DESCRIPTION
This primary controller I.C., developedin BCD60II
technology, has been designed to implement off
L4990A
PRIMARY CONTROLLER
MULTIPOWER BCD TECHNOLOGY
DIP16SO16W
ORDERING NUMBERS:
line or DC-DC power supply applications using a
fixedfrequency current mode control.
Based on a standard current mode PWM controller this device includes some features as programmable soft start, IN/OUT synchronization,
disable (to be used for over voltage protection
and for power management), precise maximum
Duty Cycle Control, 100ns (typ) leading edge
blanking on current sense, pulse by pulse current
limit and overcurrent protection with soft start intervention.
L4990/L4990A(DIP16)
L4990D/L4990AD (SO16W)
BLOCK DIAGRAM
RCT
3
DC
14
DIS
2.5V
13
ISEN
1.2V
SS
7
July 1999
+
-
-
+
OVER CURRENT
+
-
DIS
BLANKING
1VR
SYNCDC-LIM
TIMING2
T
PWM
FAULT
SOFT-START
2R
12
SGNDCOMP
25V
16V/10V
VREF OK
CLK
DIS
V
CC
Vref
+
PWM UVLO
-
SQ
R
2.5V
+
E/A
-
6
13V
VREF
48151
D98IN1002
9
V
C
10
OUT
11
PGND
5
VFB
1/24
L4990 - L4990A
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
CCSupply Voltage (I
I
OUT
Output Peak Pulse Current1.5A
Analog Inputs & Outputs (6,7)-0.3 to 8V
Analog Inputs & Outputs (1,2,3,4,5,15,14 13)-0.3 to 6V
P
tot
T
j
T
stg
(*) maximum package power dissipation limits must be observed
Power Dissipation @ T
Junction Temperature, Operating Range-25 to 125
Storage Temperature, Operating Range-55 to 150
PIN CONNECTION
< 50mA) (*)selflimitV
CC
=70°C1W
amb
C
°
C
°
SYNC
RCT
DC
VREF
VFB
COMP
SS
V
CC
1
2
3
4
5
6
7OUT
15
14
13
12
11
10
8V
D95IN197
N.C.16
DC-LIM
DIS
ISEN
SGND
PGND
9
C
THERMAL DATA
SymbolParameterValueUnit
R
th j-amb
R
th j-ambThermal Resistance Junction to Ambient
Thermal Resistance Junction to AmbientDIP1680°C/W
SO16
120°C/W
PIN FUNCTIONS
N.NameFunction
1SYNCSynchronization. A synchronization pulse terminates the PWM cycle and discharges Ct
2RCTOscillator pin for external C
3DCDuty Cycle control
4VREF5.0V +/-1.5% reference voltage
5VFBError Amplifier Inverting input
6COMPError Amplifier Output
7SSSoft start pin for external capacitor Css
8V
9V
CC
C
Supply for internal ”Signal” circuitry
Supply for Power section
10OUTHigh current totem pole output
11PGNDPower ground
12SGNDSignal ground
13ISENCurrent sense
14DISDisable. It must never be leftfloating. Tie to SGND if not used.
15DC-LIMConnecting this pin to Vref, DC is limitedto 50%. If it is left floating or grounded no limitation is
imposed
16NCNot connected
components
t,Rt
2/24
L4990 - L4990A
ELECTRICALCHARACTERISTICS
CC
= 15V; Tj=0 to 70°C; unless otherwisespecified.)
(V
SymbolParameterTest ConditionMin.Typ.Max.Unit
REFERENCE SECTION
V
O
T
S
Output VoltageTj=25°C; IO= 1mA4.9255.05.075V
Line RegulationV
Load RegulationI
= 12 to 20V2.015mV
CC
= 1 to 20mA5.020mV
O
Temperature Stability0.4mV/°C
Total VariationLine, Load,Temperature4.8755.05.125V
I
OS
Short Circuit CurrentVref = 0V30150mA
Power Down/UVLOV
The I.C. contains a standard PWM current mode
control section with improved performance with
respectto the UC384Xfamily.
Enhanced features include start-up bias current
reduced to < 270µA (typ), improved E/A performance (4MHz B/W, 1.3mA Source Current, highslew rate) accurate 1MHz oscillator, and also reduced propagation delays in the critical path from
Current Sense to Output.
4/24
ADDITIONALFEATURES
SoftStart (SS)
An external capacitor is charged by an internal
constant current source (20µA) to generate a SS
signal which clamps the E/A output
The SS pin doubles as a Fault Reset Delay function as describedbelow.
Current Limit/ Reset Delay
An internal high-speed current limit comparator
L4990 - L4990A
referenced to 1.2V detects primary over-current
conditions. On detection of an overcurrent fault
the output is immediately shutdown and the fault
is also latched. A Fault Reset Delay is implemented by discharging the external Soft Start
(SS) timing capacitor before resetting the fault
latch and initiating a softstart cycle.
In case of a continuous fault condition the SS capacitor is charged to 5V before being discharged
again, to ensure that the fault frequency does not
exceed the programmedsoft start frequency.
Duty CycleLimit
A simple connectionbetween the DC-LIM and the
available Vref activatesan internal T- FlipFlop limiting the DC to about 50%. If this pin is not connected or grounded, the limit of the duty cycle is
extended to about 100%
Duty CycleControl
Duty Cycle DC is externally programmed by setting a voltage between 1V (0% DC) and 3V
(100% DC) at the DC pin. The programmed voltage is compared with the oscillator C
capacitor
T
charging waveform to determine the maximum
ON-time in each period. This function gives a fine
control of DC.
If this pin is floating the maximum duty cycle depends on DC-LIM status.
Synchronization
A SYNC pin eases Synchronization of the IC to
the external world ( e.g. another IC working in
parallelor to TV/monitorsyncsignal).
In TV/monitor applications the timing components
,CTare set for a frequency lower than the
R
T
minimum TV sync frequency.When the TV circuit
has powered-up it takes over and the system frequencyis that of the SYNC. Duty Cycle is controllableusing the DC function.
In parallel operation of several IC’s no Master/Slavedesignationis requiredas the higherfrequency IC is automaticallythe master. Controllers
to be synchronized have their SYNC pins tied together and each SYNC pin operatesas a bidirectional circuit. The first IC to drive its SYNC pin is
the master and it initiates a discharge of the C
timing capacitor of every controller. The Sync input signal is edge-triggered and sets an internal
”sync latch” which ensures full discharge of C
.
T
DisableFunction
The DIS pin performs a logic level latched-shutdown function. When pulled above 2.5V it shuts
down the complete IC with a standby current of
<270µA(typ).
To reset the IC the V
pin must be pulled-down
CC
belowthe lower UVLO threshold (10V).
LeadingEdge Blanking (LEB)
An LEB interval of 100ns has been incorporated
into the IC to blank out the current sense signal
during the first 100ns from switch turn-on.
This provides noise immunity to turn-on spikes
and reduces external RC filteringrequirementson
the current-sensesignal.
T
Figure 1. Quiescentcurrent vs. input voltage.
(X = 7.6V and Y = 8.4V for L4990A)
Iq [mA]
30
20
8
6
1
0.8
0.6
0.4
0.2
0
0 4 8 12162024
V14 = 0, OSC=disabled
Tj = 25°C
X
Vcc [V]
Y
Figure2. Quiescentcurrentvs. input voltage
(after disable).
Iq [uA]
300
270
240
210
8 1012141618202224
Vcc [V]
V14 = Vref
Tj = 25°C
5/24
L4990 - L4990A
Figure 3. Quiescentcurrent vs. input voltage.
Iq [m A ]
9.0
V14 = 0, V5 = Vref
8.5
8.0
7.5
7.0
8 1012141618202224
igure5. Quiescentcurrent vs. input voltage
F
Iq [mA]
36
30
24
Rt = 4 .5 Kohm ,Tj = 2 5°C
1M hz
500Khz
300Khz
100Khz
Vcc [V]
and switching frequency.
Co = 1nF, Tj = 25°C
DC = 100%
1MHz
igure4. Quiescentcurrentvs. input voltage
F
and switching frequency.
Iq [mA]
36
30
24
18
12
6
0
8 10121416182022
Co = 1nF, Tj = 25°C
DC = 0%
1MHz
500KHz
300KHz
100KHz
Vcc [V]
Figure6. Referencevoltage vs. load current.
Vref [V]
5.1
5.05
Vcc=15V
Tj = 25°C
18
12
500KHz
300KHz
100KHz
6
0
8 10121416182022
Vcc [V]
Figure 7. Vref vs. junction temperature.
Vref [V])
5.1
5.05
5
4.95
Vcc = 15V
Iref = 1mA
5
4.95
4.9
0510152025
Iref [mA]
Figure8. Vref vs. junctiontemperature.
Vref [V]
5.1
Vcc = 15V
5.05
5
4.95
Iref= 20mA
4.9
-50-250255075100125150
Tj (°C)
6/24
4.9
-50-250255075100125150
Tj (°C)
L4990 - L4990A
Figure 9. Vref SVRR vs. switchingfrequency.
SVRR (dB)
120
80
40
0
110100100010000
fsw (Hz)
Vcc=15V
Vp-p=1V
Figure 11. Outputsaturation.
Vsat = V [V]
2.5
1.5
10
2
Vcc = 15V
Tj= 25°C
Figure10. Output saturation.
Vsat = V [V]
16
14
12
10
10
Vcc = 15V
Tj = 25°C
8
6
00.20.40.60.811.2
Isource [A]
Figure12. UVLO Saturation
Ipin10 [mA]
50
40
30
Vcc < Vccon
beforetu rn-on
1
0.5
0
00.20.40.60.811.2
Isink [A]
Figure13.Timingresistorvs.switchingfrequency.
fsw(KHz)
5000
2000
Vcc =15V,V15=0V
Tj= 25° C
1000
50 0
20 0
10 0
50
20
5.6nF
2.2nF
100p F
220pF
470pF
1nF
10
10203040
Rt (kohm)
20
10
0
02004006008001,000 1,200 1,400
Vpin10 [mV]
Figure14. Switchingfrequencyvs. temperature.
fsw (KHz)
320
Rt= 4.5Kohm, Ct = 1nF
310
300
290
280
-50-250255075100125150
Vcc = 15V, V15=Vref
Tj (°C)
7/24
L4990 - L4990A
Figure 15. Switchingfrequencyvs. temperature.
fsw (KHz)
320
Rt= 4.5Kohm, Ct = 1nF
310
300
290
280
-50-250255075100125150
Vcc = 15V,V15= 0
Tj (°C)
Figure 17. Maximum Duty Cycle vs Vpin3.
DC ControlVoltage Vpin3 [V]
3.5
V15 = Vref
3
2.5
V15 = 0V
Figure16. Dead time vs Ct.
Dead time[ns]
1,500
Rt=4.5Kohm
V15= 0V
1,200
900
V15= Vref
600
300
246810
TimingcapacitorCt [nF]
Figure18.Delaytooutputvsjunctiontemperature.
Delayto output (ns)
130
120
110
100
2
Rt = 4.5Kohm,
1.5
Ct = 1nF
1
0 102030405060708090100
Duty Cy cle [%]
Figure 19. E/A frequencyresponse.
G [dB]
150
100
50
0
0.010.11101001000 10000 100000
f(KHz)
Phase
140
120
100
80
60
40
20
90
80
70
60
-50-250255075100125150
Tj(°C)
PIN10=OPEN
1Vpulse
onPIN13
8/24
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