SGS Thomson Microelectronics L293DD, L293D Datasheet

PUSH-PULLFOUR CHANNEL DRIVER WITH DIODES
600mA OUTPUT CURRENT CAPABILITY PER CHANNEL
1.2A PEAK OUTPUT CURRENT (non repeti­tive) PER CHANNEL
ENABLEFACILITY OVERTEMPERATUREPROTECTION LOGICAL ”0” INPUT VOLTAGE UP TO 1.5 V
(HIGH NOISE IMMUNITY) INTERNALCLAMPDIODES
L293D
L293DD
SO(12+4+4) Powerdip (12+2+2)
DESCRIPTION
The Device is a monolithic integrated high volt­age, high current four channel driver designed to accept standard DTL or TTL logic levels and drive inductive loads (such as relays solenoides, DC and stepping motors) and switching power tran­sistors.
To simplify use as two bridges each pair of chan­nels is equippedwith an enable input. A separate supply input is provided for the logic, allowing op­eration at a lower voltage and internal clamp di­odes are included.
This device is suitable for use in switching appli­cations at frequenciesup to 5 kHz.
BLOCK DIAGRAM
ORDERING NUMBERS:
L293DD L293D
The L293D is assembled in a 16 lead plastic packaage which has 4 center pins connected to­getherand usedfor heatsinking
The L293DD is assembled in a 20 lead surface mount which has 8 center pins connected to­getherand usedfor heatsinking.
June 1996
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L293D - L293DD
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
S
V
SS
V
i
V
en
I
o
P
tot
T
stg,Tj
PIN CONNECTIONS (Top view)
Supply Voltage 36 V Logic Supply Voltage 36 V Input Voltage 7 V Enable Voltage 7 V Peak Output Current (100µs non repetitive) 1.2 A Total Power Dissipation at T
=90°C4W
pins
Storage and Junction Temperature – 40 to 150
C
°
SO(12+4+4)
Powerdip(12+2+2)
THERMAL DATA
Symbol Decription DIP SO Unit
R
th j-pins
R
th j-amb
R
th j-case
(*) With 6sq. cm on board heatsink.
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Thermal Resistance Junction-pins max. 14 Thermal Resistance junction-ambient max. 80 50 (*) Thermal Resistance Junction-case max. 14
C/W
°
C/W
°
L293D - L293DD
ELECTRICAL CHARACTERISTICS
(for each channel, V
=24V, VSS= 5 V, T
S
=25°C, unless
amb
otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
S
V
SS
I
S
I
SS
V
IL
V
IH
I
IL
I
IH
V
en L
V
en H
I
en L
I
en H
V
CE(sat)H
V
CE(sat)L
V
F
t
r
t
f
t
on
t
off
(*) See fig. 1.
Supply Voltage (pin 10) V
SS
Logic Supply Voltage (pin 20) 4.5 36 V Total Quiescent Supply Current
(pin 10)
Total Quiescent Logic Supply Current (pin 20)
Input Low Voltage (pin2, 9, 12,
Vi=L; IO=0; Ven=H 2 6 mA
=H; IO=0; Ven= H 16 24 mA
V
i
=L 4 mA
V
en
Vi=L; IO=0; Ven= H 44 60 mA
=H; IO=0; Ven= H 16 22 mA
V
i
= L 16 24 mA
V
en
– 0.3 1.5 V
19) Input High Voltage (pin 2, 9,
12, 19) Low Voltage Input Current(pin
7 V 2.3 V
V
SS
> 7 V 2.3 7 V
V
SS
VIL= 1.5 V – 10 µA
2, 9, 12, 19) High Voltage Input Current (pin
2.3 V VIH≤ VSS– 0.6 V 30 100 µA
2, 9, 12, 19) Enable Low Voltage
– 0.3 1.5 V
(pin 1, 11) Enable High Voltage
(pin 1, 11) Low Voltage Enable Current
VSS≤ 7 V 2.3 V
> 7 V 2.3 7 V
V
SS
V
= 1.5 V – 30 – 100 µA
en L
(pin 1, 11) High Voltage Enable Current
2.3 V V
VSS– 0.6V ± 10 µA
en H
(pin 1, 11) Source Output Saturation
IO= – 0.6A 1.4 1.8 V
Voltage (pins 3, 8, 13, 18) Sink Output Saturation Voltage
IO= + 0.6 A 1.2 1.8 V
(pins 3, 8, 13, 18) Clamp Diode Forward Voltage IO= 600nA 1.3 V Rise Time (*) 0.1 to 0.9 V Fall Time (*) 0.9 to 0.1 V
O O
Turn-on Delay (*) 0.5 Vito 0.5 V Turn-off Delay (*) 0.5 Vito 0.5 V
O O
250 ns 250 ns 750 ns 200 ns
36 V
SS
SS
V
V
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