16 STAGEBINARI COUNTER
LOWSYMMETRICALOUTPUT RESISTANCE,
TYPICALLY 100 OHM ATVDD=15V
OSCILLATOR FREQUENCY RANGE : DC TO
100kHz
AUTOOR MASTER RESET DISABLES OSCILLATORDURINGRESET TOREDUCE POWER
DISSIPATION
OPERATESWITH VERY SLOW CLOCK RISE
AND FALL TIMES
BUILT-INLOW-POWER RC OSCILLATOR
EXTERNAL CLOCK (applied to pin 3) CAN BE
USEDINSTEAD OF OSCILLATOR
OPERATESAS 2NFREQUENCY DIVIDER OR
AS A SINGLE-TRANSITION TIMER
Q/Q SELECT PROVIDES OUTPUT LOGIC
LEVELFLEXIBILITY
CAPABLEOF DRIVINGSIXLOW POWERTTL
LOADS, THREE LOW-POWER SCHOTTKY
LOADS, PR SIX HTL LOADS OVER THE
RATEDTEMPERATURE RANGE
SYMMETRICALOUTPUTCHARACTERISTICS
100% TESTED FOR QUIESCENT CURRENT
AT 20V
5-10-15VPARAMETRICRATINGS
MEETSALLREQUIREMENTSOFJEDECTENTATIVESTANDARD N13A, ”STANDARDSPECIFICATIONS FOR DESCRIPTION OF ’ B ’
SERIESCMOS DEVICES”
HCC4 54 1B
HCF4541B
PROGRAMMABLE TIMER
EY
(Plastic Package)
M1
(Micro Package)
ORDER CODE S :
HCC 4541 BFHCF4541 BM 1
HCF4541 BE YHCF4541 BC1
PIN CO NNECTION (top vie w)
(Ceramic Frit Seal Package)
(Plastic Chip Carrier)
F
C1
DESCRI PTION
TheHCC/HCF4541B Programmable Timeriscomposed of a 16-stage binary counter, an oscillator
controlled by2 externalresistorsand a capacitor,an
output control logic and an automatic power-on
reset circuit. The counter varies on positive-edge
clocktransation and it can be cleared by the MASTER RESETinput.The outputfrom thistimer is the
Q or Q output from the 8th, 13th, or 16th counter
stage.Thechoice ofthestagedepends on thetimeselectinputsA or B (seefrequency selection table).
The output isavailable inone ofthe two modes that
can be selected via the MODE input, pin 10 (see
truth table). The output turns out as a continuous
squarewave,with afrequencyequaltotheoscillator
frequency divided by 2N. When this MODE input is
November1996
1/11
HCC/HCF4541B
a logic” 1 ”, whenit is a logic ” 0 ” andafter a MASTER RESET is started, and Q output has been selected, the output goes up to a high stateafter 2
N-1
counts.It remainsin thatstate till anotherMASTER
RESETpulse is apply or the mode inputis a logic ”
1 ”. Theprocess starts bysettingtheAUTO RESET
input(pin 5) to logic ” 0 ” and switching poweron. If
pin 5 is setto logic ”1 ”, the AUTORESETcircuitis
not enabled and counting cannot start till a positive
MASTERRESETpulse isapplied, returningtoalow
level. The AUTO RESET consumes a remarkable
RC OscillatorCircuit.
amount of power and should not be used if lowpoweroperation is wanted.
The frequency of the oscillator depends on the RC
network. Itcanbe calculated usingthefollowing formula:
f =
1
2.3 RTCC
TC
wheref is between 1 kHz and 100 kHz
and RS ≥ 10 kΩ and ≈ 2R
TC
FUNCTIONAL DIAGRAM
2/11
HCC/HCF4541B
ABSOLU TE M AXIMU M R AT INGS
SymbolParameterValueUnit
*Supply Voltage: HCC Types
V
DD
HCF Types
Input Voltage– 0.5to VDD+ 0.5V
V
I
I
DC Input Current (anyone input)± 10mA
I
Total Power Dissipation (perpackage)
P
tot
Dissipation per Output Transistor
for T
= FullPackage-temperature range
op
T
Operating Temperature : HCC Types
op
HCF Types
T
Storage Temperature– 65to + 150°C
stg
Stresses above those listed under ” Absolute Maximum Ratings ” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
* All voltages are with respect to VSS(GND).
The Noise Margin for both ” 1 ” and ” 0 ” level is : 1V min. with VDD= 5V 2V min. with VDD= 10V 2.5V min. with VDD=15V
T
Low
25°CT
High
Min. Max. Min. Typ. Max. Min. Max.
–
± 0.1
± 0.1± 1µA
5
Unit
µA
V
V
V
V
mA
mA
4/11
HCC/HCF4541B
DYNAMICELECTRICAL CHARACTERISTICS (T
=25°C, CL= 50pF, RL=200kΩ,
amb
typicaltemperature coefficient for allVDDvalues is 0.3%/°C, all input riseand fall time = 20ns)
SymbolParameter
8
(2
)
Propagation Delay Time
t
Clock toQ
PHL
t
PLH
16
)
(2
t
PHL
t
PLH
Transition Time5100200
t
THL
t
TLH
Master Reset,Clock Pulse Width5900300
f
Maximum Clock Pulse Input Frequency51.5
CL
tr,tfMaximum Clock Pulse InputRise or FallTime5
VDD
(V)
53.510.5
101.253.8
150.92.9
5618
103.510
152.57.5
1050100
154080
5180360
1090180
1565130
10300100
1522585
104
156
10
15
Values
Min.Typ.Max.
Unlimitedµs
Unit
µs
µs
ns
ns
MHz
5/11
HCC/HCF4541B
DIGITAL TIMER A PPLICATION
A positive MASTER RESET pulse clears the
counters andlatch.The outputgoeshighand keeps
up tillthenumber ofpulses,selected byAandB, are
counted.Thiscircuitis retriggerable andisas accurate as theinputfrequency. If amoreaccuratecircuit
is desired, an external clock can be used on pin 3.
A set-uptime equal tothe width oftheone shot output is required immediately following initial power
up, during which time theoutput will be high.
FREQUENC Y S ELECT ION TA BL ETRUTH TABLE
AB
00138192
01101024
1018256
111665536
N°of Stages
N
Count
N
2
Pin
5Auto Reset OnAutoReset Disable
6MasterReset OffMaster Reset On
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such informationnor for any infringement of patents or other rights of third parties which may results from its use. No
licenseis grantedby implication or otherwise under any patentor patent rights of SGS-THOMSONMicroelectronics. Specifications mentioned
in this publication aresubject to changewithout notice. Thispublication supersedes and replacesall informationpreviouslysupplied.
SGS-THOMSONMicroelectronics products are not authorized for use ascriticalcomponents in lifesupport devices or systemswithout express
writtenapproval ofSGS-THOMSON Microelectonics.