TTLLOADS,ONELOWER-POWER
SCHOTTKY LOAD, OR TWO HTL LOADS
OVER THE RATED TEMPERATURE RANGE
.STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
.QUIESCENT CURRENTAT 20VFORHCCDE-
VICE
.5V, 10V, AND 15V PARAMETRIC RATINGS
.INPUTCURRENTOF100nAAT18VAND25°C
FOR HCC DEVICE
.100% TESTEDFOR QUIESCENTCURRENT
.MEETSALLREQUIREMENTSOFJEDECTEN-
TATIVE STANDARD No. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIESCMOS DEVICES”
EY
(Plastic Package)
(ChipCarrier)
ORDERCODES :
HCC 4536BFHCF4536BEY
PIN CONNECTIONS
(CeramicPackage)
C1
HCF4536BC1
F
DESCRIPT ION
TheHCC4536B(extended temperature range) and
HCF4536B (intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package. The
HCC/HCF4536B is a programmable timer consisting of 24 ripple-binary counter stages.Thesalient
featureof this device is its flexibility. The devicecan
count from 1 to 224or the first 8 stages can be bypassed to allow an output, selectable by a 4-bit code, from any oneof the remaining 16 stages. It can
be driven by an external clock or an RC oscillator
that canbe constructedusing on-chip components.
November1996
1/17
HCC/HCF4536B
InputIN1serves as either theexternal clockinputor
the input to the on-chip RC oscillator. OUT1 and
OUT2 are connection terminalsfor the external RC
components.Inaddition,anon-chipmonostablecircuit is provided to allow a variable pulse widthoutput. Various timing functionscan be achieved using
combinations of these capabilities. A logic 1 on the
8-BYPASS input enables a bypass of the first 8 stages and makes stage 9 the firstcounterstageof the
last16stages.Selection of1of16 outputsisaccomplished by the decoder andthe BCD inputs A, B, C
FUN CTIONAL DI AG R A M
and D. MONO IN is the timing input for the on-chip
monostable oscillator. Grounding of the MONO IN
terminalthrough a resistor of10KΩ or higher, disables the one-shot circuitand connects the decoder
directly to the DECODE OUT terminal. A resistorto
VDDand a capacitor to ground from the MONO IN
terminalenables theone-shot circuitand controls its
pulse width. A fast test mode is enabled by a logic
1 on 8-BYPASS, SET, and RESET. This mode divides the 24-stage counter into three 8-stagesections to facilitate a fast test sequence.
ABSOLUTE MAXIMUM RAT IN G S
SymbolParameterValueUnit
V
*Supply Voltage : HCC Types
DD
V
Input Voltage– 0.5 to VDD+ 0.5V
i
I
DC Input Current (any one input)± 10mA
I
P
T
T
Stresses abovethose listed under”Absolute MaximumRatings”may cause permanent damage tothe device. Thisisa stressrating onlyand
functionaloperation of the device at theseor any other conditions abovethose indicated intheoperational sectionsof thisspecification is not
implied.Exposure toabsolutemaximum ratingconditionsforexternal periods may affectdevice reliability.
* All voltages are withrespect to VSS(GND).
2/17
Total Power Dissipation (per package)
tot
Dissipation per Output Transistor
for Top= Full Package-temperature Range
TypicalDynamic Power Dissipation vs. Input
Pulse Frequency.
TypicalPulse Width vs. ExternalCapacitance
(VDD= 15V).
TYPICAL APPLI CA TI ONS
Time InternalConfiguration Using External Clock
; Setand Clock Inhibit Functions.
10/17
TimeInternal Configuration Using External Clock
; Resetand Output Monostable to Achieve a
Pulse Output.
TYPICAL APPLI CA TI ONS ( Continued)
HCC/HCF4536B
Time Internal Configuration UsingOnchip RCOscillator and Reset Input to Initiate TimeInterval.
Application Showing Use of 4098B and 4536B to
get DecodePulse 8 ClockPulses after Reset
TIMING DIAGRAM
11/17
HCC/HCF4536B
Functional Tes t Sequence
InputsOutputsComments
In 1Se tR eset8- Bypass
10110
11110
01110First ”1” to ”0” Transition of Clock
1
0
–
–
01111The 255 ”1” to ”0” Transition
00001
10001In
00000Counter Ripples from an all ”1” state to an all ”0”
111
Decade Out
Q 1 Thru Q 24
All 24 step s a re in rese t mo de.
Counter is in three 8-stage section in parallel
mode.
255 ”1” to ”0” transitions are clocked in the
counter.
Counter converted back to 24 stages in series
mode.
Set and Reset must be connected together and
simultaneoulsy go from ”1” to ”0”.
switches to a ”1”.
1
state.
FUNCTIONAL TEST SEQUENCE
TestFunction hasbeenincluded forthereduction of
test timerequired to exerciseall 24 counterstages.
This test function divides the counter into three 8stage section and255 counts are loadedin eachof
the 8-stagesectionsin parallel. Allflip-flopsarenow
TEST CIRCUITS
at a ”1”. The counter is now returned to the normal
24-steps in series configuration. One more pulse is
enteredintoIn1whichwillcausethecounter toripple
from an all ”1” stateto an all ”0” state.
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may results from its use. No
licenseis granted by implication orotherwise under any patentor patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned
in thispublication are subject tochange withoutnotice. Thispublicationsupersedes andreplacesall information previously supplied.
SGS-THOMSONMicroelectronics products are not authorized for use as criticalcomponents in lifesupport devices or systemswithoutexpress
writtenapproval ofSGS-THOMSONMicroelectonics.
1996SGS-THOMSONMicroelectronics - Printedin Italy- All RightsReserved
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