HCF4510B
PRESETTABLE UP/DOWN COUNTERS
■ MEDIUMSPEED OPERATIONf
TYP.AT10V
■ SYNCHRONOUS INTERNAL CARRY
PROPAGATION
■ RESETAND PRESETCAPABILITY
■ QUIESCENTCURRENTSPECIFIEDTO 15V
■ 5V,10V,AND15VPARAMETRICRATINGS
■ INPUTCURRENTOF100nAAT 15VAND25°C
■ 100%TESTED FORQUIESCENTCURRENT
MEETS ALL REQUIREMENTS OF JEDEC
TENTATIVE STANDARD No. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIESCMOS DEVICES”
DESCRIPTION
The HCF4510B and HCF4516B are monolithic
integrated circuits available in 16-lead dual in-line
plastic and plastic micro package. The
HCF4510B Presettable BCD Up/Down Counter
and the HCF4516B Presettable Binary Up/Down
Counter consist of four synchronously clocked
D-typeflip-flops (witha gating structureto provide
T-type flip-flop capability) connected as counters.
These counterscan be clearedby a high level on
the RESET line, and can be preset to any binary
number presenton the jam inputs by a high level
on the PRESET ENABLE line. The HCF4510B
will count out of non-BCD counter states in a
maximum of two clock pulses in the up mode,
=8MHz
CL
HCF4516B
SOPDIP
ORDER CODES
PACK AG E TUBE T & R
DIP HCF45XXBEY
SOP HCF45XXBM1 HCF45XXM013TR
and a maximum of four clock pulses in the down
mode. If the CARRY-IN input is held low, the
counter advances up or down on each
positive-going clock transition. Synchronous
cascading is accomplished by connecting all
clock inputs in parallel and connecting the
CARRY-OUT of a less significant stage to the
CARRY-IN of a more significant stage. The
HCF4510B and HCF4516B can be loaded in the
ripple mode by connecting the CARRY-OUT to
the clockof the next stage. IftheUP/DOWN input
changes during a terminal count, the
CARRY-OUT must be gated with the clock, and
the UP/DOWN input must change while the clock
is high. This method providesa cleanclock signal
to the subsequentcounting stage.
PIN CONNECTION
March 2000
1/12
HCF4510B/4515B
FUNCTIONAL DIAGRAM
TRUTH TABLE
CL CI U/D PE R Action
X 1 X 0 0 No Count
X X X 1 0 Preset
XXXX1Reset
X=Don’tcare
0100Count Up
0000Count Down
ABSOLUTE MAXIMUMRATING
Symb o l Parameter Val u e Uni t
* Supply Voltage -0.5 to +18 V
V
DD
Input Voltage -0.5 to VDD+ 0.5 V
V
i
DC Input Current (any one input)
I
I
Total Power Dissipation (per package)
P
tot
10 mA
±
200
mW
Dissipation per Output Transistor
for Top = Full Package Temperature Range
Operating Temperature -40 to +85
T
op
Storage Temperature -65 to +150
T
stg
Stressesabove those listedunder ”Absolute Maximum Ratings” may cause permanent damage tothe device. This isa stress rating only and functional
operation ofthe device atthese or any other conditions above thoseindicated inthe operational sectionsof this specification is no t implied.Exposure to
abso lute maximumratingconditions for externalpe riodsmayaffectdevicerel iab ilit y.
*Allvoltagevalues arereferredtoV
pinvoltage.
SS
100
mW
o
C
o
C
RECOMMENDED OPERATINGCONDITIONS
Symb o l Parameter Val u e Uni t
V
Supply Voltage 3 to 15 V
DD
Input Voltage 0 to V
V
I
Operating Temperature -40 to +85
T
op
DD
V
o
C
2/12
LOGICDIAGRAMS
4510B
HCF4510B/4516B
4516B
3/12
HCF4510B/4515B
TIMINGDIAGRAMS
4510B
4516B
4/12
HCF4510B/4516B
STATICELECTRICAL CHARACTERISTICS
(over recommended operating conditions)
Symb o l Parameter Test Con diti o s Va lue Uni t
V
|I
|
V
I
(V)
Quiescent Current 0/5 5 20 0.02 20 150
I
L
O
(V)
O
(µA)
V
(V)
DD
o
-40
C25
Mi n . M ax. Min. Typ. Max. M in. M ax.
0/10 10 40 0.02 40 300
o
C85
o
C
µ
0/15 15 80 0.02 80 600
V
OH
Output High
Voltage
0/5 < 1 5 4.95 4.95 4.95
0/10 < 1 10 9.95 9.95 9.95
0/15 < 1 15 14.95 14.95 14.95
V
OL
Output Low
Voltage
5/0 < 1 5 0.05 0.05 0.05
10/0 < 1 10 0.05 0.05 0.05
15/0 < 1 15 0.05 0.05 0.05
V
IH
Input High
Voltage
0.5/4.5 < 1 5 3.5 3.5 3.5
1/9 < 1 10 7 7 7
1.5/13.5 < 1 15 11 11 11
V
IL
Input Low
Voltage
4.5/0.5 < 1 5 1.5 1.5 1.5
9/1 < 1 10 3 3 3
13.5/1.5 < 1 15 4 4 4
I
OH
Output Drive
Current
0/5 2.5 5 -1.53 -1.36 -3.2 -1.1
0/5 4.6 5 -0.52 -0.44 -1 -0.36
mA
0/10 9.5 10 -1.3 -1.1 -2.6 -0.9
0/15 13.5 15 -3.6 -3.0 -6.8 -2.4
Output Sink Current 0/5 0.4 5 0.52 0.44 1 0.36
I
OL
0/10 0.5 10 1.3 1.1 2.6 0.9
mA
0/15 1.5 15 3.6 3.0 6.8 2.4
I
IH,IIL
Input Leakage
Current
Input Capacitance Any Input 5 7.5
C
I
TheNoiseMarginforboth”1” and ”0” levelis:1V min.withVDD=5 V,2V min.withVDD=10V,2.5Vmin.withVDD=15V
0/15 Any
Input
15
±
0.3
-5
0.3
10
±
±
1
±
µ
pF
A
V
V
V
V
A
5/12
HCF4510B/4515B
DYNAMICELECTRICAL CHARACTERISTICS
typicaltemperaturecoefficentfor all V
valuesis 03%/oC, all inputrise andfall times=20 ns)
DD
=25oC, CL=50pF,RL= 200KΩ,
(T
amb
Symb o l P a rameter Test Con diti o ns Val u e Uni t
V
Min. Typ. Max.
DD
(V)
t
Propagation Delay Time Clock to Q Output 5 200 400
t
PHL
PLH
10 100 200
ns
15 75 150
t
Propagation Delay Time Preset or Reset to
PHL
t
Q Output
PLH
5 210 420
10 105 210
ns
15 80 160
t
Propagation Delay Time Clock to Carry Out 5 240 480
PHL
t
PLH
10 120 240
ns
15 90 180
t
Propagation Delay Time Carry In to Carry
PHL
t
Out
PLH
5 125 250
10 60 120
ns
15 50 100
t
Propagation Delay Time Preset or Reset to
PHL
Carry Out
t
PLH
5 320 640
10 160 320
ns
15 125 250
t
Transition Time 5 100 200
THL
t
TLH
10 50 100
ns
15 40 80
f
Max Clock Frequency 5 2 4
MAX
10 4 8
MHz
15 5.5 11
t
Clock Pulse Width 5 150
W
10 75
ns
15 60
Preset Enable or Reset Removal Time (1) 5 150
10 80
ns
15 60
t
Clock Rise and Fall Time (2) 5 15
r,tf
10 5
s
µ
15 5
t
Carry In Setup Time 5 130
setup
10 60
ns
15 45
t
Up Down Setup Time 5 360
setup
10 160
ns
15 110
t
Preset Enable or Reset Pulse Width 5 220
W
10 100
ns
15 75
(1) Timerequired afterthefalling edge of the reset or preset enable inutsbefore the risingedge of theclock willtriggerthe counter (similarto setuptime).
(2) Ifmore than unitis cascated inthe parallel clocked application, trCL should be made less than orequal to thesum of thefixed propagation delay at
15pFandthetransitiontimeofthecarryoutputdrivingstageoftheestimatedcapacitive load.
6/12
HCF4510B/4516B
TypicalOutput Low (sink) Current
Characteristics.
TypicalOutput High (source)Current
Characteristics.
MinimumOutput Low (sink) Current
Characteristics.
MinimumOutput High (source) Current
Characteristics.
TypicalPropagationDelay Time vs.Load
Capacitancefor Clock to Q Output.
TypicalMaximum Clock Input Frequencyvs.
SupplyVoltage.
7/12
HCF4510B/4515B
Typical TransitionTime vs. Load Capacitance. Typical Dynamic PowerDissipation vs.
Frequency.
TYPICALAPPLICATIONS
TYPICAL16-CHANNEL, 10 BITDATA ACQUISITION SYSTEM
Thisacquisitionsystem can be operated in the random access mode by jamming in thechannel number at the present inputs, or in the sequential mode
byclockingtheHCF4516B.
8/12
CASCADINGCOUNTERPACKAGES
TESTCIRCUITS
HCF4510B/4516B
QuiescentDevice Current.
InputLeakage Current.
Noise Immunity.
PowerDissipationand Input Waveform.
9/12
HCF4510B/4515B
Plastic DIP-16 (0.25) MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
mm inch
10/12
P001C
SO-16 MECHANICALDATA
HCF4510B/4516B
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.004 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45 (typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024
S 8 (max.)
mm inch
P013H
11/12
HCF4510B/4515B
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12/12
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