SGS Thomson Microelectronics HCF4046B Datasheet

MICROPOWER PHASE-LOCKED LOOP

.QUIESCENT CURRENT SPECIFIED TO 20V

FOR HCC DEVICE

.VERY LOW POWER CONSUMPTION : 100µW

(TYP.) AT VCO fo= 10kHz, VDD=5V

.OPERATING FREQUENCY RANGE : UP TO

1.4MHz(TYP.) AT VDD=10V

.LOWFREQUENCYDRIFT : 0.06%/°C (typ.)AT

VDD=10V

.CHOICE OF TWO PHASE COMPARATORS :

1) EXCLUSIVE - OR NETWORK

2)EDGE-CONTROLLEDMEMORY NETWORK
WITH PHASE-PULSE OUTPUT FORLOCK IN­DICATION

.HIGH VCO LINEARITY: 1%(TYP.)

.VCO INHIBIT CONTROL FOR ON-OFF KE-

YING AND ULTRA-LOW STANDBY POWER
CONSUMPTION

.SOURCE-FOLLOWER OUTPUT OF VCO

CONTROL INPUT(demod. output)

.ZENERDIODETO ASSIST SUPPLY REGULA-

TION

.5V, 10V AND 15V PARAMETRIC RATING

.INPUT CURRENTOF100nAAT18V AND 25°C

FOR HCC DEVICE

.100% TESTEDFOR QUIESCENTCURRENT

.MEETSALLREQUIREMENTSOFJEDECTEN-

TATIVE STANDARD N°. 13A, ”STANDARD
SPECIFICATIONSFOR DESCRIPTIONOF ”B”
SERIESCMOS DEVICES”

HCC/HCF4046B

EY

(Plastic Package)

C1

(ChipCarrier)

ORDERCODES :

HCC4046BF HCF4046BEY

PIN CON NEC TIONS

F

(CeramicPackage)

HCF4043BC1

DESCRIPTION
TheHCC4046B(extended temperature range) and

HCF4046B (intermediate temperature range) are

monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package. The
HCC/HCF4046B COS/MOS Micropower Phase­Locked Loop (PLL) consists of a low-power, linear
voltage-controlled oscillator(VCO)andtwodifferent
phase comparators having a common signal-input
amplifier and a common comparator input. A 5.2V
zener diode is provided for supply regulation if
necessary.

June 1989

1/13

HCC/HCF4046B

VCO Section

The VCO requires one external capacitor C1 and
one ortwoexternal resistors(R1or R1andR2).Re­sistorR1 andcapacitorC1 determine the frequency
range of the VCO andresistor R2 enablestheVCO
tohavea frequencyoffsetif required.The highinput
impedance(10

12Ω

)oftheVCOsimplifiersthedesign
of low-pass filters by permitting the designer a wide
choice of resistor-to-capacitor ratios. In order not to
loadthelow-passfilter,asource-followeroutputofthe
VCO input voltage is provided at terminal 10 (DE­MODULATED OUTPUT). If this terminal is used, a
load resistor (RS)of10kΩor more should be con-
nectedfromthisterminalto VSS. Ifunused this termi­nal shouldbeleftopen. TheVCOcanbeconnected
either directly or through frequency dividers to the
comparator input of the phase comparators. A full
COS/MOSlogicswingis availableattheoutputofthe
VCO and allows direct coupling to COS/MOS fre­quency dividers such as the HCC/HCF4024B,

HCC/HCF4018B, HCC/HCF4020B,
HCC/HCF4022B, HCC/HCF4029B,and
HBC/HBF4059A. One or more HCC/HCF4018B

(Presettable Divide-by-N Counter) or HCC/HCF4029B
(Presettable Up/Down Counter), or HBC/HBF4059A
(Programmable Divide-by-”N” Counter), together
withtheHCC/HCF4046B(Phase-Locked Loop)can
be used to build a micropowerlow-frequency syn­thesizer.Alogic0 on theINHIBITinput”enables” the
VCO and the source follower, whilea logic 1 ”turns
off” both to minimize stand-bypower consumption.

Phase Comparators

The phase-comparator signal input (terminal 14)
can be direct-coupled provided the signal swing is
within COS/MOS logic levels [logic ”0” ≤ 30 %
(VDD–VSS), logic ”1” ≥ 70 % (VDD-VSS)]. For
smaller swings the signal must be capacitively
coupled to the self-biasing amplifier at the signal
input. Phase comparator I is an exclusive-OR net­work;it operates analagously to an over-driven bal­anced mixer. To maximize the lock range, the
signal-and comparator-input frequencies musthave
a 50% dutycycle.With nosignal ornoiseon the sig­nal input, this phase comparator has an average
output voltage equal to VDD/2. The low-pass filter
connected to the outputof phase comparator I sup­plies the averaged voltage to the VCO input, and
causes the VCO to oscillate at thecenter frequency
(fo). The frequency range of input signals on which
the PLLwilllockifitwas initiallyoutof lock isdefined
asthefrequencycapturerange(2fc).Thefrequency
range of input signals on which the loop will stay
lockedif it was initially in lock is defined as the fre­quencylockrange (2 fL). The capturerange is≤ the

lock range. With phase comparator I the range of
frequencies over which the PLL can acquire lock
(capture range) is dependent on the low-pass-filter
characteristics, and can be made as large as the
lockrange.Phase-comparator I enablesaPLL sys­tem to remain in lock in spite of high amounts of
noise in the input signal. One characteristic of this
type of phase comparator is that it may lock onto
input frequencies that are close to harmonics of the
VCO center-frequency. A second characteristic is
that the phase angle between the signal and the
comparator input varies between 0° and 180°, and
is 90° at the center frequency. Fig. (a) shows the
typical, triangular, phase-to-output response char­acteristicofphase-comparator I.Typical waveforms
for a COS/MOS phase-locked-loop employing
phasecomparatorIinlockedconditionoffoisshown
infig.(b).Phase-comparator II isanedge-controlled
digital memory network. It consists of four flip-flop
stages,control gating, and a three-stage output-cir­cuitcomprising p- and n-type drivers having a com­mon output node. When the p-MOS or n-MOS
driversareONtheypulltheoutputuptoVDDordown
to VSS, respectively.Thistype of phase comparator
acts only on the positive edges of the signal and
comparator inputs. The dutycyclesofthesignaland
comparator inputs are not important since positive
transitionscontrol the PLL systemutilizing thistype
ofcomparator.Ifthe signal-input frequency ishigher
than the comparator-input frequency, the p-type
outputdriverismaintainedONmostofthe time,and
both the n- and p-driversOFF (3 state)the remain­der of the time.If the signal-input frequency is lower
than the comparator-input frequency, the n-type
outputdriverismaintainedONmostofthe time,and
both the n- and p-driversOFF (3 state)the remain­der of the time. If the signal and comparator-input
frequencies are the same, but the signalinput lags
the comparator input in phase, the n-type output
driver is maintained ONfor a time corresponding to
the phase difference. If the signal and comparator­inputfrequencies are thesame, but the comparator
input lags the signal in phase, the p-type output
driver is maintained ONfor a time corresponding to
the phase difference. Subsequently, the capacitor
voltageofthe low-passfilterconnected tothisphase
comparator is adjusted until the signal and com­parator inputs are equal in both phase and fre­quency. Atthisstablepoint bothp-andn-type output
drivers remainOFFand thusthe phasecomparator
outputbecomes an open circuitand holds the volt­age on the capacitor of the low-pass filter constant.
Moreover the signal at the ”phase pulses” output is
ahighlevelwhichcanbe usedforindicatinga locked
condition. Thus, for phase comparator II, no phase
difference exists between signal and comparator

2/13

HCC/HCF4046B

inputover the full VCO frequencyrange. Moreover,
the powerdissipation dueto thelow-passfilter is re­duced when thistype of phase comparator is used
because both the p- and n-type output drivers are
OFF for most of the signal input cycle. It should be
notedthat the PLL lock range for this type of phase

Figure a : Phase-Comparator I Characteristics at

Low-Pass Filter Output.

comparator is equal to the capture range, inde­pendent ofthelow-pass filter.Withnosignalpresent
at the signal input,the VCO is adjustedto itslowest
frequency for phase comparator II. Fig. (c) shows
typical waveforms for a COS/MOSPLL employing
phasecomparator II in a locked condition.

Figureb :TypicalWaveformsfor COS/MOSPhase

Locked-Loop Employing Phase Com­parator I in Locked Condition of f

o.

Figure C : Typical Waveforms For COS/MOS Phase-locked Loop Employing Phase Comparator II In

LockedCondition.

3/13

HCC/HCF4046B

FUN CTIONAL DI AGRAM

V

DD

S-2299

ALL INPUTS ARE PROTECTED BY
COS/MOS PROTECTION NETWORK

V

SS

ABSOLUTE M AXI MU M RATINGS

Symbol Parameter Val ue Unit

V

* Supply Voltage : HCC Types

DD

HCF Types

V

Input Voltage – 0.5 to VDD+ 0.5 V

i

DC Input Current (any one input) ± 10 mA

I

I

P

Total Power Dissipation (per package)

tot

– 0.5 to + 20
– 0.5 to + 18

200

V
V

mW
Dissipation per Output Transistor
for T

T

T

Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltage values are referred to VSSpin voltage.

Operating Temperature : HCC Types

op

Storage Temperature – 65 to + 150 °C

stg

= Full Package-temperature Range

op

HCF Types

100

–55to+125

–40to+85

mW

°C
°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

V

T

Supply Voltage :HCC Types

DD

HCF Types

V

Input Voltage 0 to V

I

Operating Temperature : HCC Types

op

HCF Types

3to18
3to15

DD

– 55 to + 125

–40to+85

V
V

V

°C
°C

4/13