40160B - DECADE WITH ASYNCHRONOUS
CLEAR
40161B - BINARY WITH ASYNCHRONOUS
CLEAR
40162B - DECADE WITH SYNCHRONOUS
CLEAR
40163B - BINARY WITH SYNCHRONOUS
CLEAR
.INTERNAL LOOK-AHEADFOR FAST COUNT-
ING
.CARRY OUTPUT FOR CASCADING
.SYNCHRONOUSLY PROGRAMMABLE
.LOW-POWER TTL COMPATIBILITY
.STANDARDIZEDSYMMETRICALOUTPUT
CHARACTERISTICS
.QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
.5V, 10V AND 15V PARAMETRIC RATINGS
.INPUT CURRENTOF100nAAT18VAND 25oC
FOR HCC DEVICE
.100% TESTEDFOR QUIESCENTCURRENT
.MEETSALLREQUIREMENTSOFJEDECTEN-
TATIVE STANDARD N. 13A, ” STANDARD
SPECIFICATIONS FOR DESCRIPTION OF B
SERIESCMOS DEVICES ”
HCC/HCF40160B-40161B
HCC/HCF40162B-40163B
EY
(PlasticPackage)
M1
(MicroPackage)
ORDER CODES :
HCC40XXXBFHCF40XXX BEY
(CeramicPackage)
HCF40XXX BC1
F
C1
(Chip Carrier)
DESCRIPTION
The HCC40160B, 40161B, 40162B, 40163B (ex-
tended temperature range) and HCF40160B,40161B, 40162B, 40163B (intermediate temperature range) are monolithic integrated circuits,available in 16-lead dual in line plastic or ceramic
package and plastic micropackage.
HCC/HCF40160B, 40161B, 40162B and 40163B
are4-bitsynchronous programmable counters. The
CLEAR function of the HCC/HCF40162B and40163Bissynchronousand a low ontheat the clear
CLEAR input sets all four outputs low on the next
positiveCLOCK edge. The CLEAR function of the
HCC/HCF40160B and 40161B is asynchronous
and alowlevel at the CLEAR inputsets allfour outputs low regardless of the state of the CLOCK,
LOAD or ENABLEinputs. A low level at theLOAD
inputdisables thecounter and causes the output to
agree with the set-up data after the next CLOCK
pulseregardless oftheconditions oftheENABLE in-
September 1988
PIN CONNECTIONS
1/15
HCC/H CF40160B-40161B-40162-40163
cascadingcounter for n-bit synchronour application
without additional gating. Instrumental in accomplishing this function are two count-enable input
and a carry output (COUT). Counting is enable
when bothPE and TEinputs arehigh. The TEinput
is fed forward to enable COUT. This enableoutput
produces apositive outputpulsewith a durationapproximately equal to the positiveportion of the Q1
output. This positive overflow carry pulse can be
used to enable successive cascadedstages. Logic
transitionsat the PE or TE inputs may occurwhen
the clock is eitherhigh orlow.
ABSOLU TE MAXIMUM RATI NG
SymbolParameterValueUnit
*Supply Voltage: HCC Types
V
DD
HCF Types
V
P
Input Voltage-0.5 to VDD+ 0.5V
i
I
DC Input Current (any one input)± 10mA
I
Total Power Dissipation (per package)
tot
Dissipation per Output Transistor
for Top = Full Package Temperature Range
T
Operating Temperature: HCC Types
op
HCF Types
T
Stressesabove thoselistedunder ”Absolute Maximum Ratings”maycause permanent damage tothedevice. Thisisa stressratingonly and functional
operationofthedevice atthese or anyother conditions above thoseindicated intheoperational sections of thisspecification is not implied.Exposure
to absolute maximum rating conditions forexternal periods may affect device reliability.
* All voltagevalues are referred to VSSpinvoltage.
TheNoiseMargin for both”1” and”0” levelis: 1Vmin.withVDD=5V, 2 V min.with VDD=10 V,2.5 V min. withVDD=15V
Input CapacitanceAny Input57.5pF
I
=-55oCforHCC device: -40oC for HCF device.
=+125oCforHCC device: +85oC for HCF device.
HCC
Types
HCC
Types
0/18
18±0.1±10
Any Input
0/1515±0.3±10
-5
±0.1±1
-5
±0.3±1
HIGH
Unit
*
µA
V
V
V
V
mA
mA
µA
5/15
HCC/H CF40160B-40161B-40162-40163
DYNAMIC ELECTRICAL CHARACTERISTICS (T
=25oC, CL=50pF,RL= 200 KΩ,
amb
typic al temperat ure coef f ic ent for all VDDvalues is 03 %/oC, all input rise and fall t i mes = 20 ns)
SymbolParameter
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
setup
Propagation Delay Time
Clock to Q
Propagation Delay Time
Clock to C
OUT
Propagation Delay Time
TE to C
OUT
Setup Time
Data to Clock
t
setup
Setup Time
Load to Clock
t
setup
Setup Time
PE or TE to Clock
t
t
t
t
t
hold
THL
TLH
t
f
rtf
PHL
Hold Time50
Transition Time5100200
CLock Input Pulse Width517085
W
Maximum Clock Input Frequency523
CL
Clock Input Rise or Fall Time *200
Propagation Delay Time (40160B, 40161B)
Clear to Q
t
setup
Setup Time (40162B, 40163B)
Clear to Clock
t
hold
Hold Time (40162B, 40163B)
Clear to Clock
t
rem
t
Clear Removal Time (40162B, 40163B)5200100
Clear Input Pulse Width Low Level (40160B,
W
40161B)
* If more than oneunitis cascated in theparallelclocked application, tr shouldbe madeless than or equal to thesum ofthe fixedpropagation delay
at 50 pF and thetransition timeof thecarry output drivingstagefor the estimated capacitance
Test ConditionsValue
(V) Min.Typ.Max.
V
DD
5200400
1080160
1560120
5225450
1095190
1570140
5125250
1055110
154080
5240120
109045
156030
5240120
109045
156030
5340170
1014070
1510050
100
150
1050100
154080
107035
155025
105.58.5
15812
5250500
10110220
1580160
5340170
1014070
1510050
50
100
150
1010050
157035
517085
107035
155025
70
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
6/15
HCC/ HCF40160B-40161B-40162B-40163B
Output Low (sink) Current Characteristics
Typical Propagation Delay Time vs Load Capacitance
Output High (source) Current Characteristics
Typical Transition Time vs Load Capacitance
Typical Dynamic Power Dissipation vs Input Frequency
7/15
HCC/H CF40160B-40161B-40162-40163
TYPICAL APPLI CA TI ONS
Detail of Flip-flops For 40160B And 40161B (Asynchronous Clear)
Detail of Flip-flops For 40162B And 40163B (Synchronous Clear)
8/15
HCC/ HCF40160B-40161B-40162B-40163B
Cascading Counter Packages In The Parallel-Clocked Mode
Cascading Counter Packages In The Ripple-Clocked Mode
Information furnished is believed to be accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted byimplication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronicsproducts are not authorized foruse ascritical componentsin life support devices orsystems without express
written approval of SGS-THOMSON Microelectonics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
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