TATIVE STANDARD NO. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF”B”
SERIESCMOS DEVICES”
HCC/HCF4015B
INPUT/PARALLEL OUTPUT
EY
(Plastic Package)F(Ceramic Frit Seal Package)
M1
(MicroPackage)
ORDERCODES :
HCC4015BFHCF4015BM1
HCF4015BEYHCF4015BC1
(Plastic Chip Carrier)
C1
DESCRIPTION
TheHCC4015B(extended temperature range) and
HCF4015B (intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package and plastic
micropackage.
TheHCC/HCF4015Bconsistsof two identical, inde-
pendent,4-stageserial-input/parallel-output registers.
Eachregister has independent CLOCK and RESET
inputsas well asa singleserialDATAinput. ”Q” outputsareavailablefromeachofthefourstagesonboth
registers.AllregisterstagesareD-type,master-slave
flip-flops. Thelogic level present attheDATA input is
transferredintothefirstregisterstageandshiftedover
onestageateach positive-going clocktransition. Resettingofallstagesisaccomplishedby ahighlevelon
the reset line. Register expansion to 8 stages using
one HCC/HCF4015B package, or to more than 8
stagesusingadditionalHCC/HCF4015B’sispossible.
PIN CON NECTIONS
June 1989
1/12
HCC/HCF4015B
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMU M RA TI NGS
SymbolParame terVal ueUnit
V
*Supply Voltage : HCC Types
DD
HCF Types
V
Input Voltage– 0.5 to VDD+ 0.5V
i
I
DC Input Current (any one input)± 10mA
I
P
Total Power Dissipation (per package)
tot
Dissipation per Output Transistor
for T
T
Operating Temperature : HCC Types
op
= Full Package-temperature Range
op
HCF Types
T
Stresses above those listed under ”Absolute Maximum Ratings ”may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device
reliability.
* All voltage values are referred to VSSpin voltage.
typical temperature coefficient forall VDDvalues is 0.3 %/°C, all inputrise and fall times = 20ns)
SymbolParamet e r
Test Conditions
V
(V) Min.Typ.Max.
DD
CLOCKED OPERATION
t
PLH,tPHL
Propagation Delay Time
(carry out or decoded out lines)
5160320
1080160
1560120
t
THL,tTLH
Transition Time
(carry out or decoded out lines)
5100200
1050100
154080
f
CL
Maximum Clock Input Frequency536
10612
158.517
t
Clock Pulse Width518090
W
108040
155025
t
*Clock Input Rise or Fall Time515
r,tf
1015
1515
t
se tu p
Data Setup Time57035
104020
153015
RESET OPERATION
t
PLH,tPHL
Propagation Delay Time5200400
10100200
1580160
t
Reset Pulse Width5200100
W
108040
156030
* Ifmorethan unitis cascaded inthe parallelclocked application, trCLshould bemade less thanorequal tothe sumof thefixed propagation delay
at 15pFand the transition time of the carry output driving stagefor the estimated capacitive load.
Information furnished is believed tobe accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may results from its use. No
license isgranted by implicationor otherwise underany patent or patentrights of SGS-THOMSON Microelectronics.Specificationsmentioned
in this publication are subject to changewithout notice. This publication supersedes andreplaces all information previously supplied.
SGS-THOMSON Microelectronicsproductsare notauthorizedforuse ascritical componentsin life supportdevices orsystems withoutexpress
written approval of SGS-THOMSON Microelectonics.
1994 SGS-THOMSON Microelectronics - All RightsReserved
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
SGS-THOMSON MicroelectronicsGROUP OF COMPANIES
12/12
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