SGS Thomson Microelectronics FC106 Datasheet



FEATURES

FC106

Fibre Channel Transceiver 1.0625 GBaud

PRELIMINARY DATA

■ Serial Link Transceiver

●

serializer and deserializer

● implementing the Fibre Channel FC0

and FC1 layers

■ Direct support for 1.0625 GBaud Fibre

Channel (ANSI X3.230-1994) rates

■ Fibre Channel 10-bit Interface (ANSI

TR/X3.18-199X)

■ Direct interfaces to optical tranceivers

■ Plesiochronous mode operation

● transmitter and receiver clock

frequencies may differ by up to 100 ppm

■ Integrated Fibre Channel 8b/10b

encode/decode (optional use through
JTAG)

■ Byte and word synchronization of

incoming serial stream

■ Supports any DC-balanced encoding

scheme

■ Internal Loop-Back for Self-Test

■ Random Pattern Auto-Test

■ Optional integrated impedance

adaptation to transmission line
characteristics (50 or 75 ohms)

■ TTL compatible parallel I/O’s

■ JTAG Test Access Port

■ 0.35

CMOS Technology for low cost

µ

and low power

■ PQFP package available in two sizes:

14x14 mm (FC106/14) or 10x10 mm
(FC106/10)

Receive
Byte
Clock

8 bit / 10 bit

DECODER

(optional)

DESERIALIZER

CLOCK RECOVERY

BYTE AND WORD

ALIGNEMENT

10 bits

8 bit / 10bit
ENCODER

SERIALIZER
AND CLOCK

FREQUENCY

MULTIPLICATION

REFCLK

(optional)

FC 106

1.0625 Gbaud

Serial data over copper

or optical cables

APPLICATIONS

■ Fibre Channel Arbitrated Loop

■ Fibre Channel fabric

■ Transmission schemes encoding

bytes as 10-bit characters to form a
DC-balanced stream

■ High performance backplane

interconnect

Parallel Interface

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September 98 Revision 1.2

FC106

Table of Contents

1 General Description - - - - - - - - - - ------------4

2 Interface Diagram - - - - - - -----------------6

3 Functional Description - - - - - ---------------7

3.1 Block diagram - - - - - ------------------8

3.2 Input latches - - - - - - - - - - - - - - - - - - - - - - - - 8

3.3 8bit/10bit Encoder/Decoder - - - --------------9

3.4 DLL clock generator - - - - - - - - - -----------9

3.5 Serializer functional description and reference clock -----9

3.6 Serializer latches and XOR-tree - - - - - - - ------- 10

3.7 Serial input multiplexer - - - - - - - - - - - -------10

3.8 Deserializer functional description -------------10

3.9 Bit alignment - - - - - - - - - - - - - - - - - - - - - - - 11

3.10 Byte and word alignment - - - ------------- 12

3.11 Clock recovery - - - - - - - - - - - - - - - - - - - - - 12

3.12 Serial input-output buffer - - - ------------- 13

3.13 I/O impedance control ------------------14

3.14 Self-test ------------------------- 15

4 Serial I/O Electrical Model - ----------------16

5 Electrical Specifications - - - - - - - - - - - - - ----- 17

5.1 Absolute maximum ratings - - - - - - - - -------- 17

5.2 Operating conditions - - - - - --------------17

5.3 DC characteristics - - - - - - - - - - - - - ------- 18

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FC106

6 Timing Specifications - - - ----------------- 20

6.1 Transmit interface timing and latency - - - - - - - ----20

6.2 Receive interface timing - ----------------21

6.2.1 Receive clock timing and latency - - - - - - - ----21

6.2.2 Receive interface timing - - - - - - - - ------- 23

6.3 Serial Input/output AC characteristics - - - - - - - ----24

7 FC106 Pin Description - - - - - - - - - ---------- 25

7.1 Pin summary - - - - - - - - - - ------------- 25

7.2 Pin functions - - - - - - - - - - - - - - - - - - - - - - - 26

8 Package Specifications ------------------- 29

8.1 FC106 64-pin PQFP pinout - - - -------------29

8.2 FC106 64-pin Quad Flat-pack package dimensions ----30

8.2.1 FC106/14: 14x14 mm package dimensions - - ----30

8.2.2 FC106/10: 10x10 mm package dimensions - - ----31

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FC106

1 General Description

The FC106 Fibre Channel transceiver chip implements the lower layer protocols of the ANSI
X3.230-1994 Fibre Channel standard. The Fibre Channel standard specifies the mapping of
various upper layer protocols (ULP) such as SCSI, IP and HiPPI to a common lower layer
protocol, together with appropriate electrical and optical high performance specifications.
Fibre Channel provides a channel over which concurrent communication of a variety of
ULP’s may exist on a single interconnect between workstations, mainframes and
supercomputers, and provides a connection to mass storage devices and other peripherals.

The FC106 implements the Fibre Channel electrical transceiver physical layer specification
for 1.0625 Gbit/s. At this frequency, the Fibre Channel delivers 100 MByte/s of data
bandwidth over a twin coaxial or twin optical fibre cable. This bandwidth equals or exceeds
most bus bandwidths. The FC106 chip performs the high speed serialization and
deserialization function that makes bus-bandwidth, serial communication possible. This chip
can drive electrical cables directly or it can interface with suitable optical modules. Figure 1.1
shows the different connections.

Figure 1.1 FC106 chip connections

1.0625 Gb/s

System 1 System 2

REFCLK (1)

Fibre

Channel

Controller

I/O Bus

10 bits

SerialDataover copper

or optical cables

FC106

REFCLK (2)

FC106

10 bits

Fibre

Channel

Controller

I/O Bus

The parallel interface on the FC106 is compatible with the 10-Bit Interface Specification
(ANSI TR/X3.18-1998) which defines a common, standard signaling interface between the
Fibre Channel Physical and Protocol layers. In addition, the FC106 can be used for all other
proprietary serial links transmitting data as 10-bit encoded characters.

The FC106 incorporates an impedance adaptor circuit (set by the pins ZC+, ZC-) to ensure
high quality adaptation to the transmission line characteristic impedance.This feature is
optional and the user can keep external adaptation for compatibility reasons.

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FC106

The FC106 integrates a loop-back path for system-level test purposes. It also includes a
self-test capability in which random patterns are transmitted through the internal loop-back
path and compared after reception.

The FC106 is implemented in a standard digital 0.35µ CMOS process. Its typical power
consumption is 0.4 Watts (not including the power required to drive the TTL parallel output
port, which is in the 0.1 Watt range for output capacitive loads of 10 pF per pin).

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FC106

2 Interface Diagram

Figure 2.1 Interface diagram

10

TX[0:9]

T

T

T

C

R

M

K

S

S

Test

transmitter

T

D

I

T
DORSA

T
E

T

N

REFCLK

EWRAP
EN_CDET

FC
Protocol
Device

[106.25 MHz]

COM_DET

RBC[0:1]

RX[0:9]

2

10

FC106

receiver

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FC106

3 Functional Description

The FC106 provides all required signals in the 10-Bit Interface Specification for Fibre
Channel. It also provides 10 pins for additional functions (these pins are marked in the
following by *). The additional functions are:

impedance control (ZC+*, ZC-*)

•

• production test through JTAG(TCK

self-test of the chip (AT*)

•

(*)

-TRSTN(*)-TMS(*)-TDI(*)-TDO(*)- TEST ENABLE(*))

• reset pin (RS) (but note that another reset is automatically generated in the chip during

power on).

In addition to implementing the Fibre Channel standard, the FC106 is adaptable through the
JTAGpath to the transmission of any sequence of 10-bit encoded characters at rates varying
between 1 and 1.1 Gbaud.

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FC106

3.1 Block diagram

Figure 3.1 Block diagram

TCK(*)
TRSTN(*)

TMS(*)

TDI(*)
TDO(*)
TEST ENABLE(*)

TX [0:9]

JTAG

CONTROL

ENC

SERIALIZER

XOR
Tree

TX-

transmitter

TX+

8b/10b

encoder

RCB[0:1]

AT (*)

RS (*)

REFCLK

SELF
TEST

ENC

RX[0:9]

3.2 Input latches

8b/10b

decoder

EN_CDET

DLL clock generator

Clock Recovery

Word
Align­ment

DESERIALIZER

COM_DET

Bit
Align­ment

ZC+(*)

ZC

setting

ZC-(*)

RX-

receiver

RX+

(*)Test signals not

included in FCS

10-bit interface

EWRAP

The transmitter accepts 10-bit wide TTL parallel data at inputs TX[0:9]. The user-provided
reference clock signal REFCLK is also used as the transmit byte clock. The TX[0:9] and
REFCLK signals must be properly aligned, as shown in Section 6.1:

timing and latency

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on page 20.

Revision 1.2

Transmit interface

FC106

3.3 8bit/10bit Encoder/Decoder

In normal operation mode, the FC106 accepts 10-bit pre-encoded data, and provides to the
application, 10-bit encoded data (as specified in the ANSI 10-bit Interface Specification).

In addition, the FC106 contains an 8b/10b encoder/decoder, which can be inserted into the
data flow. The selection of this mode is made through the JTAG path. In this mode, the
FC106 accepts and delivers bytes on 9 bits (8 bits of data on TX/RX[0:7] and 1 bit on TX/
RX[8] which is used to differentiate control characters). The timings of the parallel I/O ports
are identical in both modes: using the 8b/10b encoder/decoder increases the transmission
latency by 2 byte clock periods (equivalent toa4meterincrease of the cable length).

3.4 DLL clock generator

The DelayLocked Loop (DLL) block generates the internal clocks. These are required by the
transmitter section to perform its function, and by the receiver block to generate the
reference clocks which are used to recover the serial data input frequency. These clocks are
based on the user supplied reference byte clock REFCLK. This clock is multiplied by 10 to
generate the required serial output data rate. No external components are required to
operate the DLL Clock Generator.

3.5 Serializer functional description and reference
clock

The FC106 serializer performs the serialization of 10-bit pre-encoded parallel data at
signaling rates up to 1.0625 Gb/s. System design is simplified by the integration into the chip
of a block performing clock multiplication from the parallel data clock.

It accepts 10-bit encoded parallel data words which are clocked into the device at 1/10 of the
signaling rate. For Fibre Channel use, data should be encoded for transmission using the
8B/10B block code described in the Fibre Channel specification. The FC106 serializes the
input data and transmits it at a signaling rate of 10 times the frequency of the REFCLK input.
The device includes a Delay-Locked-Loop based clock multiplier that generates the

1.0625 Gbaud clocks. This DLL is fully monolithic and requires no external components. Its

acquisition time, at power-up, is less than 16 microseconds.
The FC106 loads parallel data on the rising edge of REFCLK. The delay through the FC106

from loading the code-group to the transmission of the first bit of the code-group on the TX+,
TX- pair, is 17.4 ns with an extra 9.4 ns if the 8b10b encoding function is enabled.

A loop-back-mode signal EWRAP is provided allowing internal dynamic self-test of the chip.
When EWRAP is low, the output of the transmitter is sent to the TX+ and TX- output pins,
and the input of the receiver is driven by the signals entered through the RX+ and RX- pins.

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FC106

When EWRAP is high, the output of the transmitter is sent directly to the input of the
receiver.

3.6 Serializer latches and XOR-tree

The parallel data words TX[0:9] are individually sampled using the clocks provided by the
DLL Clock Generator. The outputs of these serializer latches are merged through an
Exclusive-OR tree, in order to generate the output data bit streams.

3.7 Serial input multiplexer

The Input Multiplexer supports the internal loopback of the high speed serial signal for test
purposes.

In normal operation, EWRAP is set low.The serial output data stream is placed at TX+/TX­outputs, and the serial data accepted at RX+/RX- is transmitted to the deserializer block.

When wrap-mode is activated by setting EWRAP high, the serial data generated by the
serializer block is internally wrapped to the input of the deserializer block.

3.8 Deserializer functional description

The FC106 deserializer operates at signaling rates up to 1.0625 Gb/s, as specified in the
Fibre Channel standard. It extracts the clock and retimes the data from the serial bit stream.
The serial bit stream should be encoded as 10-bit characters (for example the 8B/10B code
for FibreChannel) which provide a transition density greater than 10%. The retimed serial bit
stream is converted into a 10-bit parallel output word. The FC106 has internal DLL based
clock recovery circuit which requires no external components.

When the DLL of the serializer clock multiplier is locked to the expected data rate (defined by
REFCLK), the retiming acquisition time (to lock to the incoming serial data stream) is less
than 3 microseconds.

The FC106 provides byte and data word alignment using a comma symbol recognition
mechanism.

The 7-bit comma symbol is defined in Fibre Channel specification as a [0:6]= 0011111. This
pattern is only contained within special characters known as K28.1, K28.5 and K28.7
defined specifically for synchronization by Fibre Channel.

Serial data is received on the RX+ and RX- pins. The DLL clock recovery circuit will lock to
the data stream if the clock to be recovered is within 0.01% of the expected data rate. For

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